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Searched refs:QCA953X_PLL_DDR_CONFIG_REG (Results 1 – 3 of 3) sorted by relevance

/rk3399_rockchip-uboot/arch/mips/mach-ath79/qca953x/
H A Dlowlevel_init.S146 sw t1, QCA953X_PLL_DDR_CONFIG_REG(t0)
159 lw t1, QCA953X_PLL_DDR_CONFIG_REG(t0)
162 sw t1, QCA953X_PLL_DDR_CONFIG_REG(t0)
H A Dclk.c65 val = readl(regs + QCA953X_PLL_DDR_CONFIG_REG); in get_clocks()
/rk3399_rockchip-uboot/arch/mips/mach-ath79/include/mach/
H A Dar71xx_regs.h421 #define QCA953X_PLL_DDR_CONFIG_REG 0x04 macro