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Searched refs:QCA953X_PLL_CLK_CTRL_REG (Results 1 – 3 of 3) sorted by relevance

/rk3399_rockchip-uboot/arch/mips/mach-ath79/qca953x/
H A Dlowlevel_init.S136 lw t1, QCA953X_PLL_CLK_CTRL_REG(t0)
138 sw t1, QCA953X_PLL_CLK_CTRL_REG(t0)
150 sw t1, QCA953X_PLL_CLK_CTRL_REG(t0)
165 lw t1, QCA953X_PLL_CLK_CTRL_REG(t0)
168 sw t1, QCA953X_PLL_CLK_CTRL_REG(t0)
H A Dclk.c41 ctrl = readl(regs + QCA953X_PLL_CLK_CTRL_REG); in get_clocks()
/rk3399_rockchip-uboot/arch/mips/mach-ath79/include/mach/
H A Dar71xx_regs.h422 #define QCA953X_PLL_CLK_CTRL_REG 0x08 macro