Searched refs:PMU_BASE_ADDR (Results 1 – 4 of 4) sorted by relevance
| /rk3399_rockchip-uboot/arch/arm/mach-rockchip/rk3562/ |
| H A D | rk3562.c | 55 #define PMU_BASE_ADDR 0xff258000 macro
558 rk_clrreg(PMU_BASE_ADDR + PMU2_PWR_GATE_SFTCON0, in qos_priority_init()
566 readl(PMU_BASE_ADDR + PMU2_PWR_GATE_STS0)); in qos_priority_init()
569 } while (readl(PMU_BASE_ADDR + PMU2_PWR_GATE_STS0) & in qos_priority_init()
573 rk_clrreg(PMU_BASE_ADDR + PMU2_MEM_SD_SFTCON0, BIT(i)); in qos_priority_init()
576 rk_clrreg(PMU_BASE_ADDR + PMU2_BIU_IDLE_SFTCON0, in qos_priority_init()
586 readl(PMU_BASE_ADDR + PMU2_BIU_IDLE_ACK_STS0)); in qos_priority_init()
589 } while (readl(PMU_BASE_ADDR + PMU2_BIU_IDLE_ACK_STS0) & in qos_priority_init()
599 readl(PMU_BASE_ADDR + PMU2_BIT_IDLE_STS0)); in qos_priority_init()
602 } while (readl(PMU_BASE_ADDR + PMU2_BIT_IDLE_STS0) & in qos_priority_init()
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| /rk3399_rockchip-uboot/arch/arm/mach-rockchip/rv1126/ |
| H A D | rv1126.c | 56 #define PMU_BASE_ADDR 0xff3e0000 macro
624 writel(0xffffffff, PMU_BASE_ADDR + PMU_NOC_AUTO_CON0); in arch_cpu_init()
625 writel(0xffffffff, PMU_BASE_ADDR + PMU_NOC_AUTO_CON1); in arch_cpu_init()
652 writel(0xffff0000, PMU_BASE_ADDR + PMU_PWR_GATE_SFTCON); in arch_cpu_init()
657 } while (delay && readl(PMU_BASE_ADDR + PMU_PWR_DWN_ST)); in arch_cpu_init()
660 writel(0xffff0000, PMU_BASE_ADDR + PMU_BUS_IDLE_SFTCON(0)); in arch_cpu_init()
661 writel(0xffff0000, PMU_BASE_ADDR + PMU_BUS_IDLE_SFTCON(1)); in arch_cpu_init()
668 } while (delay && readl(PMU_BASE_ADDR + PMU_BUS_IDLE_ACK)); in arch_cpu_init()
675 } while (delay && readl(PMU_BASE_ADDR + PMU_BUS_IDLE_ST)); in arch_cpu_init()
677 pd_st = readl(PMU_BASE_ADDR + PMU_PWR_DWN_ST); in arch_cpu_init()
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| /rk3399_rockchip-uboot/arch/arm/mach-rockchip/rk3568/ |
| H A D | rk3568.c | 39 #define PMU_BASE_ADDR 0xfdd90000 macro
822 PMU_BASE_ADDR + PMU_PWR_GATE_SFTCON); in qos_priority_init()
831 } while (readl(PMU_BASE_ADDR + PMU_PWR_DWN_ST) & ~(BIT(0) | BIT(1))); in qos_priority_init()
835 PMU_BASE_ADDR + PMU_BUS_IDLE_SFTCON0); in qos_priority_init()
846 } while (readl(PMU_BASE_ADDR + PMU_BUS_IDLE_ACK) & ~(BIT(1) | BIT(2))); in qos_priority_init()
857 } while (readl(PMU_BASE_ADDR + PMU_BUS_IDLE_ST) & ~(BIT(1) | BIT(2))); in qos_priority_init()
870 writel(0xffffffff, PMU_BASE_ADDR + PMU_NOC_AUTO_CON0); in arch_cpu_init()
871 writel(0x000f000f, PMU_BASE_ADDR + PMU_NOC_AUTO_CON1); in arch_cpu_init()
925 writel(0xffffffff, PMU_BASE_ADDR + PMU_NOC_AUTO_CON0); in arch_cpu_init()
926 writel(0x000f000f, PMU_BASE_ADDR + PMU_NOC_AUTO_CON1); in arch_cpu_init()
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| /rk3399_rockchip-uboot/drivers/video/rk_eink/ |
| H A D | rk_ebc_tcon.c | 251 #define PMU_BASE_ADDR 0xfdd90000 macro
299 writel(pd_reg, PMU_BASE_ADDR + PMU_PWR_GATE_SFTCON); in ebc_power_domain()
308 } while (readl(PMU_BASE_ADDR + PMU_PWR_DWN_ST) & pd_stat); in ebc_power_domain()
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