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Searched refs:PLL_PPLL (Results 1 – 16 of 16) sorted by relevance

/rk3399_rockchip-uboot/include/dt-bindings/clock/
H A Drk1808-cru.h12 #define PLL_PPLL 6 macro
H A Drk3528-cru.h16 #define PLL_PPLL 4 macro
H A Drk3399-cru.h343 #define PLL_PPLL 1 macro
H A Drk3568-cru.h13 #define PLL_PPLL 1 macro
H A Drockchip,rk3576-cru.h19 #define PLL_PPLL 9 macro
H A Drk3588-cru.h21 #define PLL_PPLL 9 macro
/rk3399_rockchip-uboot/drivers/clk/rockchip/
H A Dclk_rk1808.c63 RK1808_CLK_DUMP(PLL_PPLL, "ppll", true),
90 [PPLL] = PLL(pll_rk3036, PLL_PPLL, RK1808_PMU_PLL_CON(0),
918 case PLL_PPLL: in rk1808_clk_get_rate()
1003 case PLL_PPLL: in rk1808_clk_set_rate()
H A Dclk_rk3528.c75 [PPLL] = PLL(pll_rk3328, PLL_PPLL, RK3528_PCIE_PLL_CON(32),
127 RK3528_CLK_DUMP(PLL_PPLL, "ppll"),
1358 case PLL_PPLL: in rk3528_clk_get_rate()
1480 case PLL_PPLL: in rk3528_clk_set_rate()
H A Dclk_rk3588.c66 [PPLL] = PLL(pll_rk3588, PLL_PPLL, RK3588_PMU_PLL_CON(128),
87 RK3588_CLK_DUMP(PLL_PPLL, "ppll", true),
1587 case PLL_PPLL: in rk3588_clk_get_rate()
1738 case PLL_PPLL: in rk3588_clk_set_rate()
H A Dclk_rk3576.c79 [PPLL] = PLL(pll_rk3588, PLL_PPLL, RK3576_PMU_PLL_CON(128),
98 RK3576_CLK_DUMP(PLL_PPLL, "ppll", true),
2094 case PLL_PPLL: in rk3576_clk_get_rate()
2260 case PLL_PPLL: in rk3576_clk_set_rate()
H A Dclk_rk3568.c80 [PPLL] = PLL(pll_rk3328, PLL_PPLL, RK3568_PMU_PLL_CON(0),
102 RK3568_CLK_DUMP(PLL_PPLL, "ppll", false),
381 case PLL_PPLL: in rk3568_pmuclk_get_rate()
421 case PLL_PPLL: in rk3568_pmuclk_set_rate()
/rk3399_rockchip-uboot/arch/arm/dts/
H A Drk1808.dtsi300 <&cru PLL_PPLL>, <&cru ARMCLK>,
H A Drk3399.dtsi1257 assigned-clocks = <&pmucru PLL_PPLL>;
H A Drk3528.dtsi696 <&cru PLL_PPLL>,
H A Drk3588s.dtsi515 <&cru PLL_PPLL>, <&cru PLL_CPLL>,
H A Drk3568.dtsi562 <&pmucru CLK_RTC_32K>, <&pmucru PLL_PPLL>,