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Searched refs:PLLREFE_BASE_DIVP (Results 1 – 1 of 1) sorted by relevance

/rk3399_rockchip-uboot/arch/arm/mach-tegra/tegra210/
H A Dclock.c1076 #define PLLREFE_BASE_DIVP(p) (((p) & 0x1f) << 16) macro
1098 PLLREFE_BASE_DIVP(0) | in tegra_pllref_enable()