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Searched refs:PLLE_SS_CNTL_INTERP_RESET (Results 1 – 4 of 4) sorted by relevance

/rk3399_rockchip-uboot/arch/arm/mach-tegra/tegra20/
H A Dclock.c625 #define PLLE_SS_CNTL_INTERP_RESET (1 << 11) macro
712 value |= PLLE_SS_CNTL_SSCBYP | PLLE_SS_CNTL_INTERP_RESET | in tegra_plle_enable()
743 value &= ~PLLE_SS_CNTL_INTERP_RESET; in tegra_plle_enable()
/rk3399_rockchip-uboot/arch/arm/mach-tegra/tegra30/
H A Dclock.c654 #define PLLE_SS_CNTL_INTERP_RESET (1 << 11) macro
758 value |= PLLE_SS_CNTL_SSCBYP | PLLE_SS_CNTL_INTERP_RESET | in tegra_plle_enable()
789 value &= ~PLLE_SS_CNTL_INTERP_RESET; in tegra_plle_enable()
/rk3399_rockchip-uboot/arch/arm/mach-tegra/tegra124/
H A Dclock.c939 #define PLLE_SS_CNTL_INTERP_RESET (1 << 11) macro
990 value |= PLLE_SS_CNTL_SSCBYP | PLLE_SS_CNTL_INTERP_RESET | in tegra_plle_enable()
1034 value &= ~PLLE_SS_CNTL_INTERP_RESET; in tegra_plle_enable()
/rk3399_rockchip-uboot/arch/arm/mach-tegra/tegra210/
H A Dclock.c1125 #define PLLE_SS_CNTL_INTERP_RESET (1 << 11) macro
1236 value &= ~PLLE_SS_CNTL_INTERP_RESET; in tegra_plle_enable()