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Searched refs:PLLE_MISC_SETUP_BASE (Results 1 – 2 of 2) sorted by relevance

/rk3399_rockchip-uboot/arch/arm/mach-tegra/tegra20/
H A Dclock.c638 #define PLLE_MISC_SETUP_BASE(x) (((x) & 0xffff) << 16) macro
692 value &= ~PLLE_MISC_SETUP_BASE(0xffff); in tegra_plle_enable()
706 value |= PLLE_MISC_SETUP_BASE(0x7); in tegra_plle_enable()
/rk3399_rockchip-uboot/arch/arm/mach-tegra/tegra30/
H A Dclock.c667 #define PLLE_MISC_SETUP_BASE(x) (((x) & 0xffff) << 16) macro
721 value &= ~PLLE_MISC_SETUP_BASE(0xffff); in tegra_plle_enable()
752 value |= PLLE_MISC_SETUP_BASE(0x7); in tegra_plle_enable()