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Searched refs:PLLE_BASE_PLDIV_CML (Results 1 – 4 of 4) sorted by relevance

/rk3399_rockchip-uboot/arch/arm/mach-tegra/tegra30/
H A Dclock.c661 #define PLLE_BASE_PLDIV_CML(x) (((x) & 0xf) << 24) macro
737 value &= ~PLLE_BASE_PLDIV_CML(0x0f); in tegra_plle_enable()
738 value |= PLLE_BASE_PLDIV_CML(cpcon); in tegra_plle_enable()
/rk3399_rockchip-uboot/arch/arm/mach-tegra/tegra124/
H A Dclock.c946 #define PLLE_BASE_PLDIV_CML(x) (((x) & 0xf) << 24) macro
995 value &= ~PLLE_BASE_PLDIV_CML(0xf); in tegra_plle_enable()
998 value |= PLLE_BASE_PLDIV_CML(cpcon); in tegra_plle_enable()
/rk3399_rockchip-uboot/arch/arm/mach-tegra/tegra210/
H A Dclock.c1131 #define PLLE_BASE_PLDIV_CML(x) (((x) & 0x1f) << 24) macro
1184 value &= ~PLLE_BASE_PLDIV_CML(0x1f); in tegra_plle_enable()
1187 value |= PLLE_BASE_PLDIV_CML(0xe); in tegra_plle_enable()
/rk3399_rockchip-uboot/arch/arm/mach-tegra/tegra20/
H A Dclock.c632 #define PLLE_BASE_PLDIV_CML(x) (((x) & 0xf) << 24) macro