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Searched refs:PLLE_BASE_ENABLE (Results 1 – 4 of 4) sorted by relevance

/rk3399_rockchip-uboot/arch/arm/mach-tegra/tegra20/
H A Dclock.c631 #define PLLE_BASE_ENABLE (1 << 30) macro
686 value &= ~PLLE_BASE_ENABLE; in tegra_plle_enable()
717 value |= PLLE_BASE_ENABLE_CML | PLLE_BASE_ENABLE; in tegra_plle_enable()
/rk3399_rockchip-uboot/arch/arm/mach-tegra/tegra30/
H A Dclock.c660 #define PLLE_BASE_ENABLE (1 << 30) macro
715 value &= ~PLLE_BASE_ENABLE; in tegra_plle_enable()
763 value |= PLLE_BASE_ENABLE_CML | PLLE_BASE_ENABLE; in tegra_plle_enable()
/rk3399_rockchip-uboot/arch/arm/mach-tegra/tegra124/
H A Dclock.c944 #define PLLE_BASE_ENABLE (1 << 30) macro
1006 value |= PLLE_BASE_ENABLE; in tegra_plle_enable()
/rk3399_rockchip-uboot/arch/arm/mach-tegra/tegra210/
H A Dclock.c1130 #define PLLE_BASE_ENABLE (1 << 31) macro
1200 value |= PLLE_BASE_ENABLE; in tegra_plle_enable()