Searched refs:PLLE_BASE (Results 1 – 4 of 4) sorted by relevance
| /rk3399_rockchip-uboot/arch/arm/mach-tegra/tegra30/ |
| H A D | clock.c | 658 #define PLLE_BASE 0x0e8 macro
713 value = readl(NV_PA_CLK_RST_BASE + PLLE_BASE); in tegra_plle_enable()
716 writel(value, NV_PA_CLK_RST_BASE + PLLE_BASE); in tegra_plle_enable()
735 value = readl(NV_PA_CLK_RST_BASE + PLLE_BASE); in tegra_plle_enable()
749 writel(value, NV_PA_CLK_RST_BASE + PLLE_BASE); in tegra_plle_enable()
762 value = readl(NV_PA_CLK_RST_BASE + PLLE_BASE); in tegra_plle_enable()
764 writel(value, NV_PA_CLK_RST_BASE + PLLE_BASE); in tegra_plle_enable()
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| /rk3399_rockchip-uboot/arch/arm/mach-tegra/tegra20/ |
| H A D | clock.c | 629 #define PLLE_BASE 0x0e8 macro
684 value = readl(NV_PA_CLK_RST_BASE + PLLE_BASE); in tegra_plle_enable()
687 writel(value, NV_PA_CLK_RST_BASE + PLLE_BASE); in tegra_plle_enable()
716 value = readl(NV_PA_CLK_RST_BASE + PLLE_BASE); in tegra_plle_enable()
718 writel(value, NV_PA_CLK_RST_BASE + PLLE_BASE); in tegra_plle_enable()
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| /rk3399_rockchip-uboot/arch/arm/mach-tegra/tegra124/ |
| H A D | clock.c | 943 #define PLLE_BASE 0x0e8 macro
967 value = readl(NV_PA_CLK_RST_BASE + PLLE_BASE); in tegra_plle_enable()
969 writel(value, NV_PA_CLK_RST_BASE + PLLE_BASE); in tegra_plle_enable()
994 value = readl(NV_PA_CLK_RST_BASE + PLLE_BASE); in tegra_plle_enable()
1001 writel(value, NV_PA_CLK_RST_BASE + PLLE_BASE); in tegra_plle_enable()
1005 value = readl(NV_PA_CLK_RST_BASE + PLLE_BASE); in tegra_plle_enable()
1007 writel(value, NV_PA_CLK_RST_BASE + PLLE_BASE); in tegra_plle_enable()
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| /rk3399_rockchip-uboot/arch/arm/mach-tegra/tegra210/ |
| H A D | clock.c | 1129 #define PLLE_BASE 0x0e8 macro
1183 value = readl(NV_PA_CLK_RST_BASE + PLLE_BASE); in tegra_plle_enable()
1190 writel(value, NV_PA_CLK_RST_BASE + PLLE_BASE); in tegra_plle_enable()
1199 value = readl(NV_PA_CLK_RST_BASE + PLLE_BASE); in tegra_plle_enable()
1201 writel(value, NV_PA_CLK_RST_BASE + PLLE_BASE); in tegra_plle_enable()
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