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Searched refs:PLLE_AUX_SEQ_ENABLE (Results 1 – 2 of 2) sorted by relevance

/rk3399_rockchip-uboot/arch/arm/mach-tegra/tegra124/
H A Dclock.c959 #define PLLE_AUX_SEQ_ENABLE (1 << 24) macro
973 value &= ~PLLE_AUX_SEQ_ENABLE; in tegra_plle_enable()
/rk3399_rockchip-uboot/arch/arm/mach-tegra/tegra210/
H A Dclock.c1147 #define PLLE_AUX_SEQ_ENABLE (1 << 24) macro
1255 value |= PLLE_AUX_SEQ_ENABLE; in tegra_plle_enable()