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Searched refs:PCTL2_MR_WR_BUSY (Results 1 – 2 of 2) sorted by relevance

/rk3399_rockchip-uboot/drivers/ram/rockchip/
H A Dsdram_pctl_px30.c23 while (readl(pctl_base + DDR_PCTL2_MRSTAT) & PCTL2_MR_WR_BUSY) in pctl_read_mr()
35 while (readl(pctl_base + DDR_PCTL2_MRSTAT) & PCTL2_MR_WR_BUSY) in pctl_write_mr()
51 while (readl(pctl_base + DDR_PCTL2_MRSTAT) & PCTL2_MR_WR_BUSY) in pctl_write_mr()
/rk3399_rockchip-uboot/arch/arm/include/asm/arch-rockchip/
H A Dsdram_pctl_px30.h167 #define PCTL2_MR_WR_BUSY BIT(0) macro