Searched refs:NUM_CHANNELS (Results 1 – 5 of 5) sorted by relevance
17 #define NUM_CHANNELS 1 /* number of channels */ macro76 uint32_t rcvn[NUM_CHANNELS][NUM_RANKS][NUM_BYTE_LANES];77 uint32_t rdqs[NUM_CHANNELS][NUM_RANKS][NUM_BYTE_LANES];78 uint32_t wdqs[NUM_CHANNELS][NUM_RANKS][NUM_BYTE_LANES];79 uint32_t wdq[NUM_CHANNELS][NUM_RANKS][NUM_BYTE_LANES];80 uint32_t vref[NUM_CHANNELS][NUM_BYTE_LANES];81 uint32_t wctl[NUM_CHANNELS][NUM_RANKS];82 uint32_t wcmd[NUM_CHANNELS];144 uint32_t channel_size[NUM_CHANNELS];145 uint32_t column_bits[NUM_CHANNELS];[all …]
17 NUM_CHANNELS = 3, enumerator28 struct sandbox_pwm_chan chan[NUM_CHANNELS];37 if (channel >= NUM_CHANNELS) in sandbox_pwm_set_config()52 if (channel >= NUM_CHANNELS) in sandbox_pwm_set_enable()66 if (channel >= NUM_CHANNELS) in sandbox_pwm_set_invert()
285 for (ch = 0; ch < NUM_CHANNELS; ch++) { in ddrphy_init()309 for (ch = 0; ch < NUM_CHANNELS; ch++) { in ddrphy_init()940 for (ch = 0; ch < NUM_CHANNELS; ch++) { in ddrphy_init()976 for (ch = 0; ch < NUM_CHANNELS; ch++) { in ddrphy_init()1012 for (ch = 0; ch < NUM_CHANNELS; ch++) { in ddrphy_init()1064 for (ch = 0; ch < NUM_CHANNELS; ch++) { in ddrphy_init()1362 for (ch = 0; ch < NUM_CHANNELS; ch++) { in restore_timings()1390 for (ch = 0; ch < NUM_CHANNELS; ch++) { in default_timings()1417 uint32_t final_delay[NUM_CHANNELS][NUM_BYTE_LANES]; in rcvn_cal()1451 for (ch = 0; ch < NUM_CHANNELS; ch++) { in rcvn_cal()[all …]
1359 for (channel = 0; channel < NUM_CHANNELS; channel++) { in clear_pointers()1456 for (channel = 0; channel < NUM_CHANNELS; channel++) { in print_timings()
99 #define NUM_CHANNELS GENMASK(14, 12) macro