xref: /rk3399_rockchip-uboot/drivers/video/drm/rk628/rk628_gvi.h (revision ab3bc87339b1566ceabcfb54995e11928492c356) 
1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3  * Copyright (c) 2024 Rockchip Electronics Co. Ltd.
4  *
5  * Author: Guochun Huang <hero.huang@rock-chips.com>
6  */
7 
8 #ifndef RK628_GVI_H
9 #define RK628_GVI_H
10 
11 #include "rk628.h"
12 
13 #define GVI_BASE					0x80000
14 #define HOSTREG(x)					((x) + GVI_BASE)
15 #define GVI_SYS_CTRL0					HOSTREG(0x0000)
16 #define GVI_SYS_CTRL1					HOSTREG(0x0004)
17 #define GVI_SYS_CTRL2					HOSTREG(0x0008)
18 #define GVI_SYS_CTRL3					HOSTREG(0x000c)
19 #define GVI_VERSION					HOSTREG(0x0010)
20 #define GVI_SYS_RST					HOSTREG(0x0014)
21 #define GVI_LINE_FLAG					HOSTREG(0x0018)
22 #define GVI_STATUS					HOSTREG(0x001c)
23 #define GVI_LOCKED_MASK					0x70
24 #define GVI_LOCKED_STATUS				0x40
25 #define GVI_PLL_LOCK_TIMEOUT				HOSTREG(0x0030)
26 #define GVI_HTPDN_TIMEOUT				HOSTREG(0x0034)
27 #define GVI_LOCKN_TIMEOUT				HOSTREG(0x0038)
28 #define GVI_WAIT_LOCKN					HOSTREG(0x003C)
29 #define GVI_WAIT_HTPDN					HOSTREG(0x0040)
30 #define GVI_INTR_EN					HOSTREG(0x0050)
31 #define GVI_INTR_CLR					HOSTREG(0x0054)
32 #define GVI_INTR_RAW_STATUS				HOSTREG(0x0058)
33 #define GVI_INTR_STATUS					HOSTREG(0x005c)
34 #define GVI_COLOR_BAR_CTRL				HOSTREG(0x0060)
35 #define GVI_COLOR_BAR_HTIMING0				HOSTREG(0x0070)
36 #define GVI_COLOR_BAR_HTIMING1				HOSTREG(0x0074)
37 #define GVI_COLOR_BAR_VTIMING0				HOSTREG(0x0078)
38 #define GVI_COLOR_BAR_VTIMING1				HOSTREG(0x007c)
39 
40 /* SYS_CTRL0 */
41 #define SYS_CTRL0_GVI_EN				BIT(0)
42 #define SYS_CTRL0_AUTO_GATING				BIT(1)
43 #define SYS_CTRL0_FRM_RST_EN				BIT(2)
44 #define SYS_CTRL0_FRM_RST_MODE				BIT(3)
45 #define SYS_CTRL0_LANE_NUM_MASK				GENMASK(7, 4)
46 #define SYS_CTRL0_LANE_NUM(x)				UPDATE(x, 7, 4)
47 #define SYS_CTRL0_BYTE_MODE_MASK			GENMASK(9, 8)
48 #define SYS_CTRL0_BYTE_MODE(x)				UPDATE(x, 9, 8)
49 #define SYS_CTRL0_SECTION_NUM_MASK			GENMASK(11, 10)
50 #define SYS_CTRL0_SECTION_NUM(x)			UPDATE(x, 11, 10)
51 #define SYS_CTRL0_CDR_ENDIAN_SWAP			BIT(12)
52 #define SYS_CTRL0_PACK_BYTE_SWAP			BIT(13)
53 #define SYS_CTRL0_PACK_ENDIAN_SWAP			BIT(14)
54 #define SYS_CTRL0_ENC8B10B_ENDIAN_SWAP			BIT(15)
55 #define SYS_CTRL0_CDR_EN				BIT(16)
56 #define SYS_CTRL0_ALN_EN				BIT(17)
57 #define SYS_CTRL0_NOR_EN				BIT(18)
58 #define SYS_CTRL0_ALN_NOR_MODE				BIT(19)
59 #define SYS_CTRL0_GVI_MASK				GENMASK(19, 16)
60 #define SYS_CTRL0_GVI_GN_EN(x)				UPDATE(x, 19, 16)
61 
62 #define SYS_CTRL0_SCRAMBLER_EN				BIT(20)
63 #define SYS_CTRL0_ENCODE8B10B_EN			BIT(21)
64 #define SYS_CTRL0_INIT_RD_EN				BIT(22)
65 #define SYS_CTRL0_INIT_RD_VALUE				BIT(23)
66 #define SYS_CTRL0_FORCE_HTPDN_EN			BIT(24)
67 #define SYS_CTRL0_FORCE_HTPDN_VALUE			BIT(25)
68 #define SYS_CTRL0_FORCE_PLL_EN				BIT(26)
69 #define SYS_CTRL0_FORCE_PLL_VALUE			BIT(27)
70 #define SYS_CTRL0_FORCE_LOCKN_EN			BIT(28)
71 #define SYS_CTRL0_FORCE_LOCKN_VALUE			BIT(29)
72 
73 /* SYS_CTRL1 */
74 #define SYS_CTRL1_COLOR_DEPTH_MASK			GENMASK(3, 0)
75 #define SYS_CTRL1_COLOR_DEPTH(x)			UPDATE(x, 3, 0)
76 #define SYS_CTRL1_DUAL_PIXEL_EN				BIT(4)
77 #define SYS_CTRL1_TIMING_ALIGN_EN			BIT(8)
78 #define SYS_CTRL1_LANE_ALIGN_EN				BIT(9)
79 
80 #define SYS_CTRL1_DUAL_PIXEL_SWAP			BIT(12)
81 #define SYS_CTRL1_RB_SWAP				BIT(13)
82 #define SYS_CTRL1_YC_SWAP				BIT(14)
83 #define SYS_CTRL1_WHOLE_FRM_EN				BIT(16)
84 #define SYS_CTRL1_NOR_PROTECT				BIT(17)
85 #define SYS_CTRL1_RD_WCNT_UPDATE			BIT(31)
86 
87 /* SYS_CTRL2 */
88 #define SYS_CTRL2_AFIFO_READ_THOLD_MASK			GENMASK(7, 0)
89 #define SYS_CTRL2_AFIFO_READ_THOLD(x)			UPDATE(x, 7, 0)
90 #define SYS_CTRL2_AFIFO_ALMOST_FULL_THOLD_MASK		GENMASK(23, 16)
91 #define SYS_CTRL2_AFIFO_ALMOST_FULL_THOLD(x)		UPDATE(x, 23, 16)
92 #define SYS_CTRL2_AFIFO_ALMOST_EMPTY_THOLD_MASK		GENMASK(31, 24)
93 #define SYS_CTRL2_AFIFO_ALMOST_EMPTY_THOLD(x)		UPDATE(x, 31, 24)
94 
95 /* SYS_CTRL3 */
96 #define SYS_CTRL3_LANE0_SEL_MASK			GENMASK(2, 0)
97 #define SYS_CTRL3_LANE0_SEL(x)				UPDATE(x, 2, 0)
98 #define SYS_CTRL3_LANE1_SEL_MASK			GENMASK(6, 4)
99 #define SYS_CTRL3_LANE1_SEL(x)				UPDATE(x, 6, 4)
100 #define SYS_CTRL3_LANE2_SEL_MASK			GENMASK(10, 8)
101 #define SYS_CTRL3_LANE2_SEL(x)				UPDATE(x, 10, 8)
102 #define SYS_CTRL3_LANE3_SEL_MASK			GENMASK(14, 12)
103 #define SYS_CTRL3_LANE3_SEL(x)				UPDATE(x, 14, 12)
104 #define SYS_CTRL3_LANE4_SEL_MASK			GENMASK(18, 16)
105 #define SYS_CTRL3_LANE4_SEL(x)				UPDATE(x, 18, 16)
106 #define SYS_CTRL3_LANE5_SEL_MASK			GENMASK(22, 20)
107 #define SYS_CTRL3_LANE5_SEL(x)				UPDATE(x, 22, 20)
108 #define SYS_CTRL3_LANE6_SEL_MASK			GENMASK(26, 24)
109 #define SYS_CTRL3_LANE6_SEL(x)				UPDATE(x, 26, 24)
110 #define SYS_CTRL3_LANE7_SEL_MASK			GENMASK(30, 28)
111 #define SYS_CTRL3_LANE7_SEL(x)				UPDATE(x, 30, 28)
112 /* VERSIION */
113 #define VERSION_VERSION(x)				UPDATE(x, 31, 0)
114 /* SYS_RESET*/
115 #define SYS_RST_SOFT_RST				BIT(0)
116 /* LINE_FLAG */
117 #define LINE_FLAG_LANE_FLAG0_MASK			GENMASK(15, 0)
118 #define LINE_FLAG_LANE_FLAG0(x)				UPDATE(x, 15, 0)
119 #define LINE_FLAG_LANE_FLAG1_MASK			GENMASK(31, 16)
120 #define LINE_FLAG_LANE_FLAG1(x)				UPDATE(x, 31, 16)
121 /* STATUS */
122 #define STATUS_HTDPN					BIT(4)
123 #define STATUS_LOCKN					BIT(5)
124 #define STATUS_PLL_LOCKN				BIT(6)
125 #define STATUS_AFIFO0_WCNT_MASK				GENMASK(23, 16)
126 #define STATUS_AFIFO0_WCNT(x)				UPDATE(x, 23, 16)
127 #define STATUS_AFIFO1_WCNT_MASK				GENMASK(31, 24)
128 #define STATUS_AFIFO1_WCNT(x)				UPDATE(x, 31, 24)
129 /* PLL_LTIMEOUT */
130 #define PLL_LOCK_TIMEOUT_PLL_LOCK_TIME_OUT_MASK		GENMASK(31, 0)
131 #define PLL_LOCK_TIMEOUT_PLL_LOCK_TIME_OUT(x)		UPDATE(x, 31, 0)
132 /* HTPDNEOUT */
133 #define HTPDN_TIMEOUT_HTPDN_TIME_OUT_MASK		GENMASK(31, 0)
134 #define HTPDN_TIMEOUT_HTPDN_TIME_OUT(x)			UPDATE(x, 31, 0)
135 /* LOCKNEOUT */
136 #define LOCKN_TIMEOUT_LOCKN_TIME_OUT_MASK		GENMASK(31, 0)
137 #define LOCKN_TIMEOUT_LOCKN_TIME_OUT(x)			UPDATE(x, 31, 0)
138 /* WAIT_LOCKN */
139 #define WAIT_LOCKN_WAIT_LOCKN_TIME_MASK			GENMASK(30, 0)
140 #define WAIT_LOCKN_WAIT_LOCKN_TIME(x)			UPDATE(x, 30, 0)
141 #define WAIT_LOCKN_WAIT_LOCKN_TIME_EN			BIT(31)
142 /* WAIT_HTPDN */
143 #define WAIT_HTPDN_WAIT_HTPDN_TIME_MASK			GENMASK(30, 0)
144 #define WAIT_HTPDN_WAIT_HTPDN_TIME(x)			UPDATE(x, 30, 0)
145 #define WAIT_HTPDN_WAIT_HTPDN_EN			BIT(31)
146 /* INTR_EN */
147 #define INTR_EN_INTR_FRM_ST_EN				BIT(0)
148 #define INTR_EN_INTR_PLL_LOCK_EN			BIT(1)
149 #define INTR_EN_INTR_HTPDN_EN				BIT(2)
150 #define INTR_EN_INTR_LOCKN_EN				BIT(3)
151 #define INTR_EN_INTR_PLL_TIMEOUT_EN			BIT(4)
152 #define INTR_EN_INTR_HTPDN_TIMEOUT_EN			BIT(5)
153 #define INTR_EN_INTR_LOCKN_TIMEOUT_EN			BIT(6)
154 #define INTR_EN_INTR_LINE_FLAG0_EN			BIT(8)
155 #define INTR_EN_INTR_LINE_FLAG1_EN			BIT(9)
156 #define INTR_EN_INTR_AFIFO_OVERFLOW_EN			BIT(10)
157 #define INTR_EN_INTR_AFIFO_UNDERFLOW_EN			BIT(11)
158 #define INTR_EN_INTR_PLL_ERR_EN				BIT(12)
159 #define INTR_EN_INTR_HTPDN_ERR_EN			BIT(13)
160 #define INTR_EN_INTR_LOCKN_ERR_EN			BIT(14)
161 /* INTR_CLR*/
162 #define INTR_CLR_INTR_FRM_ST_CLR			BIT(0)
163 #define INTR_CLR_INTR_PLL_LOCK_CLR			BIT(1)
164 #define INTR_CLR_INTR_HTPDN_CLR				BIT(2)
165 #define INTR_CLR_INTR_LOCKN_CLR				BIT(3)
166 #define INTR_CLR_INTR_PLL_TIMEOUT_CLR			BIT(4)
167 #define INTR_CLR_INTR_HTPDN_TIMEOUT_CLR			BIT(5)
168 #define INTR_CLR_INTR_LOCKN_TIMEOUT_CLR			BIT(6)
169 #define INTR_CLR_INTR_LINE_FLAG0_CLR			BIT(8)
170 #define INTR_CLR_INTR_LINE_FLAG1_CLR			BIT(9)
171 #define INTR_CLR_INTR_AFIFO_OVERFLOW_CLR		BIT(10)
172 #define INTR_CLR_INTR_AFIFO_UNDERFLOW_CLR		BIT(11)
173 #define INTR_CLR_INTR_PLL_ERR_CLR			BIT(12)
174 #define INTR_CLR_INTR_HTPDN_ERR_CLR			BIT(13)
175 #define INTR_CLR_INTR_LOCKN_ERR_CLR			BIT(14)
176 /* INTR_RAW_STATUS */
177 #define INTR_RAW_STATUS_RAW_INTR_FRM_ST			BIT(0)
178 #define INTR_RAW_STATUS_RAW_INTR_PLL_LOCK		BIT(1)
179 #define INTR_RAW_STATUS_RAW_INTR_HTPDN			BIT(2)
180 #define INTR_RAW_STATUS_RAW_INTR_LOCKN			BIT(3)
181 #define INTR_RAW_STATUS_RAW_INTR_PLL_TIMEOUT		BIT(4)
182 #define INTR_RAW_STATUS_RAW_INTR_HTPDN_TIMEOUT		BIT(5)
183 #define INTR_RAW_STATUS_RAW_INTR_LOCKN_TIMEOUT		BIT(6)
184 #define INTR_RAW_STATUS_RAW_INTR_LINE_FLAG0		BIT(8)
185 #define INTR_RAW_STATUS_RAW_INTR_LINE_FLAG1		BIT(9)
186 #define INTR_RAW_STATUS_RAW_INTR_AFIFO_OVERFLOW		BIT(10)
187 #define INTR_RAW_STATUS_RAW_INTR_AFIFO_UNDERFLOW	BIT(11)
188 #define INTR_RAW_STATUS_RAW_INTR_PLL_ERR		BIT(12)
189 #define INTR_RAW_STATUS_RAW_INTR_HTPDN_ERR		BIT(13)
190 #define INTR_RAW_STATUS_RAW_INTR_LOCKN_ERR		BIT(14)
191 /* INTR_STATUS */
192 #define INTR_STATUS_INTR_FRM_ST				BIT(0)
193 #define INTR_STATUS_INTR_PLL_LOCK			BIT(1)
194 #define INTR_STATUS_INTR_HTPDN				BIT(2)
195 #define INTR_STATUS_INTR_LOCKN				BIT(3)
196 #define INTR_STATUS_INTR_PLL_TIMEOUT			BIT(4)
197 #define INTR_STATUS_INTR_HTPDN_TIMEOUT			BIT(5)
198 #define INTR_STATUS_INTR_LOCKN_TIMEOUT			BIT(6)
199 #define INTR_STATUS_INTR_LINE_FLAG0			BIT(8)
200 #define INTR_STATUS_INTR_LINE_FLAG1			BIT(9)
201 #define INTR_STATUS_INTR_AFIFO_OVERFLOW			BIT(10)
202 #define INTR_STATUS_INTR_AFIFO_UNDERFLOW		BIT(11)
203 #define INTR_STATUS_INTR_PLL_ERR			BIT(12)
204 #define INTR_STATUS_INTR_HTPDN_ERR			BIT(13)
205 #define INTR_STATUS_INTR_LOCKN_ERR			BIT(14)
206 
207 /* COLOR_BAR_CTRL */
208 #define COLOR_BAR_EN					BIT(0)
209 
210 #define COLOR_DEPTH_RGB_YUV444_18BIT			0
211 #define COLOR_DEPTH_RGB_YUV444_24BIT			1
212 #define COLOR_DEPTH_RGB_YUV444_30BIT			2
213 #define COLOR_DEPTH_YUV422_16BIT			8
214 #define COLOR_DEPTH_YUV422_20BIT			9
215 
216 int rk628_gvi_parse(struct rk628 *rk628, ofnode gvi_np);
217 void rk628_gvi_enable(struct rk628 *rk628);
218 void rk628_gvi_disable(struct rk628 *rk628);
219 #endif
220