1 /*
2 * Copyright (c) 2021 Rockchip Electronics Co., Ltd
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6 #include <common.h>
7 #include <dm.h>
8 #include <fdt_support.h>
9 #include <misc.h>
10 #include <mmc.h>
11 #include <spl.h>
12 #include <asm/io.h>
13 #include <asm/arch/cpu.h>
14 #include <asm/arch/hardware.h>
15 #include <asm/arch/ioc_rk3588.h>
16 #include <asm/arch/rockchip_smccc.h>
17 #include <dt-bindings/clock/rk3588-cru.h>
18
19 DECLARE_GLOBAL_DATA_PTR;
20
21 #define FIREWALL_DDR_BASE 0xfe030000
22 #define FW_DDR_MST5_REG 0x54
23 #define FW_DDR_MST13_REG 0x74
24 #define FW_DDR_MST19_REG 0x8c
25 #define FW_DDR_MST21_REG 0x94
26 #define FW_DDR_MST26_REG 0xa8
27 #define FW_DDR_MST27_REG 0xac
28 #define FIREWALL_SYSMEM_BASE 0xfe038000
29 #define FW_SYSM_MST5_REG 0x54
30 #define FW_SYSM_MST13_REG 0x74
31 #define FW_SYSM_MST19_REG 0x8c
32 #define FW_SYSM_MST21_REG 0x94
33 #define FW_SYSM_MST26_REG 0xa8
34 #define FW_SYSM_MST27_REG 0xac
35 #define PMU1_SGRF_BASE 0xfd582000
36 #define PMU1_SGRF_SOC_CON0 0x0
37 #define PMU1_SGRF_SOC_CON6 0x18
38 #define PMU1_SGRF_SOC_CON7 0x1c
39 #define PMU1_SGRF_SOC_CON8 0x20
40 #define PMU1_SGRF_SOC_CON9 0x24
41 #define PMU1_SGRF_SOC_CON10 0x28
42 #define PMU1_SGRF_SOC_CON13 0x34
43 #define SYS_GRF_BASE 0xfd58c000
44 #define SYS_GRF_SOC_CON6 0x0318
45 #define USBGRF_BASE 0xfd5ac000
46 #define USB_GRF_USB3OTG0_CON1 0x001c
47 #define BUS_SGRF_BASE 0xfd586000
48 #define BUS_SGRF_SOC_CON2 0x08
49 #define BUS_SGRF_FIREWALL_CON18 0x288
50 #define PMU_BASE 0xfd8d0000
51 #define PMU_PWR_GATE_SFTCON1 0x8150
52
53 #define USB2PHY1_GRF_BASE 0xfd5d4000
54 #define USB2PHY2_GRF_BASE 0xfd5d8000
55 #define USB2PHY3_GRF_BASE 0xfd5dc000
56 #define USB2PHY_GRF_CON2 0x0008
57
58 #define PMU1_IOC_BASE 0xfd5f0000
59 #define PMU2_IOC_BASE 0xfd5f4000
60
61 #define BUS_IOC_BASE 0xfd5f8000
62 #define BUS_IOC_GPIO2A_IOMUX_SEL_L 0x40
63 #define BUS_IOC_GPIO2A_IOMUX_SEL_H 0x44
64 #define BUS_IOC_GPIO2B_IOMUX_SEL_L 0x48
65 #define BUS_IOC_GPIO2B_IOMUX_SEL_H 0x4c
66 #define BUS_IOC_GPIO2D_IOMUX_SEL_L 0x58
67 #define BUS_IOC_GPIO2D_IOMUX_SEL_H 0x5c
68 #define BUS_IOC_GPIO3A_IOMUX_SEL_L 0x60
69 #define BUS_IOC_GPIO3A_IOMUX_SEL_H 0x64
70 #define BUS_IOC_GPIO3C_IOMUX_SEL_H 0x74
71
72 #define VCCIO3_5_IOC_BASE 0xfd5fa000
73 #define IOC_VCCIO3_5_GPIO2A_DS_H 0x44
74 #define IOC_VCCIO3_5_GPIO2B_DS_L 0x48
75 #define IOC_VCCIO3_5_GPIO2B_DS_H 0x4c
76 #define IOC_VCCIO3_5_GPIO3A_DS_L 0x60
77 #define IOC_VCCIO3_5_GPIO3A_DS_H 0x64
78 #define IOC_VCCIO3_5_GPIO3C_DS_H 0x74
79
80 #define EMMC_IOC_BASE 0xfd5fd000
81 #define EMMC_IOC_GPIO2A_DS_L 0x40
82 #define EMMC_IOC_GPIO2D_DS_L 0x58
83 #define EMMC_IOC_GPIO2D_DS_H 0x5c
84
85 #define CRU_BASE 0xfd7c0000
86 #define CRU_GPLL_CON1 0x01c4
87 #define CRU_SOFTRST_CON77 0x0b34
88 #define CRU_GLB_RST_CON 0x0c10
89
90 #define PMU1CRU_BASE 0xfd7f0000
91 #define PMU1CRU_SOFTRST_CON00 0x0a00
92 #define PMU1CRU_SOFTRST_CON03 0x0a0c
93 #define PMU1CRU_SOFTRST_CON04 0x0a10
94
95 #define HDMIRX_NODE_FDT_PATH "/hdmirx-controller@fdee0000"
96 #define RK3588_PHY_CONFIG 0xfdee00c0
97
98 #define DMAC0_PRIORITY_REG 0xfdf32208
99 #define VOP_M0_PRIORITY_REG 0xfdf82008
100 #define VOP_M1_PRIORITY_REG 0xfdf82208
101 #define MMU600PHP_TBU_PRIORITY_REG 0xfdf3a608
102 #define MMU600PHP_TCU_PRIORITY_REG 0xfdf3a808
103 #define QOS_PRIORITY_LEVEL(h, l) ((((h) & 7) << 8) | ((l) & 7))
104
105 #define SATA0_BASE_ADDR 0xfe210000
106 #define SATA1_BASE_ADDR 0xfe220000
107 #define SATA2_BASE_ADDR 0xfe230000
108 #define SATA_PI 0xC
109 #define SATA_PORT_CMD 0x118
110 #define SATA_FBS_ENABLE BIT(22)
111
112 #ifdef CONFIG_ARM64
113 #include <asm/armv8/mmu.h>
114
115 static struct mm_region rk3588_mem_map[] = {
116 {
117 .virt = 0x0UL,
118 .phys = 0x0UL,
119 .size = 0xf0000000UL,
120 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
121 PTE_BLOCK_INNER_SHARE
122 }, {
123 .virt = 0xf0000000UL,
124 .phys = 0xf0000000UL,
125 .size = 0x10000000UL,
126 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
127 PTE_BLOCK_NON_SHARE |
128 PTE_BLOCK_PXN | PTE_BLOCK_UXN
129 }, {
130 .virt = 0x100000000UL,
131 .phys = 0x100000000UL,
132 .size = 0x700000000UL,
133 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
134 PTE_BLOCK_INNER_SHARE
135 }, {
136 .virt = 0x900000000,
137 .phys = 0x900000000,
138 .size = 0x150000000,
139 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
140 PTE_BLOCK_NON_SHARE |
141 PTE_BLOCK_PXN | PTE_BLOCK_UXN
142 }, {
143 /* List terminator */
144 0,
145 }
146 };
147
148 struct mm_region *mem_map = rk3588_mem_map;
149 #endif
150
151 /* GPIO0B_IOMUX_SEL_L */
152 enum {
153 GPIO0B0_SHIFT = 0,
154 GPIO0B0_MASK = GENMASK(3, 0),
155 GPIO0B0_UART0_RX_M1 = 4,
156
157 GPIO0B1_SHIFT = 4,
158 GPIO0B1_MASK = GENMASK(7, 4),
159 GPIO0B1_UART0_TX_M1 = 4,
160 };
161
162 /* GPIO0C_IOMUX_SEL_H */
163 enum {
164 GPIO0C4_SHIFT = 0,
165 GPIO0C4_MASK = GENMASK(3, 0),
166 GPIO0C4_UART0_RX_M0 = 4,
167
168 GPIO0C5_SHIFT = 4,
169 GPIO0C5_MASK = GENMASK(7, 4),
170 GPIO0C5_UART0_TX_M0 = 4,
171 };
172
173 /* GPIO0B_IOMUX_SEL_H */
174 enum {
175 GPIO0B5_SHIFT = 4,
176 GPIO0B5_MASK = GENMASK(7, 4),
177 GPIO0B5_REFER = 8,
178 GPIO0B5_UART2_TX_M0 = 10,
179
180 GPIO0B6_SHIFT = 8,
181 GPIO0B6_MASK = GENMASK(11, 8),
182 GPIO0B6_REFER = 8,
183 GPIO0B6_UART2_RX_M0 = 10,
184 };
185
186 /* GPIO0D_IOMUX_SEL_L */
187 enum {
188 GPIO0D1_SHIFT = 4,
189 GPIO0D1_MASK = GENMASK(7, 4),
190 GPIO0D1_REFER = 8,
191 GPIO0D1_UART1_TX_M2 = 10,
192
193 GPIO0D2_SHIFT = 8,
194 GPIO0D2_MASK = GENMASK(11, 8),
195 GPIO0D2_REFER = 8,
196 GPIO0D2_UART1_RX_M2 = 10,
197 };
198
199 /* GPIO1A_IOMUX_SEL_L */
200 enum {
201 GPIO1A0_SHIFT = 0,
202 GPIO1A0_MASK = GENMASK(3, 0),
203 GPIO1A0_UART6_RX_M1 = 10,
204
205 GPIO1A1_SHIFT = 4,
206 GPIO1A1_MASK = GENMASK(7, 4),
207 GPIO1A1_UART6_TX_M1 = 10,
208 };
209
210 /* GPIO1B_IOMUX_SEL_L */
211 enum {
212 GPIO1B2_SHIFT = 8,
213 GPIO1B2_MASK = GENMASK(11, 8),
214 GPIO1B2_UART4_RX_M2 = 10,
215
216 GPIO1B3_SHIFT = 12,
217 GPIO1B3_MASK = GENMASK(15, 12),
218 GPIO1B3_UART4_TX_M2 = 10,
219 };
220
221 /* GPIO1B_IOMUX_SEL_H */
222 enum {
223 GPIO1B4_SHIFT = 0,
224 GPIO1B4_MASK = GENMASK(3, 0),
225 GPIO1B4_UART7_RX_M2 = 10,
226
227 GPIO1B5_SHIFT = 4,
228 GPIO1B5_MASK = GENMASK(7, 4),
229 GPIO1B5_UART7_TX_M2 = 10,
230
231 GPIO1B6_SHIFT = 8,
232 GPIO1B6_MASK = GENMASK(11, 8),
233 GPIO1B6_UART1_TX_M1 = 10,
234
235 GPIO1B7_SHIFT = 12,
236 GPIO1B7_MASK = GENMASK(15, 12),
237 GPIO1B7_UART1_RX_M1 = 10,
238 };
239
240 /* GPIO1C_IOMUX_SEL_L */
241 enum {
242 GPIO1C0_SHIFT = 0,
243 GPIO1C0_MASK = GENMASK(3, 0),
244 GPIO1C0_UART3_RX_M0 = 10,
245
246 GPIO1C1_SHIFT = 4,
247 GPIO1C1_MASK = GENMASK(7, 4),
248 GPIO1C1_UART3_TX_M0 = 10,
249 };
250
251 /* GPIO1D_IOMUX_SEL_L */
252 enum {
253 GPIO1D0_SHIFT = 0,
254 GPIO1D0_MASK = GENMASK(3, 0),
255 GPIO1D0_UART6_TX_M2 = 10,
256
257 GPIO1D1_SHIFT = 4,
258 GPIO1D1_MASK = GENMASK(7, 4),
259 GPIO1D1_UART6_RX_M2 = 10,
260
261 GPIO1D2_SHIFT = 8,
262 GPIO1D2_MASK = GENMASK(11, 8),
263 GPIO1D2_UART4_TX_M0 = 10,
264
265 GPIO1D3_SHIFT = 12,
266 GPIO1D3_MASK = GENMASK(15, 12),
267 GPIO1D3_UART4_RX_M0 = 10,
268 };
269
270 /* GPIO2A_IOMUX_SEL_H */
271 enum {
272 GPIO2A6_SHIFT = 8,
273 GPIO2A6_MASK = GENMASK(11, 8),
274 GPIO2A6_UART6_RX_M0 = 10,
275
276 GPIO2A7_SHIFT = 12,
277 GPIO2A7_MASK = GENMASK(15, 12),
278 GPIO2A7_UART6_TX_M0 = 10,
279 };
280
281 /* GPIO2B_IOMUX_SEL_H */
282 enum {
283 GPIO2B4_SHIFT = 0,
284 GPIO2B4_MASK = GENMASK(3, 0),
285 GPIO2B4_UART7_RX_M0 = 10,
286
287 GPIO2B5_SHIFT = 4,
288 GPIO2B5_MASK = GENMASK(7, 4),
289 GPIO2B5_UART7_TX_M0 = 10,
290
291 GPIO2B6_SHIFT = 8,
292 GPIO2B6_MASK = GENMASK(11, 8),
293 GPIO2B6_UART1_RX_M0 = 10,
294
295 GPIO2B7_SHIFT = 12,
296 GPIO2B7_MASK = GENMASK(15, 12),
297 GPIO2B7_UART1_TX_M0 = 10,
298 };
299
300 /* GPIO2C_IOMUX_SEL_L */
301 enum {
302 GPIO2C2_SHIFT = 8,
303 GPIO2C2_MASK = GENMASK(11, 8),
304 GPIO2C2_UART9_TX_M0 = 10,
305 };
306
307 /* GPIO2C_IOMUX_SEL_H */
308 enum {
309 GPIO2C4_SHIFT = 0,
310 GPIO2C4_MASK = GENMASK(3, 0),
311 GPIO2C4_UART9_RX_M0 = 10,
312 };
313
314 /* GPIO2D_IOMUX_SEL_H */
315 enum {
316 GPIO2D4_SHIFT = 0,
317 GPIO2D4_MASK = GENMASK(3, 0),
318 GPIO2D4_UART5_RX_M2 = 10,
319
320 GPIO2D5_SHIFT = 4,
321 GPIO2D5_MASK = GENMASK(7, 4),
322 GPIO2D5_UART5_TX_M2 = 10,
323 };
324
325 /* GPIO3A_IOMUX_SEL_H */
326 enum {
327 GPIO3A2_SHIFT = 8,
328 GPIO3A2_MASK = GENMASK(11, 8),
329 GPIO3A2_UART8_TX_M1 = 10,
330
331 GPIO3A3_SHIFT = 12,
332 GPIO3A3_MASK = GENMASK(15, 12),
333 GPIO3A3_UART8_RX_M1 = 10,
334 };
335
336 /* GPIO3B_IOMUX_SEL_L */
337 enum {
338 GPIO3B1_SHIFT = 4,
339 GPIO3B1_MASK = GENMASK(7, 4),
340 GPIO3B1_UART2_TX_M2 = 10,
341
342 GPIO3B2_SHIFT = 8,
343 GPIO3B2_MASK = GENMASK(11, 8),
344 GPIO3B2_UART2_RX_M2 = 10,
345 };
346
347 /* GPIO3B_IOMUX_SEL_H */
348 enum {
349 GPIO3B5_SHIFT = 4,
350 GPIO3B5_MASK = GENMASK(7, 4),
351 GPIO3B5_UART3_TX_M1 = 10,
352
353 GPIO3B6_SHIFT = 8,
354 GPIO3B6_MASK = GENMASK(11, 8),
355 GPIO3B6_UART3_RX_M1 = 10,
356 };
357
358 /* GPIO3C_IOMUX_SEL_L */
359 enum {
360 GPIO3C0_SHIFT = 0,
361 GPIO3C0_MASK = GENMASK(3, 0),
362 GPIO3C0_UART7_TX_M1 = 10,
363
364 GPIO3C1_SHIFT = 4,
365 GPIO3C1_MASK = GENMASK(7, 4),
366 GPIO3C1_UART7_RX_M1 = 10,
367 };
368
369 /* GPIO3C_IOMUX_SEL_H */
370 enum {
371 GPIO3C4_SHIFT = 0,
372 GPIO3C4_MASK = GENMASK(3, 0),
373 GPIO3C4_UART5_TX_M1 = 10,
374
375 GPIO3C5_SHIFT = 4,
376 GPIO3C5_MASK = GENMASK(7, 4),
377 GPIO3C5_UART5_RX_M1 = 10,
378 };
379
380 /* GPIO3D_IOMUX_SEL_L */
381 enum {
382 GPIO3D0_SHIFT = 0,
383 GPIO3D0_MASK = GENMASK(3, 0),
384 GPIO3D0_UART4_RX_M1 = 10,
385
386 GPIO3D1_SHIFT = 4,
387 GPIO3D1_MASK = GENMASK(7, 4),
388 GPIO3D1_UART4_TX_M1 = 10,
389 };
390
391 /* GPIO3D_IOMUX_SEL_H */
392 enum {
393 GPIO3D4_SHIFT = 0,
394 GPIO3D4_MASK = GENMASK(3, 0),
395 GPIO3D4_UART9_RX_M2 = 10,
396
397 GPIO3D5_SHIFT = 4,
398 GPIO3D5_MASK = GENMASK(7, 4),
399 GPIO3D5_UART9_TX_M2 = 10,
400 };
401
402 /* GPIO4A_IOMUX_SEL_L */
403 enum {
404 GPIO4A3_SHIFT = 12,
405 GPIO4A3_MASK = GENMASK(15, 12),
406 GPIO4A3_UART0_TX_M2 = 10,
407 };
408
409 /* GPIO4A_IOMUX_SEL_H */
410 enum {
411 GPIO4A4_SHIFT = 0,
412 GPIO4A4_MASK = GENMASK(3, 0),
413 GPIO4A4_UART0_RX_M2 = 10,
414
415 GPIO4A5_SHIFT = 4,
416 GPIO4A5_MASK = GENMASK(7, 4),
417 GPIO4A5_UART3_TX_M2 = 10,
418
419 GPIO4A6_SHIFT = 8,
420 GPIO4A6_MASK = GENMASK(11, 8),
421 GPIO4A6_UART3_RX_M2 = 10,
422 };
423
424 /* GPIO4B_IOMUX_SEL_L */
425 enum {
426 GPIO4B0_SHIFT = 0,
427 GPIO4B0_MASK = GENMASK(3, 0),
428 GPIO4B0_UART8_TX_M0 = 10,
429
430 GPIO4B1_SHIFT = 4,
431 GPIO4B1_MASK = GENMASK(7, 4),
432 GPIO4B1_UART8_RX_M0 = 10,
433 };
434
435 /* GPIO4B_IOMUX_SEL_H */
436 enum {
437 GPIO4B4_SHIFT = 0,
438 GPIO4B4_MASK = GENMASK(3, 0),
439 GPIO4B4_UART9_TX_M1 = 10,
440
441 GPIO4B5_SHIFT = 4,
442 GPIO4B5_MASK = GENMASK(7, 4),
443 GPIO4B5_UART9_RX_M1 = 10,
444 };
445
446 /* GPIO4D_IOMUX_SEL_L */
447 enum {
448 GPIO4D0_SHIFT = 0,
449 GPIO4D0_MASK = GENMASK(3, 0),
450 GPIO4D0_GPIO = 0,
451 GPIO4D0_SDMMC_D0 = 1,
452 GPIO4D0_PDM1_SDI3_M0 = 2,
453 GPIO4D0_JTAG_TCK_M1 = 5,
454 GPIO4D0_I2C3_SCL_M4 = 9,
455 GPIO4D0_UART2_TX_M1 = 10,
456 GPIO4D0_PWM8_M1 = 12,
457
458 GPIO4D1_SHIFT = 4,
459 GPIO4D1_MASK = GENMASK(7, 4),
460 GPIO4D1_GPIO = 0,
461 GPIO4D1_SDMMC_D1 = 1,
462 GPIO4D1_PDM1_SDI2_M0 = 2,
463 GPIO4D1_JTAG_TMS_M1 = 5,
464 GPIO4D1_I2C3_SDA_M4 = 9,
465 GPIO4D1_UART2_RX_M1 = 10,
466 GPIO4D1_PWM9_M1 = 12,
467 };
468
469 /* GPIO4D_IOMUX_SEL_H */
470 enum {
471 GPIO4D4_SHIFT = 0,
472 GPIO4D4_MASK = GENMASK(3, 0),
473 GPIO4D4_UART5_RX_M0 = 10,
474
475 GPIO4D5_SHIFT = 4,
476 GPIO4D5_MASK = GENMASK(7, 4),
477 GPIO4D5_UART5_TX_M0 = 10,
478 };
479
board_debug_uart_init(void)480 void board_debug_uart_init(void)
481 {
482 __maybe_unused static struct rk3588_bus_ioc * const bus_ioc = (void *)BUS_IOC_BASE;
483
484 /* UART 0 */
485 #if defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xfd890000)
486
487 #if defined(CONFIG_ROCKCHIP_UART_MUX_SEL_M) && \
488 (CONFIG_ROCKCHIP_UART_MUX_SEL_M == 0)
489 static struct rk3588_pmu2_ioc * const pmu2_ioc = (void *)PMU2_IOC_BASE;
490
491 /* UART0_M0 Switch iomux */
492 rk_clrsetreg(&pmu2_ioc->gpio0c_iomux_sel_h,
493 GPIO0C4_MASK | GPIO0C5_MASK,
494 GPIO0C4_UART0_RX_M0 << GPIO0C4_SHIFT |
495 GPIO0C5_UART0_TX_M0 << GPIO0C5_SHIFT);
496
497 #elif defined(CONFIG_ROCKCHIP_UART_MUX_SEL_M) && \
498 (CONFIG_ROCKCHIP_UART_MUX_SEL_M == 1)
499 static struct rk3588_pmu1_ioc * const pmu1_ioc = (void *)PMU1_IOC_BASE;
500
501 /* UART0_M1 Switch iomux */
502 rk_clrsetreg(&pmu1_ioc->gpio0b_iomux_sel_l,
503 GPIO0B0_MASK | GPIO0B1_MASK,
504 GPIO0B0_UART0_RX_M1 << GPIO0B0_SHIFT |
505 GPIO0B1_UART0_TX_M1 << GPIO0B1_SHIFT);
506
507 #elif defined(CONFIG_ROCKCHIP_UART_MUX_SEL_M) && \
508 (CONFIG_ROCKCHIP_UART_MUX_SEL_M == 2)
509
510 /* UART0_M2 Switch iomux */
511 rk_clrsetreg(&bus_ioc->gpio4a_iomux_sel_h,
512 GPIO4A4_MASK,
513 GPIO4A4_UART0_RX_M2 << GPIO4A4_SHIFT);
514 rk_clrsetreg(&bus_ioc->gpio4a_iomux_sel_l,
515 GPIO4A3_MASK,
516 GPIO4A3_UART0_TX_M2 << GPIO4A3_SHIFT);
517
518 #endif
519
520 /* UART 1 */
521 #elif defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xfeb40000)
522 #if defined(CONFIG_ROCKCHIP_UART_MUX_SEL_M) && \
523 (CONFIG_ROCKCHIP_UART_MUX_SEL_M == 0)
524
525 /* UART1_M0 Switch iomux */
526 rk_clrsetreg(&bus_ioc->gpio2b_iomux_sel_h,
527 GPIO2B6_MASK | GPIO2B7_MASK,
528 GPIO2B6_UART1_RX_M0 << GPIO2B6_SHIFT |
529 GPIO2B7_UART1_TX_M0 << GPIO2B7_SHIFT);
530
531 #elif defined(CONFIG_ROCKCHIP_UART_MUX_SEL_M) && \
532 (CONFIG_ROCKCHIP_UART_MUX_SEL_M == 1)
533
534 /* UART1_M1 Switch iomux */
535 rk_clrsetreg(&bus_ioc->gpio1b_iomux_sel_h,
536 GPIO1B7_MASK | GPIO1B6_MASK,
537 GPIO1B7_UART1_RX_M1 << GPIO1B7_SHIFT |
538 GPIO1B6_UART1_TX_M1 << GPIO1B6_SHIFT);
539
540 #elif defined(CONFIG_ROCKCHIP_UART_MUX_SEL_M) && \
541 (CONFIG_ROCKCHIP_UART_MUX_SEL_M == 2)
542
543 static struct rk3588_pmu2_ioc * const pmu2_ioc = (void *)PMU2_IOC_BASE;
544
545 /* Refer to BUS_IOC */
546 rk_clrsetreg(&pmu2_ioc->gpio0d_iomux_sel_l,
547 GPIO0D2_MASK | GPIO0D1_MASK,
548 GPIO0D2_REFER << GPIO0D2_SHIFT |
549 GPIO0D1_REFER << GPIO0D1_SHIFT);
550
551 /* UART1_M2 Switch iomux */
552 rk_clrsetreg(&bus_ioc->gpio0d_iomux_sel_l,
553 GPIO0D2_MASK | GPIO0D1_MASK,
554 GPIO0D2_UART1_RX_M2 << GPIO0D2_SHIFT |
555 GPIO0D1_UART1_TX_M2 << GPIO0D1_SHIFT);
556
557 #endif
558
559 /* UART 2 */
560 #elif defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xfeb50000)
561 #if defined(CONFIG_ROCKCHIP_UART_MUX_SEL_M) && \
562 (CONFIG_ROCKCHIP_UART_MUX_SEL_M == 0)
563
564 static struct rk3588_pmu2_ioc * const pmu2_ioc = (void *)PMU2_IOC_BASE;
565
566 /* Refer to BUS_IOC */
567 rk_clrsetreg(&pmu2_ioc->gpio0b_iomux_sel_h,
568 GPIO0B6_MASK | GPIO0B5_MASK,
569 GPIO0B6_REFER << GPIO0B6_SHIFT |
570 GPIO0B5_REFER << GPIO0B5_SHIFT);
571
572 /* UART2_M0 Switch iomux */
573 rk_clrsetreg(&bus_ioc->gpio0b_iomux_sel_h,
574 GPIO0B6_MASK | GPIO0B5_MASK,
575 GPIO0B6_UART2_RX_M0 << GPIO0B6_SHIFT |
576 GPIO0B5_UART2_TX_M0 << GPIO0B5_SHIFT);
577
578 #elif defined(CONFIG_ROCKCHIP_UART_MUX_SEL_M) && \
579 (CONFIG_ROCKCHIP_UART_MUX_SEL_M == 1)
580
581 /* UART2_M1 Switch iomux */
582 rk_clrsetreg(&bus_ioc->gpio4d_iomux_sel_l,
583 GPIO4D1_MASK | GPIO4D0_MASK,
584 GPIO4D1_UART2_RX_M1 << GPIO4D1_SHIFT |
585 GPIO4D0_UART2_TX_M1 << GPIO4D0_SHIFT);
586
587 #elif defined(CONFIG_ROCKCHIP_UART_MUX_SEL_M) && \
588 (CONFIG_ROCKCHIP_UART_MUX_SEL_M == 2)
589
590 /* UART2_M2 Switch iomux */
591 rk_clrsetreg(&bus_ioc->gpio3b_iomux_sel_l,
592 GPIO3B2_MASK | GPIO3B1_MASK,
593 GPIO3B2_UART2_RX_M2 << GPIO3B2_SHIFT |
594 GPIO3B1_UART2_TX_M2 << GPIO3B1_SHIFT);
595
596 #endif
597
598 /* UART 3 */
599 #elif defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xfeb60000)
600 #if defined(CONFIG_ROCKCHIP_UART_MUX_SEL_M) && \
601 (CONFIG_ROCKCHIP_UART_MUX_SEL_M == 0)
602
603 /* UART3_M0 Switch iomux */
604 rk_clrsetreg(&bus_ioc->gpio1c_iomux_sel_l,
605 GPIO1C0_MASK | GPIO1C1_MASK,
606 GPIO1C0_UART3_RX_M0 << GPIO1C0_SHIFT |
607 GPIO1C1_UART3_TX_M0 << GPIO1C1_SHIFT);
608
609 #elif defined(CONFIG_ROCKCHIP_UART_MUX_SEL_M) && \
610 (CONFIG_ROCKCHIP_UART_MUX_SEL_M == 1)
611
612 /* UART3_M1 Switch iomux */
613 rk_clrsetreg(&bus_ioc->gpio3b_iomux_sel_h,
614 GPIO3B6_MASK | GPIO3B5_MASK,
615 GPIO3B6_UART3_RX_M1 << GPIO3B6_SHIFT |
616 GPIO3B5_UART3_TX_M1 << GPIO3B5_SHIFT);
617
618 #elif defined(CONFIG_ROCKCHIP_UART_MUX_SEL_M) && \
619 (CONFIG_ROCKCHIP_UART_MUX_SEL_M == 2)
620
621 /* UART3_M2 Switch iomux */
622 rk_clrsetreg(&bus_ioc->gpio4a_iomux_sel_h,
623 GPIO4A6_MASK | GPIO4A5_MASK,
624 GPIO4A6_UART3_RX_M2 << GPIO4A6_SHIFT |
625 GPIO4A5_UART3_TX_M2 << GPIO4A5_SHIFT);
626
627 #endif
628
629 /* UART 4 */
630 #elif defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xfeb70000)
631 #if defined(CONFIG_ROCKCHIP_UART_MUX_SEL_M) && \
632 (CONFIG_ROCKCHIP_UART_MUX_SEL_M == 0)
633
634 /* UART4_M0 Switch iomux */
635 rk_clrsetreg(&bus_ioc->gpio1d_iomux_sel_l,
636 GPIO1D3_MASK | GPIO1D2_MASK,
637 GPIO1D3_UART4_RX_M0 << GPIO1D3_SHIFT |
638 GPIO1D2_UART4_TX_M0 << GPIO1D2_SHIFT);
639
640 #elif defined(CONFIG_ROCKCHIP_UART_MUX_SEL_M) && \
641 (CONFIG_ROCKCHIP_UART_MUX_SEL_M == 1)
642
643 /* UART4_M1 Switch iomux */
644 rk_clrsetreg(&bus_ioc->gpio3d_iomux_sel_l,
645 GPIO3D0_MASK | GPIO3D1_MASK,
646 GPIO3D0_UART4_RX_M1 << GPIO3D0_SHIFT |
647 GPIO3D1_UART4_TX_M1 << GPIO3D1_SHIFT);
648
649 #elif defined(CONFIG_ROCKCHIP_UART_MUX_SEL_M) && \
650 (CONFIG_ROCKCHIP_UART_MUX_SEL_M == 2)
651
652 /* UART4_M2 Switch iomux */
653 rk_clrsetreg(&bus_ioc->gpio1b_iomux_sel_l,
654 GPIO1B2_MASK | GPIO1B3_MASK,
655 GPIO1B2_UART4_RX_M2 << GPIO1B2_SHIFT |
656 GPIO1B3_UART4_TX_M2 << GPIO1B3_SHIFT);
657
658 #endif
659
660 /* UART 5 */
661 #elif defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xfeb80000)
662 #if defined(CONFIG_ROCKCHIP_UART_MUX_SEL_M) && \
663 (CONFIG_ROCKCHIP_UART_MUX_SEL_M == 0)
664
665 /* UART5_M0 Switch iomux */
666 rk_clrsetreg(&bus_ioc->gpio4d_iomux_sel_h,
667 GPIO4D4_MASK | GPIO4D5_MASK,
668 GPIO4D4_UART5_RX_M0 << GPIO4D4_SHIFT |
669 GPIO4D5_UART5_TX_M0 << GPIO4D5_SHIFT);
670
671 #elif defined(CONFIG_ROCKCHIP_UART_MUX_SEL_M) && \
672 (CONFIG_ROCKCHIP_UART_MUX_SEL_M == 1)
673
674 /* UART5_M1 Switch iomux */
675 rk_clrsetreg(&bus_ioc->gpio3c_iomux_sel_h,
676 GPIO3C5_MASK | GPIO3C4_MASK,
677 GPIO3C5_UART5_RX_M1 << GPIO3C5_SHIFT |
678 GPIO3C4_UART5_TX_M1 << GPIO3C4_SHIFT);
679
680 #elif defined(CONFIG_ROCKCHIP_UART_MUX_SEL_M) && \
681 (CONFIG_ROCKCHIP_UART_MUX_SEL_M == 2)
682
683 /* UART5_M2 Switch iomux */
684 rk_clrsetreg(&bus_ioc->gpio2d_iomux_sel_h,
685 GPIO2D4_MASK | GPIO2D5_MASK,
686 GPIO2D4_UART5_RX_M2 << GPIO2D4_SHIFT |
687 GPIO2D5_UART5_TX_M2 << GPIO2D5_SHIFT);
688
689 #endif
690
691 /* UART 6 */
692 #elif defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xfeb90000)
693 #if defined(CONFIG_ROCKCHIP_UART_MUX_SEL_M) && \
694 (CONFIG_ROCKCHIP_UART_MUX_SEL_M == 0)
695
696 /* UART6_M0 Switch iomux */
697 rk_clrsetreg(&bus_ioc->gpio2a_iomux_sel_h,
698 GPIO2A6_MASK | GPIO2A7_MASK,
699 GPIO2A6_UART6_RX_M0 << GPIO2A6_SHIFT |
700 GPIO2A7_UART6_TX_M0 << GPIO2A7_SHIFT);
701
702 #elif defined(CONFIG_ROCKCHIP_UART_MUX_SEL_M) && \
703 (CONFIG_ROCKCHIP_UART_MUX_SEL_M == 1)
704
705 /* UART6_M1 Switch iomux */
706 rk_clrsetreg(&bus_ioc->gpio1a_iomux_sel_l,
707 GPIO1A0_MASK | GPIO1A1_MASK,
708 GPIO1A0_UART6_RX_M1 << GPIO1A0_SHIFT |
709 GPIO1A1_UART6_TX_M1 << GPIO1A1_SHIFT);
710
711 #elif defined(CONFIG_ROCKCHIP_UART_MUX_SEL_M) && \
712 (CONFIG_ROCKCHIP_UART_MUX_SEL_M == 2)
713
714 /* UART6_M2 Switch iomux */
715 rk_clrsetreg(&bus_ioc->gpio1d_iomux_sel_l,
716 GPIO1D1_MASK | GPIO1D0_MASK,
717 GPIO1D1_UART6_RX_M2 << GPIO1D1_SHIFT |
718 GPIO1D0_UART6_TX_M2 << GPIO1D0_SHIFT);
719
720 #endif
721
722 /* UART 7 */
723 #elif defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xfeba0000)
724 #if defined(CONFIG_ROCKCHIP_UART_MUX_SEL_M) && \
725 (CONFIG_ROCKCHIP_UART_MUX_SEL_M == 0)
726
727 /* UART7_M0 Switch iomux */
728 rk_clrsetreg(&bus_ioc->gpio2b_iomux_sel_h,
729 GPIO2B4_MASK | GPIO2B5_MASK,
730 GPIO2B4_UART7_RX_M0 << GPIO2B4_SHIFT |
731 GPIO2B5_UART7_TX_M0 << GPIO2B5_SHIFT);
732
733 #elif defined(CONFIG_ROCKCHIP_UART_MUX_SEL_M) && \
734 (CONFIG_ROCKCHIP_UART_MUX_SEL_M == 1)
735
736 /* UART7_M1 Switch iomux */
737 rk_clrsetreg(&bus_ioc->gpio3c_iomux_sel_l,
738 GPIO3C1_MASK | GPIO3C0_MASK,
739 GPIO3C1_UART7_RX_M1 << GPIO3C1_SHIFT |
740 GPIO3C0_UART7_TX_M1 << GPIO3C0_SHIFT);
741
742 #elif defined(CONFIG_ROCKCHIP_UART_MUX_SEL_M) && \
743 (CONFIG_ROCKCHIP_UART_MUX_SEL_M == 2)
744
745 /* UART7_M2 Switch iomux */
746 rk_clrsetreg(&bus_ioc->gpio1b_iomux_sel_h,
747 GPIO1B4_MASK | GPIO1B5_MASK,
748 GPIO1B4_UART7_RX_M2 << GPIO1B4_SHIFT |
749 GPIO1B5_UART7_TX_M2 << GPIO1B5_SHIFT);
750
751 #endif
752
753 /* UART 8 */
754 #elif defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xfebb0000)
755 #if defined(CONFIG_ROCKCHIP_UART_MUX_SEL_M) && \
756 (CONFIG_ROCKCHIP_UART_MUX_SEL_M == 0)
757
758 /* UART8_M0 Switch iomux */
759 rk_clrsetreg(&bus_ioc->gpio4b_iomux_sel_l,
760 GPIO4B1_MASK | GPIO4B0_MASK,
761 GPIO4B1_UART8_RX_M0 << GPIO4B1_SHIFT |
762 GPIO4B0_UART8_TX_M0 << GPIO4B0_SHIFT);
763
764 #elif defined(CONFIG_ROCKCHIP_UART_MUX_SEL_M) && \
765 (CONFIG_ROCKCHIP_UART_MUX_SEL_M == 1)
766
767 /* UART8_M1 Switch iomux */
768 rk_clrsetreg(&bus_ioc->gpio3a_iomux_sel_l,
769 GPIO3A3_MASK | GPIO3A2_MASK,
770 GPIO3A3_UART8_RX_M1 << GPIO3A3_SHIFT |
771 GPIO3A2_UART8_TX_M1 << GPIO3A2_SHIFT);
772
773 #endif
774
775 /* UART 9 */
776 #elif defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xfebc0000)
777 #if defined(CONFIG_ROCKCHIP_UART_MUX_SEL_M) && \
778 (CONFIG_ROCKCHIP_UART_MUX_SEL_M == 0)
779
780 /* UART9_M0 Switch iomux */
781 rk_clrsetreg(&bus_ioc->gpio2c_iomux_sel_h,
782 GPIO2C4_MASK,
783 GPIO2C4_UART9_RX_M0 << GPIO2C4_SHIFT);
784
785 /* UART9_M0 Switch iomux */
786 rk_clrsetreg(&bus_ioc->gpio2c_iomux_sel_l,
787 GPIO2C2_MASK,
788 GPIO2C2_UART9_TX_M0 << GPIO2C2_SHIFT);
789
790 #elif defined(CONFIG_ROCKCHIP_UART_MUX_SEL_M) && \
791 (CONFIG_ROCKCHIP_UART_MUX_SEL_M == 1)
792
793 /* UART9_M1 Switch iomux */
794 rk_clrsetreg(&bus_ioc->gpio4b_iomux_sel_h,
795 GPIO4B5_MASK | GPIO4B4_MASK,
796 GPIO4B5_UART9_RX_M1 << GPIO4B5_SHIFT |
797 GPIO4B4_UART9_TX_M1 << GPIO4B4_SHIFT);
798
799 #elif defined(CONFIG_ROCKCHIP_UART_MUX_SEL_M) && \
800 (CONFIG_ROCKCHIP_UART_MUX_SEL_M == 2)
801
802 /* UART9_M2 Switch iomux */
803 rk_clrsetreg(&bus_ioc->gpio3d_iomux_sel_h,
804 GPIO3D4_MASK | GPIO3D5_MASK,
805 GPIO3D4_UART9_RX_M2 << GPIO3D4_SHIFT |
806 GPIO3D5_UART9_TX_M2 << GPIO3D5_SHIFT);
807
808 #endif
809
810 #endif
811 }
812
813 #ifdef CONFIG_SPL_BUILD
rockchip_stimer_init(void)814 void rockchip_stimer_init(void)
815 {
816 /* If Timer already enabled, don't re-init it */
817 u32 reg = readl(CONFIG_ROCKCHIP_STIMER_BASE + 0x4);
818
819 if (reg & 0x1)
820 return;
821
822 asm volatile("msr CNTFRQ_EL0, %0" : : "r" (COUNTER_FREQUENCY));
823 writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE + 0x14);
824 writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE + 0x18);
825 writel(0x1, CONFIG_ROCKCHIP_STIMER_BASE + 0x4);
826 }
827
828 static u32 gpio4d_iomux_sel_l = 0xffffffff;
829 static u32 gpio4d_iomux_sel_h;
830 static u32 gpio0a_iomux_sel_h;
831
spl_board_sd_iomux_save(void)832 void spl_board_sd_iomux_save(void)
833 {
834 struct rk3588_bus_ioc * const bus_ioc = (void *)BUS_IOC_BASE;
835 struct rk3588_pmu1_ioc * const pmu1_ioc = (void *)PMU1_IOC_BASE;
836
837 gpio4d_iomux_sel_l = readl(&bus_ioc->gpio4d_iomux_sel_l);
838 gpio4d_iomux_sel_h = readl(&bus_ioc->gpio4d_iomux_sel_h);
839 gpio0a_iomux_sel_h = readl(&pmu1_ioc->gpio0a_iomux_sel_h);
840 }
841
spl_board_storages_fixup(struct spl_image_loader * loader)842 void spl_board_storages_fixup(struct spl_image_loader *loader)
843 {
844 int ret = 0;
845
846 if (!loader)
847 return;
848
849 if (loader->boot_device == BOOT_DEVICE_MMC2 && gpio4d_iomux_sel_l != 0xffffffff) {
850 struct rk3588_bus_ioc * const bus_ioc = (void *)BUS_IOC_BASE;
851 struct rk3588_pmu1_ioc * const pmu1_ioc = (void *)PMU1_IOC_BASE;
852 struct mmc *mmc = NULL;
853 bool no_card;
854
855 ret = spl_mmc_find_device(&mmc, BOOT_DEVICE_MMC2);
856 if (ret)
857 return;
858
859 no_card = mmc_getcd(mmc) == 0;
860 if (no_card) {
861 writel(0xffffuL << 16 | gpio4d_iomux_sel_l, &bus_ioc->gpio4d_iomux_sel_l);
862 writel(0xffffuL << 16 | gpio4d_iomux_sel_h, &bus_ioc->gpio4d_iomux_sel_h);
863 writel(0xffffuL << 16 | gpio0a_iomux_sel_h, &pmu1_ioc->gpio0a_iomux_sel_h);
864 }
865 }
866 }
867 #endif
868
board_set_iomux(enum if_type if_type,int devnum,int routing)869 void board_set_iomux(enum if_type if_type, int devnum, int routing)
870 {
871 switch (if_type) {
872 case IF_TYPE_MMC:
873 /*
874 * set the emmc io drive strength:
875 * data and cmd: 50ohm
876 * clock: 25ohm
877 */
878 writel(0x00770052, EMMC_IOC_BASE + EMMC_IOC_GPIO2A_DS_L);
879 writel(0x77772222, EMMC_IOC_BASE + EMMC_IOC_GPIO2D_DS_L);
880 writel(0x77772222, EMMC_IOC_BASE + EMMC_IOC_GPIO2D_DS_H);
881
882 /* set emmc iomux */
883 writel(0xffff1111, BUS_IOC_BASE + BUS_IOC_GPIO2A_IOMUX_SEL_L);
884 writel(0xffff1111, BUS_IOC_BASE + BUS_IOC_GPIO2D_IOMUX_SEL_L);
885 writel(0xffff1111, BUS_IOC_BASE + BUS_IOC_GPIO2D_IOMUX_SEL_H);
886 break;
887
888 case IF_TYPE_MTD:
889 if (routing == 0) {
890 writel(0x000f0002, BUS_IOC_BASE + BUS_IOC_GPIO2A_IOMUX_SEL_L);
891 writel(0xffff2222, BUS_IOC_BASE + BUS_IOC_GPIO2D_IOMUX_SEL_L);
892 writel(0x00f00020, BUS_IOC_BASE + BUS_IOC_GPIO2D_IOMUX_SEL_H);
893 /* Set the fspi m0 io ds level to 55ohm */
894 writel(0x00070002, EMMC_IOC_BASE + EMMC_IOC_GPIO2A_DS_L);
895 writel(0x77772222, EMMC_IOC_BASE + EMMC_IOC_GPIO2D_DS_L);
896 writel(0x07000200, EMMC_IOC_BASE + EMMC_IOC_GPIO2D_DS_H);
897 } else if (routing == 1) {
898 writel(0xff003300, BUS_IOC_BASE + BUS_IOC_GPIO2A_IOMUX_SEL_H);
899 writel(0xf0ff3033, BUS_IOC_BASE + BUS_IOC_GPIO2B_IOMUX_SEL_L);
900 writel(0x000f0003, BUS_IOC_BASE + BUS_IOC_GPIO2B_IOMUX_SEL_H);
901 /* Set the fspi m1 io ds level to 55ohm */
902 writel(0x33002200, VCCIO3_5_IOC_BASE + IOC_VCCIO3_5_GPIO2A_DS_H);
903 writel(0x30332022, VCCIO3_5_IOC_BASE + IOC_VCCIO3_5_GPIO2B_DS_L);
904 writel(0x00030002, VCCIO3_5_IOC_BASE + IOC_VCCIO3_5_GPIO2B_DS_H);
905 } else if (routing == 2) {
906 writel(0xffff5555, BUS_IOC_BASE + BUS_IOC_GPIO3A_IOMUX_SEL_L);
907 writel(0x00f00050, BUS_IOC_BASE + BUS_IOC_GPIO3A_IOMUX_SEL_H);
908 writel(0x00ff0022, BUS_IOC_BASE + BUS_IOC_GPIO3C_IOMUX_SEL_H);
909 /* Set the fspi m2 io ds level to 55ohm */
910 writel(0x77772222, VCCIO3_5_IOC_BASE + IOC_VCCIO3_5_GPIO3A_DS_L);
911 writel(0x00700020, VCCIO3_5_IOC_BASE + IOC_VCCIO3_5_GPIO3A_DS_H);
912 writel(0x00070002, VCCIO3_5_IOC_BASE + IOC_VCCIO3_5_GPIO3C_DS_H);
913 }
914 break;
915 default:
916 break;
917 }
918 }
919
920 #ifndef CONFIG_TPL_BUILD
arch_cpu_init(void)921 int arch_cpu_init(void)
922 {
923 #ifdef CONFIG_SPL_BUILD
924 int secure_reg;
925
926 /* Set the SDMMC eMMC crypto_ns FSPI access secure area */
927 secure_reg = readl(FIREWALL_DDR_BASE + FW_DDR_MST5_REG);
928 secure_reg &= 0xffff;
929 writel(secure_reg, FIREWALL_DDR_BASE + FW_DDR_MST5_REG);
930 secure_reg = readl(FIREWALL_DDR_BASE + FW_DDR_MST13_REG);
931 secure_reg &= 0xffff;
932 writel(secure_reg, FIREWALL_DDR_BASE + FW_DDR_MST13_REG);
933 secure_reg = readl(FIREWALL_DDR_BASE + FW_DDR_MST21_REG);
934 secure_reg &= 0xffff;
935 writel(secure_reg, FIREWALL_DDR_BASE + FW_DDR_MST21_REG);
936 secure_reg = readl(FIREWALL_DDR_BASE + FW_DDR_MST26_REG);
937 secure_reg &= 0xffff;
938 writel(secure_reg, FIREWALL_DDR_BASE + FW_DDR_MST26_REG);
939 secure_reg = readl(FIREWALL_DDR_BASE + FW_DDR_MST27_REG);
940 secure_reg &= 0xffff0000;
941 writel(secure_reg, FIREWALL_DDR_BASE + FW_DDR_MST27_REG);
942
943 secure_reg = readl(FIREWALL_SYSMEM_BASE + FW_SYSM_MST5_REG);
944 secure_reg &= 0xffff;
945 writel(secure_reg, FIREWALL_SYSMEM_BASE + FW_SYSM_MST5_REG);
946 secure_reg = readl(FIREWALL_SYSMEM_BASE + FW_SYSM_MST13_REG);
947 secure_reg &= 0xffff;
948 writel(secure_reg, FIREWALL_SYSMEM_BASE + FW_SYSM_MST13_REG);
949 secure_reg = readl(FIREWALL_SYSMEM_BASE + FW_SYSM_MST21_REG);
950 secure_reg &= 0xffff;
951 writel(secure_reg, FIREWALL_SYSMEM_BASE + FW_SYSM_MST21_REG);
952 secure_reg = readl(FIREWALL_SYSMEM_BASE + FW_SYSM_MST26_REG);
953 secure_reg &= 0xffff;
954 writel(secure_reg, FIREWALL_SYSMEM_BASE + FW_SYSM_MST26_REG);
955 secure_reg = readl(FIREWALL_SYSMEM_BASE + FW_SYSM_MST27_REG);
956 secure_reg &= 0xffff0000;
957 writel(secure_reg, FIREWALL_SYSMEM_BASE + FW_SYSM_MST27_REG);
958
959 /*
960 * Select clk_tx source as default for i2s2/i2s3
961 * Set I2Sx_MCLK as input default
962 *
963 * It's safe to set mclk as input default to avoid high freq glitch
964 * which may make devices work unexpected. And then enabled by
965 * kernel stage or any state where user use it.
966 */
967 writel(0x03c703c7, SYS_GRF_BASE + SYS_GRF_SOC_CON6);
968
969 if (readl(BUS_IOC_BASE + BUS_IOC_GPIO2D_IOMUX_SEL_L) == 0x2222) {
970 /* Set the fspi m0 io ds level to 55ohm */
971 writel(0x00070002, EMMC_IOC_BASE + EMMC_IOC_GPIO2A_DS_L);
972 writel(0x77772222, EMMC_IOC_BASE + EMMC_IOC_GPIO2D_DS_L);
973 writel(0x07000200, EMMC_IOC_BASE + EMMC_IOC_GPIO2D_DS_H);
974 } else if (readl(BUS_IOC_BASE + BUS_IOC_GPIO2D_IOMUX_SEL_L) == 0x1111) {
975 /*
976 * set the emmc io drive strength:
977 * data and cmd: 50ohm
978 * clock: 25ohm
979 */
980 writel(0x00770052, EMMC_IOC_BASE + EMMC_IOC_GPIO2A_DS_L);
981 writel(0x77772222, EMMC_IOC_BASE + EMMC_IOC_GPIO2D_DS_L);
982 writel(0x77772222, EMMC_IOC_BASE + EMMC_IOC_GPIO2D_DS_H);
983 } else if ((readl(BUS_IOC_BASE + BUS_IOC_GPIO2B_IOMUX_SEL_L) & 0xf0ff) == 0x3033) {
984 /* Set the fspi m1 io ds level to 55ohm */
985 writel(0x33002200, VCCIO3_5_IOC_BASE + IOC_VCCIO3_5_GPIO2A_DS_H);
986 writel(0x30332022, VCCIO3_5_IOC_BASE + IOC_VCCIO3_5_GPIO2B_DS_L);
987 writel(0x00030002, VCCIO3_5_IOC_BASE + IOC_VCCIO3_5_GPIO2B_DS_H);
988 } else if (readl(BUS_IOC_BASE + BUS_IOC_GPIO3A_IOMUX_SEL_L) == 0x5555) {
989 /* Set the fspi m2 io ds level to 55ohm */
990 writel(0x77772222, VCCIO3_5_IOC_BASE + IOC_VCCIO3_5_GPIO3A_DS_L);
991 writel(0x00700020, VCCIO3_5_IOC_BASE + IOC_VCCIO3_5_GPIO3A_DS_H);
992 writel(0x00070002, VCCIO3_5_IOC_BASE + IOC_VCCIO3_5_GPIO3C_DS_H);
993 }
994
995 /*
996 * Assert reset the pipephy0, pipephy1 and pipephy2,
997 * and de-assert reset them in Kernel combphy driver.
998 */
999 writel(0x01c001c0, CRU_BASE + CRU_SOFTRST_CON77);
1000
1001 /*
1002 * Assert SIDDQ for USB 2.0 PHY1, PHY2 and PHY3 to
1003 * power down all analog block to save power. And
1004 * PHY0 for OTG0 interface still in normal mode.
1005 */
1006 writel(0x20002000, USB2PHY1_GRF_BASE + USB2PHY_GRF_CON2);
1007 writel(0x20002000, USB2PHY2_GRF_BASE + USB2PHY_GRF_CON2);
1008 writel(0x20002000, USB2PHY3_GRF_BASE + USB2PHY_GRF_CON2);
1009
1010 /* Assert hdptxphy init,cmn,lane reset */
1011 writel(0xb800b800, PMU1CRU_BASE + PMU1CRU_SOFTRST_CON03);
1012 writel(0x00030003, PMU1CRU_BASE + PMU1CRU_SOFTRST_CON04);
1013
1014 spl_board_sd_iomux_save();
1015 #elif defined(CONFIG_SUPPORT_USBPLUG)
1016 int secure_reg;
1017
1018 /* Set the SDMMC eMMC crypto_ns FSPI access secure area */
1019 secure_reg = readl(FIREWALL_DDR_BASE + FW_DDR_MST5_REG);
1020 secure_reg &= 0xffff;
1021 writel(secure_reg, FIREWALL_DDR_BASE + FW_DDR_MST5_REG);
1022 secure_reg = readl(FIREWALL_DDR_BASE + FW_DDR_MST13_REG);
1023 secure_reg &= 0xffff;
1024 writel(secure_reg, FIREWALL_DDR_BASE + FW_DDR_MST13_REG);
1025 secure_reg = readl(FIREWALL_DDR_BASE + FW_DDR_MST21_REG);
1026 secure_reg &= 0xffff;
1027 writel(secure_reg, FIREWALL_DDR_BASE + FW_DDR_MST21_REG);
1028 secure_reg = readl(FIREWALL_DDR_BASE + FW_DDR_MST26_REG);
1029 secure_reg &= 0xffff;
1030 writel(secure_reg, FIREWALL_DDR_BASE + FW_DDR_MST26_REG);
1031 secure_reg = readl(FIREWALL_DDR_BASE + FW_DDR_MST27_REG);
1032 secure_reg &= 0xffff0000;
1033 writel(secure_reg, FIREWALL_DDR_BASE + FW_DDR_MST27_REG);
1034
1035 secure_reg = readl(FIREWALL_SYSMEM_BASE + FW_SYSM_MST5_REG);
1036 secure_reg &= 0xffff;
1037 writel(secure_reg, FIREWALL_SYSMEM_BASE + FW_SYSM_MST5_REG);
1038 secure_reg = readl(FIREWALL_SYSMEM_BASE + FW_SYSM_MST13_REG);
1039 secure_reg &= 0xffff;
1040 writel(secure_reg, FIREWALL_SYSMEM_BASE + FW_SYSM_MST13_REG);
1041 secure_reg = readl(FIREWALL_SYSMEM_BASE + FW_SYSM_MST21_REG);
1042 secure_reg &= 0xffff;
1043 writel(secure_reg, FIREWALL_SYSMEM_BASE + FW_SYSM_MST21_REG);
1044 secure_reg = readl(FIREWALL_SYSMEM_BASE + FW_SYSM_MST26_REG);
1045 secure_reg &= 0xffff;
1046 writel(secure_reg, FIREWALL_SYSMEM_BASE + FW_SYSM_MST26_REG);
1047 secure_reg = readl(FIREWALL_SYSMEM_BASE + FW_SYSM_MST27_REG);
1048 secure_reg &= 0xffff0000;
1049 writel(secure_reg, FIREWALL_SYSMEM_BASE + FW_SYSM_MST27_REG);
1050 #else /* U-Boot */
1051 /* uboot: config iomux */
1052 #ifdef CONFIG_ROCKCHIP_EMMC_IOMUX
1053 /* Set emmc iomux for good extention if the emmc is not the boot device */
1054 writel(0xffff1111, BUS_IOC_BASE + BUS_IOC_GPIO2A_IOMUX_SEL_L);
1055 writel(0xffff1111, BUS_IOC_BASE + BUS_IOC_GPIO2D_IOMUX_SEL_L);
1056 writel(0xffff1111, BUS_IOC_BASE + BUS_IOC_GPIO2D_IOMUX_SEL_H);
1057 #endif
1058 /*
1059 * set DMAC0 to priority 0x404 to keep the same with DMAC1/2
1060 * which had been set 0x404 by default.
1061 */
1062 writel(QOS_PRIORITY_LEVEL(4, 4), DMAC0_PRIORITY_REG);
1063
1064 /*
1065 * set VOP M0 and VOP M1 to priority 0x303,then
1066 * Peri > VOP/MCU > ISP/VICAP > other
1067 * Note: VOP priority can only be modified during the u-boot stage,
1068 * as VOP default power down, and power up after trust.
1069 */
1070 writel(QOS_PRIORITY_LEVEL(3, 3), VOP_M0_PRIORITY_REG);
1071 writel(QOS_PRIORITY_LEVEL(3, 3), VOP_M1_PRIORITY_REG);
1072 /*
1073 * set SATA,USB,GMAC to priority 0x404
1074 */
1075 writel(QOS_PRIORITY_LEVEL(4, 4), MMU600PHP_TBU_PRIORITY_REG);
1076 writel(QOS_PRIORITY_LEVEL(4, 4), MMU600PHP_TCU_PRIORITY_REG);
1077
1078 /*
1079 * Set SATA FBSCP and PORTS_IMPL for kernel drivers
1080 */
1081 writel(SATA_FBS_ENABLE, SATA0_BASE_ADDR + SATA_PORT_CMD);
1082 writel(1, SATA0_BASE_ADDR + SATA_PI);
1083 writel(SATA_FBS_ENABLE, SATA1_BASE_ADDR + SATA_PORT_CMD);
1084 writel(1, SATA1_BASE_ADDR + SATA_PI);
1085 writel(SATA_FBS_ENABLE, SATA2_BASE_ADDR + SATA_PORT_CMD);
1086 writel(1, SATA2_BASE_ADDR + SATA_PI);
1087 #endif
1088
1089 /* Select usb otg0 phy status to 0 that make rockusb can work at high-speed */
1090 writel(0x00080008, USBGRF_BASE + USB_GRF_USB3OTG0_CON1);
1091
1092 return 0;
1093 }
1094 #endif
1095
1096 #define BAD_CPU(mask, n) ((mask) & (1 << (n)))
1097 #define BAD_RKVENC(mask, n) ((mask) & (1 << (n)))
1098 #define BAD_RKVDEC(mask, n) ((mask) & (1 << (n)))
1099
fdt_rm_path(void * blob,const char * path)1100 static void fdt_rm_path(void *blob, const char *path)
1101 {
1102 fdt_del_node(blob, fdt_path_offset(blob, path));
1103 }
1104
fdt_rename_path(void * blob,const char * path,const char * name)1105 static void fdt_rename_path(void *blob, const char *path, const char *name)
1106 {
1107 int noffset;
1108
1109 noffset = fdt_path_offset(blob, path);
1110 if (noffset < 0)
1111 return;
1112
1113 fdt_set_name(blob, noffset, name);
1114 }
1115
fdt_rm_cooling_map(const void * blob,u8 cpu_mask)1116 static void fdt_rm_cooling_map(const void *blob, u8 cpu_mask)
1117 {
1118 int map1, map2;
1119 int cpub1_phd;
1120 int cpub3_phd;
1121 int node;
1122 u32 *pp;
1123
1124 node = fdt_path_offset(blob, "/cpus/cpu@500");
1125 cpub1_phd = fdtdec_get_uint(blob, node, "phandle", -1);
1126 node = fdt_path_offset(blob, "/cpus/cpu@700");
1127 cpub3_phd = fdtdec_get_uint(blob, node, "phandle", -1);
1128
1129 if (BAD_CPU(cpu_mask, 4)) {
1130 map1 = fdt_path_offset(blob, "/thermal-zones/soc-thermal/cooling-maps/map1");
1131 if (map1 > 0) {
1132 if (BAD_CPU(cpu_mask, 5)) {
1133 debug("rm: cooling-device map1\n");
1134 fdt_del_node((void *)blob, map1);
1135 } else {
1136 pp = (u32 *)fdt_getprop(blob, map1, "cooling-device", NULL);
1137 if (pp) {
1138 pp[0] = cpu_to_fdt32(cpub1_phd);
1139 debug("fix: cooling-device cpub0->cpub1\n");
1140 }
1141 }
1142 }
1143 }
1144
1145 if (BAD_CPU(cpu_mask, 6)) {
1146 map2 = fdt_path_offset(blob, "/thermal-zones/soc-thermal/cooling-maps/map2");
1147 if (map2 > 0) {
1148 if (BAD_CPU(cpu_mask, 7)) {
1149 debug("rm: cooling-device map2\n");
1150 fdt_del_node((void *)blob, map2);
1151 } else {
1152 pp = (u32 *)fdt_getprop(blob, map2, "cooling-device", NULL);
1153 if (pp) {
1154 pp[0] = cpu_to_fdt32(cpub3_phd);
1155 debug("fix: cooling-device cpub2->cpub3\n");
1156 }
1157 }
1158 }
1159 }
1160 }
1161
fdt_rm_cpu_affinity(const void * blob,u8 cpu_mask)1162 static void fdt_rm_cpu_affinity(const void *blob, u8 cpu_mask)
1163 {
1164 int i, remain, arm_pmu;
1165 u32 new_aff[8];
1166 u32 *aff;
1167
1168 arm_pmu = fdt_path_offset(blob, "/arm-pmu");
1169 if (arm_pmu > 0) {
1170 aff = (u32 *)fdt_getprop(blob, arm_pmu, "interrupt-affinity", NULL);
1171 if (!aff)
1172 return;
1173
1174 for (i = 0, remain = 0; i < 8; i++) {
1175 if (!BAD_CPU(cpu_mask, i)) {
1176 new_aff[remain++] = aff[i];
1177 debug("new_aff: 0x%08x\n", (u32)aff[i]);
1178 }
1179 }
1180
1181 fdt_setprop((void *)blob, arm_pmu, "interrupt-affinity", new_aff, remain * 4);
1182 }
1183 }
1184
fdt_rm_cpu(const void * blob,u8 cpu_mask)1185 static void fdt_rm_cpu(const void *blob, u8 cpu_mask)
1186 {
1187 const char *cpu_node_name[] = {
1188 "cpu@0", "cpu@100", "cpu@200", "cpu@300",
1189 "cpu@400", "cpu@500", "cpu@600", "cpu@700",
1190 };
1191 const char *cluster_core_name[] = {
1192 "core0", "core1", "core2", "core3",
1193 "core0", "core1", "core0", "core1",
1194 };
1195 const char *cluster_core, *cpu_node;
1196 int root_cpus, cpu;
1197 int cluster;
1198 int i;
1199
1200 root_cpus = fdt_path_offset(blob, "/cpus");
1201 if (root_cpus < 0)
1202 return;
1203
1204 for (i = 0; i < 8; i++) {
1205 if (!BAD_CPU(cpu_mask, i))
1206 continue;
1207
1208 if (i < 4)
1209 cluster = fdt_path_offset(blob, "/cpus/cpu-map/cluster0");
1210 else if (i < 6)
1211 cluster = fdt_path_offset(blob, "/cpus/cpu-map/cluster1");
1212 else
1213 cluster = fdt_path_offset(blob, "/cpus/cpu-map/cluster2");
1214
1215 if (cluster < 0)
1216 return;
1217
1218 cpu_node = cpu_node_name[i];
1219 cluster_core = cluster_core_name[i];
1220 debug("rm: %s, %s\n", cpu_node, cluster_core);
1221
1222 cpu = fdt_subnode_offset(blob, cluster, cluster_core);
1223 if (cpu > 0)
1224 fdt_del_node((void *)blob, cpu);
1225
1226 cpu = fdt_subnode_offset(blob, root_cpus, cpu_node);
1227 if (cpu > 0)
1228 fdt_del_node((void *)blob, cpu);
1229 }
1230
1231 cluster = fdt_path_offset(blob, "/cpus/cpu-map/cluster1");
1232 if (BAD_CPU(cpu_mask, 4) && BAD_CPU(cpu_mask, 5)) {
1233 debug("rm: cpu cluster1\n");
1234 fdt_del_node((void *)blob, cluster);
1235 }
1236
1237 cluster = fdt_path_offset(blob, "/cpus/cpu-map/cluster2");
1238 if (BAD_CPU(cpu_mask, 6) && BAD_CPU(cpu_mask, 7)) {
1239 debug("rm: cpu cluster2\n");
1240 fdt_del_node((void *)blob, cluster);
1241 } else {
1242 /* rename, otherwise linux only handles cluster0 */
1243 if (fdt_path_offset(blob, "/cpus/cpu-map/cluster1") < 0)
1244 fdt_set_name((void *)blob, cluster, "cluster1");
1245 }
1246 }
1247
rk3582_3_fdt_rm_cpus(const void * blob,u8 cpu_mask)1248 static void rk3582_3_fdt_rm_cpus(const void *blob, u8 cpu_mask)
1249 {
1250 /*
1251 * policy:
1252 *
1253 * 1. both of cores within the same cluster should be normal, otherwise
1254 * remove both of them.
1255 * 2. if core4~7 are all normal, remove core6 and core7 anyway.
1256 */
1257 if (BAD_CPU(cpu_mask, 4) || BAD_CPU(cpu_mask, 5))
1258 cpu_mask |= BIT(4) | BIT(5);
1259 if (BAD_CPU(cpu_mask, 6) || BAD_CPU(cpu_mask, 7))
1260 cpu_mask |= BIT(6) | BIT(7);
1261
1262 if (!BAD_CPU(cpu_mask, 4) & !BAD_CPU(cpu_mask, 5) &&
1263 !BAD_CPU(cpu_mask, 6) & !BAD_CPU(cpu_mask, 7))
1264 cpu_mask |= BIT(6) | BIT(7);
1265
1266 fdt_rm_cooling_map(blob, cpu_mask);
1267 fdt_rm_cpu_affinity(blob, cpu_mask);
1268 fdt_rm_cpu(blob, cpu_mask);
1269 }
1270
rk3582_3_fdt_rm_rkvenc01(void * blob,u8 mask)1271 static void rk3582_3_fdt_rm_rkvenc01(void *blob, u8 mask)
1272 {
1273 /*
1274 * policy:
1275 *
1276 * 1. remove bad.
1277 * 2. if both of rkvenc0 and rkvenc1 are normal, remove rkvenc1 by default.
1278 * 3. disable '*-ccu' node
1279 * 4. rename '*-core@' node
1280 */
1281 if (!BAD_RKVENC(mask, 0) && !BAD_RKVENC(mask, 1)) {
1282 /* rkvenc1 */
1283 fdt_rm_path(blob, "/rkvenc-core@fdbe0000");
1284 fdt_rm_path(blob, "/iommu@fdbef000");
1285 debug("rm: rkvenv1\n");
1286 } else {
1287 if (BAD_RKVENC(mask, 0)) {
1288 fdt_rm_path(blob, "/rkvenc-core@fdbd0000");
1289 fdt_rm_path(blob, "/iommu@fdbdf000");
1290 debug("rm: rkvenv0\n");
1291
1292 }
1293 if (BAD_RKVENC(mask, 1)) {
1294 fdt_rm_path(blob, "/rkvenc-core@fdbe0000");
1295 fdt_rm_path(blob, "/iommu@fdbef000");
1296 debug("rm: rkvenv1\n");
1297 }
1298 }
1299
1300 do_fixup_by_path((void *)blob, "/rkvenc-ccu",
1301 "status", "disabled", sizeof("disabled"), 0);
1302
1303 /* rename node name if the node exist, actually only one exist */
1304 fdt_rename_path(blob, "/rkvenc-core@fdbd0000", "rkvenc@fdbd0000");
1305 fdt_rename_path(blob, "/rkvenc-core@fdbe0000", "rkvenc@fdbe0000");
1306 }
1307
rk3582_3_fdt_rm_rkvdec01(void * blob,u8 mask)1308 static void rk3582_3_fdt_rm_rkvdec01(void *blob, u8 mask)
1309 {
1310 /*
1311 * policy:
1312 *
1313 * 1. remove bad.
1314 * 2. if both of rkvdec0 and rkvdec1 are normal, remove rkvdec1 by default.
1315 * 3. disable '*-ccu' node
1316 * 4. rename '*-core@' node
1317 */
1318 if (!BAD_RKVDEC(mask, 0) && !BAD_RKVDEC(mask, 1)) {
1319 /* rkvdec1 */
1320 fdt_rm_path(blob, "/rkvdec-core@fdc48000");
1321 fdt_rm_path(blob, "/iommu@fdc48700");
1322 debug("rm: rkvdec1\n");
1323 } else {
1324 if (BAD_RKVDEC(mask, 0)) {
1325 fdt_rm_path(blob, "/rkvdec-core@fdc38000");
1326 fdt_rm_path(blob, "/iommu@fdc38700");
1327 debug("rm: rkvdec0\n");
1328
1329 }
1330 if (BAD_RKVDEC(mask, 1)) {
1331 fdt_rm_path(blob, "/rkvdec-core@fdc48000");
1332 fdt_rm_path(blob, "/iommu@fdc48700");
1333 debug("rm: rkvdec1\n");
1334 }
1335 }
1336
1337 do_fixup_by_path((void *)blob, "/rkvdec-ccu@fdc30000",
1338 "status", "disabled", sizeof("disabled"), 0);
1339
1340 /* rename node name if the node exist, actually only one exist */
1341 fdt_rename_path(blob, "/rkvdec-core@fdc38000", "rkvdec@fdc38000");
1342 fdt_rename_path(blob, "/rkvdec-core@fdc48000", "rkvdec@fdc48000");
1343 }
1344
1345 #define CHIP_ID_OFF 2
1346 #define IP_STATE_OFF 29
1347
fdt_fixup_modules(void * blob)1348 static int fdt_fixup_modules(void *blob)
1349 {
1350 struct udevice *dev;
1351 u8 ip_state[3];
1352 u8 chip_id[2];
1353 u8 rkvenc_mask;
1354 u8 rkvdec_mask;
1355 u8 cpu_mask;
1356 int ret;
1357
1358 ret = uclass_get_device_by_driver(UCLASS_MISC,
1359 DM_GET_DRIVER(rockchip_otp), &dev);
1360 if (ret) {
1361 printf("can't get otp device, ret=%d\n", ret);
1362 return ret;
1363 }
1364
1365 ret = misc_read(dev, CHIP_ID_OFF, &chip_id, sizeof(chip_id));
1366 if (ret) {
1367 printf("can't read chip id, ret=%d\n", ret);
1368 return ret;
1369 }
1370
1371 debug("# chip: rk%02x%02x\n", chip_id[0], chip_id[1]);
1372
1373 /* only rk3582/rk3583 goes further */
1374 if (!(chip_id[0] == 0x35 && chip_id[1] == 0x82) &&
1375 !(chip_id[0] == 0x35 && chip_id[1] == 0x83))
1376 return 0;
1377
1378 ret = misc_read(dev, IP_STATE_OFF, &ip_state, sizeof(ip_state));
1379 if (ret) {
1380 printf("can't read ip state, ret=%d\n", ret);
1381 return ret;
1382 }
1383
1384 /* ip_state[0]: bit0~7 */
1385 cpu_mask = ip_state[0];
1386 /* ip_state[2]: bit0,2 */
1387 rkvenc_mask = (ip_state[2] & 0x1) | ((ip_state[2] & 0x4) >> 1);
1388 /* ip_state[1]: bit6,7 */
1389 rkvdec_mask = (ip_state[1] & 0xc0) >> 6;
1390 #if 0
1391 /* ip_state[1]: bit1~4 */
1392 gpu_mask = (ip_state[1] & 0x1e) >> 1;
1393 #endif
1394 debug("hw-mask: 0x%02x, 0x%02x, 0x%02x\n", ip_state[0], ip_state[1], ip_state[2]);
1395 debug("sw-mask: 0x%02x, 0x%02x, 0x%02x\n", cpu_mask, rkvenc_mask, rkvdec_mask);
1396
1397 /*
1398 * FIXUP WARNING!
1399 *
1400 * The node delete changes the fdt structure, a node offset you already
1401 * got before maybe not right by now. Make sure always reading the node
1402 * offset exactly before you are going to use.
1403 */
1404 if (chip_id[0] == 0x35 && (chip_id[1] == 0x82 || chip_id[1] == 0x83)) {
1405 rk3582_3_fdt_rm_rkvdec01(blob, rkvdec_mask);
1406 rk3582_3_fdt_rm_rkvenc01(blob, rkvenc_mask);
1407 rk3582_3_fdt_rm_cpus(blob, cpu_mask);
1408 }
1409
1410 return 0;
1411 }
1412
rk_board_dm_fdt_fixup(const void * blob)1413 int rk_board_dm_fdt_fixup(const void *blob)
1414 {
1415 return fdt_fixup_modules((void *)blob);
1416 }
1417
rk_board_fdt_fixup(const void * blob)1418 int rk_board_fdt_fixup(const void *blob)
1419 {
1420 int node;
1421
1422 /* set hdmirx to low power mode */
1423 node = fdt_path_offset(blob, HDMIRX_NODE_FDT_PATH);
1424 if (node >= 0) {
1425 if (fdtdec_get_int(blob, node, "low-power-mode", 0)) {
1426 printf("hdmirx low power mode\n");
1427 writel(0x00000100, RK3588_PHY_CONFIG);
1428 }
1429 }
1430
1431 return 0;
1432 }
1433
fit_standalone_release(char * id,uintptr_t entry_point)1434 int fit_standalone_release(char *id, uintptr_t entry_point)
1435 {
1436 /* pmu m0 configuration: */
1437 /* set gpll */
1438 writel(0x00f00042, CRU_BASE + CRU_GPLL_CON1);
1439
1440 sip_smc_mcu_config(ROCKCHIP_SIP_CONFIG_PMUMCU_0_ID,
1441 ROCKCHIP_SIP_CONFIG_MCU_CODE_START_ADDR,
1442 0xffff0000 | (entry_point >> 16));
1443
1444 /* select WDT trigger global reset. */
1445 writel(0x08400840, CRU_BASE + CRU_GLB_RST_CON);
1446 /* release pmu mcu */
1447 writel(0x20000000, PMU1CRU_BASE + PMU1CRU_SOFTRST_CON00);
1448
1449 return 0;
1450 }
1451
1452