1 /*
2 * Copyright (c) 2020 Rockchip Electronics Co., Ltd
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6 #include <common.h>
7 #include <clk.h>
8 #include <dm.h>
9 #include <misc.h>
10 #include <asm/io.h>
11 #include <asm/arch/cpu.h>
12 #include <asm/arch/hardware.h>
13 #include <asm/arch/grf_rk3568.h>
14 #include <asm/arch/rk_atags.h>
15 #include <linux/libfdt.h>
16 #include <fdt_support.h>
17 #include <asm/arch/clock.h>
18 #include <dt-bindings/clock/rk3568-cru.h>
19
20 DECLARE_GLOBAL_DATA_PTR;
21
22 #define PMUGRF_BASE 0xfdc20000
23 #define GRF_BASE 0xfdc60000
24 #define GRF_GPIO1B_IOMUX_H 0x0C
25 #define GRF_GPIO1C_IOMUX_L 0x10
26 #define GRF_GPIO1C_IOMUX_H 0x14
27 #define GRF_GPIO1D_IOMUX_L 0x18
28 #define GRF_GPIO1D_IOMUX_H 0x1C
29 #define GRF_GPIO1B_DS_2 0x218
30 #define GRF_GPIO1B_DS_3 0x21c
31 #define GRF_GPIO1C_DS_0 0x220
32 #define GRF_GPIO1C_DS_1 0x224
33 #define GRF_GPIO1C_DS_2 0x228
34 #define GRF_GPIO1C_DS_3 0x22c
35 #define GRF_GPIO1D_DS_0 0x230
36 #define GRF_GPIO1D_DS_1 0x234
37 #define GRF_GPIO1D_DS_2 0x238
38 #define GRF_SOC_CON4 0x510
39 #define PMU_BASE_ADDR 0xfdd90000
40 #define PMU_NOC_AUTO_CON0 (0x70)
41 #define PMU_NOC_AUTO_CON1 (0x74)
42 #define CRU_BASE 0xfdd20000
43 #define CRU_SOFTRST_CON26 0x468
44 #define CRU_SOFTRST_CON28 0x470
45 #define SGRF_BASE 0xFDD18000
46 #define SGRF_SOC_CON3 0xC
47 #define SGRF_SOC_CON4 0x10
48 #define PMUGRF_SOC_CON15 0xfdc20100
49 #define CPU_GRF_BASE 0xfdc30000
50 #define GRF_CORE_PVTPLL_CON0 (0x10)
51 #define USBPHY_U3_GRF 0xfdca0000
52 #define USBPHY_U3_GRF_CON1 (USBPHY_U3_GRF + 0x04)
53 #define USBPHY_U2_GRF 0xfdca8000
54 #define USBPHY_U2_GRF_CON0 (USBPHY_U2_GRF + 0x00)
55 #define USBPHY_U2_GRF_CON1 (USBPHY_U2_GRF + 0x04)
56
57 #define PMU_PWR_GATE_SFTCON (0xA0)
58 #define PMU_PWR_DWN_ST (0x98)
59 #define PMU_BUS_IDLE_SFTCON0 (0x50)
60 #define PMU_BUS_IDLE_ST (0x68)
61 #define PMU_BUS_IDLE_ACK (0x60)
62
63 #define EBC_PRIORITY_REG (0xfe158008)
64
65 #define SATA0_BASE_ADDR 0xfc000000
66 #define SATA1_BASE_ADDR 0xfc400000
67 #define SATA2_BASE_ADDR 0xfc800000
68 #define SATA_PI 0xC
69 #define SATA_PORT_CMD 0x118
70 #define SATA_FBS_ENABLE BIT(22)
71
72 #define OTP_SPEC_NUM_OFFSET 0x07
73 #define OTP_SPEC_NUM_MASK 0x1f
74 #define REMARK_OTP_SPEC_NUM_OFFSET 0x56
75
76 enum {
77 /* PMU_GRF_GPIO0C_IOMUX_L */
78 GPIO0C1_SHIFT = 4,
79 GPIO0C1_MASK = GENMASK(6, 4),
80 GPIO0C1_GPIO = 0,
81 GPIO0C1_PWM2_M0,
82 GPIO0C1_NPU_AVS,
83 GPIO0C1_UART0_TX,
84 GPIO0C1_MCU_JTAGTDI,
85
86 GPIO0C0_SHIFT = 0,
87 GPIO0C0_MASK = GENMASK(2, 0),
88 GPIO0C0_GPIO = 0,
89 GPIO0C0_PWM1_M0,
90 GPIO0C0_GPU_AVS,
91 GPIO0C0_UART0_RX,
92
93 /* PMU_GRF_GPIO0D_IOMUX_L */
94 GPIO0D1_SHIFT = 4,
95 GPIO0D1_MASK = GENMASK(6, 4),
96 GPIO0D1_GPIO = 0,
97 GPIO0D1_UART2_TXM0,
98
99 GPIO0D0_SHIFT = 0,
100 GPIO0D0_MASK = GENMASK(2, 0),
101 GPIO0D0_GPIO = 0,
102 GPIO0D0_UART2_RXM0,
103
104 /* PMU_GRF_SOC_CON0 */
105 UART0_IO_SEL_SHIFT = 8,
106 UART0_IO_SEL_MASK = GENMASK(9, 8),
107 UART0_IO_SEL_M0 = 0,
108 UART0_IO_SEL_M1,
109 UART0_IO_SEL_M2,
110 };
111
112 enum {
113 /* GRF_GPIO1A_IOMUX_L */
114 GPIO1A1_SHIFT = 4,
115 GPIO1A1_MASK = GENMASK(6, 4),
116 GPIO1A1_GPIO = 0,
117 GPIO1A1_I2C3_SCLM0,
118 GPIO1A1_UART3_TXM0,
119 GPIO1A1_CAN1_TXM0,
120 GPIO1A1_AUDIOPWM_ROUT,
121 GPIO1A1_ACODEC_ADCCLK,
122 GPIO1A1_AUDIOPWM_LOUT,
123
124 GPIO1A0_SHIFT = 0,
125 GPIO1A0_MASK = GENMASK(2, 0),
126 GPIO1A0_GPIO = 0,
127 GPIO1A0_I2C3_SDAM0,
128 GPIO1A0_UART3_RXM0,
129 GPIO1A0_CAN1_RXM0,
130 GPIO1A0_AUDIOPWM_LOUT,
131 GPIO1A0_ACODEC_ADCDATA,
132 GPIO1A0_AUDIOPWM_LOUTP,
133
134 /* GRF_GPIO1A_IOMUX_H */
135 GPIO1A6_SHIFT = 8,
136 GPIO1A6_MASK = GENMASK(10, 8),
137 GPIO1A6_GPIO = 0,
138 GPIO1A6_I2S1_LRCKRXM0,
139 GPIO1A6_UART4_TXM0,
140 GPIO1A6_PDM_CLK0M0,
141 GPIO1A6_AUDIOPWM_ROUTP,
142
143 GPIO1A4_SHIFT = 0,
144 GPIO1A4_MASK = GENMASK(2, 0),
145 GPIO1A4_GPIO = 0,
146 GPIO1A4_I2S1_SCLKRXM0,
147 GPIO1A4_UART4_RXM0,
148 GPIO1A4_PDM_CLK1M0,
149 GPIO1A4_SPDIF_TXM0,
150
151 /* GRF_GPIO1D_IOMUX_H */
152 GPIO1D6_SHIFT = 8,
153 GPIO1D6_MASK = GENMASK(10, 8),
154 GPIO1D6_GPIO = 0,
155 GPIO1D6_SDMMC0_D1,
156 GPIO1D6_UART2_RXM1,
157 GPIO1D6_UART6_RXM1,
158 GPIO1D6_PWM9_M1,
159
160 GPIO1D5_SHIFT = 4,
161 GPIO1D5_MASK = GENMASK(6, 4),
162 GPIO1D5_GPIO = 0,
163 GPIO1D5_SDMMC0_D0,
164 GPIO1D5_UART2_TXM1,
165 GPIO1D5_UART6_TXM1,
166 GPIO1D5_PWM8_M1,
167
168 /* GRF_GPIO2A_IOMUX_L */
169 GPIO2A3_SHIFT = 12,
170 GPIO2A3_MASK = GENMASK(14, 12),
171 GPIO2A3_GPIO = 0,
172 GPIO2A3_SDMMC1_D0,
173 GPIO2A3_GMAC0_RXD2,
174 GPIO2A3_UART6_RXM0,
175
176 GPIO2A2_SHIFT = 8,
177 GPIO2A2_MASK = GENMASK(10, 8),
178 GPIO2A2_GPIO = 0,
179 GPIO2A2_SDMMC0_CLK,
180 GPIO2A2_TEST_CLKOUT,
181 GPIO2A2_UART5_TXM0,
182 GPIO2A2_CAN0_RXM1,
183
184 GPIO2A1_SHIFT = 4,
185 GPIO2A1_MASK = GENMASK(6, 4),
186 GPIO2A1_GPIO = 0,
187 GPIO2A1_SDMMC0_CMD,
188 GPIO2A1_PWM10_M1,
189 GPIO2A1_UART5_RXM0,
190 GPIO2A1_CAN0_TXM1,
191
192 /* GRF_GPIO2A_IOMUX_H */
193 GPIO2A7_SHIFT = 12,
194 GPIO2A7_MASK = GENMASK(14, 12),
195 GPIO2A7_GPIO = 0,
196 GPIO2A7_SDMMC1_CMD,
197 GPIO2A7_GMAC0_TXD3,
198 GPIO2A7_UART9_RXM0,
199
200 GPIO2A6_SHIFT = 8,
201 GPIO2A6_MASK = GENMASK(10, 8),
202 GPIO2A6_GPIO = 0,
203 GPIO2A6_SDMMC1_D3,
204 GPIO2A6_GMAC0_TXD2,
205 GPIO2A6_UART7_TXM0,
206
207 GPIO2A5_SHIFT = 4,
208 GPIO2A5_MASK = GENMASK(6, 4),
209 GPIO2A5_GPIO = 0,
210 GPIO2A5_SDMMC1_D2,
211 GPIO2A5_GMAC0_RXCLK,
212 GPIO2A5_UART7_RXM0,
213
214 GPIO2A4_SHIFT = 0,
215 GPIO2A4_MASK = GENMASK(2, 0),
216 GPIO2A4_GPIO = 0,
217 GPIO2A4_SDMMC1_D1,
218 GPIO2A4_GMAC0_RXD3,
219 GPIO2A4_UART6_TXM0,
220
221 /* GRF_GPIO2B_IOMUX_L */
222 GPIO2B3_SHIFT = 12,
223 GPIO2B3_MASK = GENMASK(14, 12),
224 GPIO2B3_GPIO = 0,
225 GPIO2B3_GMAC0_TXD0,
226 GPIO2B3_UART1_RXM0,
227
228 GPIO2B0_SHIFT = 0,
229 GPIO2B0_MASK = GENMASK(2, 0),
230 GPIO2B0_GPIO = 0,
231 GPIO2B0_SDMMC1_CLK,
232 GPIO2B0_GMAC0_TXCLK,
233 GPIO2B0_UART9_TXM0,
234
235 /* GRF_GPIO2B_IOMUX_H */
236 GPIO2B4_SHIFT = 0,
237 GPIO2B4_MASK = GENMASK(2, 0),
238 GPIO2B4_GPIO = 0,
239 GPIO2B4_GMAC0_TXD1,
240 GPIO2B4_UART1_TXM0,
241
242 /* GRF_GPIO2C_IOMUX_L */
243 GPIO2C2_SHIFT = 8,
244 GPIO2C2_MASK = GENMASK(10, 8),
245 GPIO2C2_GPIO = 0,
246 GPIO2C2_GMAC0_MCLKINOUT = 2,
247
248 /* GRF_GPIO2C_IOMUX_H */
249 GPIO2C6_SHIFT = 8,
250 GPIO2C6_MASK = GENMASK(10, 8),
251 GPIO2C6_GPIO = 0,
252 GPIO2C6_CLK32K_OUT1,
253 GPIO2C6_UART8_RXM0,
254 GPIO2C6_SPI1_CS1M0,
255
256 GPIO2C5_SHIFT = 4,
257 GPIO2C5_MASK = GENMASK(6, 4),
258 GPIO2C5_GPIO = 0,
259 GPIO2C5_I2S2_SDIM0,
260 GPIO2C5_GMAC0_RXER,
261 GPIO2C5_UART8_TXM0,
262 GPIO2C5_SPI2_CS1M0,
263
264 /* GRF_GPIO2D_IOMUX_H */
265 GPIO2D7_SHIFT = 12,
266 GPIO2D7_MASK = GENMASK(14, 12),
267 GPIO2D7_GPIO = 0,
268 GPIO2D7_LCDC_D7,
269 GPIO2D7_BT656_D7M0,
270 GPIO2D7_SPI2_MISOM1,
271 GPIO2D7_UART8_TXM1,
272 GPIO2D7_I2S1_SDO0M2,
273
274 /* GRF_GPIO3A_IOMUX_L */
275 GPIO3A0_SHIFT = 0,
276 GPIO3A0_MASK = GENMASK(2, 0),
277 GPIO3A0_GPIO = 0,
278 GPIO3A0_LCDC_CLK,
279 GPIO3A0_BT656_CLKM0,
280 GPIO3A0_SPI2_CLKM1,
281 GPIO3A0_UART8_RXM1,
282 GPIO3A0_I2S1_SDO1M2,
283
284 /* GRF_GPIO3B_IOMUX_L */
285 GPIO3B2_SHIFT = 8,
286 GPIO3B2_MASK = GENMASK(10, 8),
287 GPIO3B2_GPIO = 0,
288 GPIO3B2_LCDC_D17,
289 GPIO3B2_BT1120_D8,
290 GPIO3B2_GMAC1_RXD1M0,
291 GPIO3B2_UART4_TXM1,
292 GPIO3B2_PWM9_M0,
293
294 GPIO3B1_SHIFT = 4,
295 GPIO3B1_MASK = GENMASK(6, 4),
296 GPIO3B1_GPIO = 0,
297 GPIO3B1_LCDC_D16,
298 GPIO3B1_BT1120_D7,
299 GPIO3B1_GMAC1_RXD0M0,
300 GPIO3B1_UART4_RXM1,
301 GPIO3B1_PWM8_M0,
302
303 /* GRF_GPIO3B_IOMUX_H */
304 GPIO3B7_SHIFT = 12,
305 GPIO3B7_MASK = GENMASK(14, 12),
306 GPIO3B7_GPIO = 0,
307 GPIO3B7_LCDC_D22,
308 GPIO3B7_PWM12_M0,
309 GPIO3B7_GMAC1_TXENM0,
310 GPIO3B7_UART3_TXM1,
311 GPIO3B7_PDM_SDI2M2,
312
313 /* GRF_GPIO3C_IOMUX_L */
314 GPIO3C3_SHIFT = 12,
315 GPIO3C3_MASK = GENMASK(14, 12),
316 GPIO3C3_GPIO = 0,
317 GPIO3C3_LCDC_DEN,
318 GPIO3C3_BT1120_D15,
319 GPIO3C3_SPI1_CLKM1,
320 GPIO3C3_UART5_RXM1,
321 GPIO3C3_I2S1_SCLKRXM,
322
323 GPIO3C2_SHIFT = 8,
324 GPIO3C2_MASK = GENMASK(10, 8),
325 GPIO3C2_GPIO = 0,
326 GPIO3C2_LCDC_VSYNC,
327 GPIO3C2_BT1120_D14,
328 GPIO3C2_SPI1_MISOM1,
329 GPIO3C2_UART5_TXM1,
330 GPIO3C2_I2S1_SDO3M2,
331
332 GPIO3C0_SHIFT = 0,
333 GPIO3C0_MASK = GENMASK(2, 0),
334 GPIO3C0_GPIO = 0,
335 GPIO3C0_LCDC_D23,
336 GPIO3C0_PWM13_M0,
337 GPIO3C0_GMAC1_MCLKINOUTM0,
338 GPIO3C0_UART3_RXM1,
339 GPIO3C0_PDM_SDI3M2,
340
341 /* GRF_GPIO3C_IOMUX_H */
342 GPIO3C5_SHIFT = 4,
343 GPIO3C5_MASK = GENMASK(6, 4),
344 GPIO3C5_GPIO = 0,
345 GPIO3C5_PWM15_IRM0,
346 GPIO3C5_SPDIF_TXM1,
347 GPIO3C5_GMAC1_MDIOM0,
348 GPIO3C5_UART7_RXM1,
349 GPIO3C5_I2S1_LRCKRXM2,
350
351 GPIO3C4_SHIFT = 0,
352 GPIO3C4_MASK = GENMASK(2, 0),
353 GPIO3C4_GPIO = 0,
354 GPIO3C4_PWM14_M0,
355 GPIO3C4_VOP_PWMM1,
356 GPIO3C4_GMAC1_MDCM0,
357 GPIO3C4_UART7_TXM1,
358 GPIO3C4_PDM_CLK1M2,
359
360 /* GRF_GPIO3D_IOMUX_H */
361 GPIO3D7_SHIFT = 12,
362 GPIO3D7_MASK = GENMASK(14, 12),
363 GPIO3D7_GPIO = 0,
364 GPIO3D7_CIF_D9,
365 GPIO3D7_EBC_SDDO9,
366 GPIO3D7_GMAC1_TXD3M1,
367 GPIO3D7_UART1_RXM1,
368 GPIO3D7_PDM_SDI0M1,
369
370 GPIO3D6_SHIFT = 8,
371 GPIO3D6_MASK = GENMASK(10, 8),
372 GPIO3D6_GPIO = 0,
373 GPIO3D6_CIF_D8,
374 GPIO3D6_EBC_SDDO8,
375 GPIO3D6_GMAC1_TXD2M1,
376 GPIO3D6_UART1_TXM1,
377 GPIO3D6_PDM_CLK0M1,
378
379 /* GRF_GPIO4A_IOMUX_L */
380 GPIO4A3_SHIFT = 12,
381 GPIO4A3_MASK = GENMASK(14, 12),
382 GPIO4A3_GPIO = 0,
383 GPIO4A3_CIF_D13,
384 GPIO4A3_EBC_SDDO13,
385 GPIO4A3_GMAC1_RXCLKM1,
386 GPIO4A3_UART7_RXM2,
387 GPIO4A3_PDM_SDI3M1,
388
389 GPIO4A2_SHIFT = 8,
390 GPIO4A2_MASK = GENMASK(10, 8),
391 GPIO4A2_GPIO = 0,
392 GPIO4A2_CIF_D12,
393 GPIO4A2_EBC_SDDO12,
394 GPIO4A2_GMAC1_RXD3M1,
395 GPIO4A2_UART7_TXM2,
396 GPIO4A2_PDM_SDI2M1,
397
398 /* GRF_GPIO4A_IOMUX_H */
399 GPIO4A5_SHIFT = 4,
400 GPIO4A5_MASK = GENMASK(6, 4),
401 GPIO4A5_GPIO = 0,
402 GPIO4A5_CIF_D15,
403 GPIO4A5_EBC_SDDO15,
404 GPIO4A5_GMAC1_TXD1M1,
405 GPIO4A5_UART9_RXM2,
406 GPIO4A5_I2S2_LRCKRXM1,
407
408 GPIO4A4_SHIFT = 0,
409 GPIO4A4_MASK = GENMASK(2, 0),
410 GPIO4A4_GPIO = 0,
411 GPIO4A4_CIF_D14,
412 GPIO4A4_EBC_SDDO14,
413 GPIO4A4_GMAC1_TXD0M1,
414 GPIO4A4_UART9_TXM2,
415 GPIO4A4_I2S2_LRCKTXM1,
416
417 /* GRF_GPIO4C_IOMUX_L */
418 GPIO4C1_SHIFT = 4,
419 GPIO4C1_MASK = GENMASK(6, 4),
420 GPIO4C1_GPIO = 0,
421 GPIO4C1_CIF_CLKIN,
422 GPIO4C1_EBC_SDCLK,
423 GPIO4C1_GMAC1_MCLKINOUTM1,
424
425 /* GRF_GPIO4C_IOMUX_H */
426 GPIO4C6_SHIFT = 8,
427 GPIO4C6_MASK = GENMASK(10, 8),
428 GPIO4C6_GPIO = 0,
429 GPIO4C6_PWM13_M1,
430 GPIO4C6_SPI3_CS0M1,
431 GPIO4C6_SATA0_ACTLED,
432 GPIO4C6_UART9_RXM1,
433 GPIO4C6_I2S3_SDIM1,
434
435 GPIO4C5_SHIFT = 4,
436 GPIO4C5_MASK = GENMASK(6, 4),
437 GPIO4C5_GPIO = 0,
438 GPIO4C5_PWM12_M1,
439 GPIO4C5_SPI3_MISOM1,
440 GPIO4C5_SATA1_ACTLED,
441 GPIO4C5_UART9_TXM1,
442 GPIO4C5_I2S3_SDOM1,
443
444 /* GRF_IOFUNC_SEL3 */
445 UART4_IO_SEL_SHIFT = 14,
446 UART4_IO_SEL_MASK = GENMASK(14, 14),
447 UART4_IO_SEL_M0 = 0,
448 UART4_IO_SEL_M1,
449
450 UART3_IO_SEL_SHIFT = 12,
451 UART3_IO_SEL_MASK = GENMASK(12, 12),
452 UART3_IO_SEL_M0 = 0,
453 UART3_IO_SEL_M1,
454
455 UART2_IO_SEL_SHIFT = 10,
456 UART2_IO_SEL_MASK = GENMASK(11, 10),
457 UART2_IO_SEL_M0 = 0,
458 UART2_IO_SEL_M1,
459
460 UART1_IO_SEL_SHIFT = 8,
461 UART1_IO_SEL_MASK = GENMASK(8, 8),
462 UART1_IO_SEL_M0 = 0,
463 UART1_IO_SEL_M1,
464
465 /* GRF_IOFUNC_SEL4 */
466 UART9_IO_SEL_SHIFT = 8,
467 UART9_IO_SEL_MASK = GENMASK(9, 8),
468 UART9_IO_SEL_M0 = 0,
469 UART9_IO_SEL_M1,
470 UART9_IO_SEL_M2,
471
472 UART8_IO_SEL_SHIFT = 6,
473 UART8_IO_SEL_MASK = GENMASK(6, 6),
474 UART8_IO_SEL_M0 = 0,
475 UART8_IO_SEL_M1,
476
477 UART7_IO_SEL_SHIFT = 4,
478 UART7_IO_SEL_MASK = GENMASK(5, 4),
479 UART7_IO_SEL_M0 = 0,
480 UART7_IO_SEL_M1,
481 UART7_IO_SEL_M2,
482
483 UART6_IO_SEL_SHIFT = 2,
484 UART6_IO_SEL_MASK = GENMASK(2, 2),
485 UART6_IO_SEL_M0 = 0,
486 UART6_IO_SEL_M1,
487
488 UART5_IO_SEL_SHIFT = 0,
489 UART5_IO_SEL_MASK = GENMASK(0, 0),
490 UART5_IO_SEL_M0 = 0,
491 UART5_IO_SEL_M1,
492 };
493
494 #ifdef CONFIG_ARM64
495 #include <asm/armv8/mmu.h>
496
497 static struct mm_region rk3568_mem_map[] = {
498 {
499 .virt = 0x0UL,
500 .phys = 0x0UL,
501 .size = 0xf0000000UL,
502 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
503 PTE_BLOCK_INNER_SHARE
504 }, {
505 .virt = 0xf0000000UL,
506 .phys = 0xf0000000UL,
507 .size = 0x10000000UL,
508 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
509 PTE_BLOCK_NON_SHARE |
510 PTE_BLOCK_PXN | PTE_BLOCK_UXN
511 }, {
512 .virt = 0x100000000UL,
513 .phys = 0x100000000UL,
514 .size = 0x100000000UL,
515 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
516 PTE_BLOCK_INNER_SHARE
517 }, {
518 .virt = 0x300000000,
519 .phys = 0x300000000,
520 .size = 0x0c0c00000,
521 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
522 PTE_BLOCK_NON_SHARE |
523 PTE_BLOCK_PXN | PTE_BLOCK_UXN
524 }, {
525 /* List terminator */
526 0,
527 }
528 };
529
530 struct mm_region *mem_map = rk3568_mem_map;
531 #endif
532
board_debug_uart_init(void)533 void board_debug_uart_init(void)
534 {
535 #if defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xfdd50000)
536 static struct rk3568_pmugrf * const pmugrf = (void *)PMUGRF_BASE;
537 /* UART0 M0 */
538 rk_clrsetreg(&pmugrf->pmu_soc_con0, UART0_IO_SEL_MASK,
539 UART0_IO_SEL_M0 << UART0_IO_SEL_SHIFT);
540
541 /* Switch iomux */
542 rk_clrsetreg(&pmugrf->pmu_gpio0c_iomux_l,
543 GPIO0C1_MASK | GPIO0C0_MASK,
544 GPIO0C1_UART0_TX << GPIO0C1_SHIFT |
545 GPIO0C0_UART0_RX << GPIO0C0_SHIFT);
546
547 #elif defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xfe650000)
548 static struct rk3568_grf * const grf = (void *)GRF_BASE;
549
550 #if defined(CONFIG_ROCKCHIP_UART_MUX_SEL_M) && \
551 (CONFIG_ROCKCHIP_UART_MUX_SEL_M == 0)
552 /* UART1 M0 */
553 rk_clrsetreg(&grf->iofunc_sel3, UART1_IO_SEL_MASK,
554 UART1_IO_SEL_M0 << UART1_IO_SEL_SHIFT);
555
556 /* Switch iomux */
557 rk_clrsetreg(&grf->gpio2b_iomux_l,
558 GPIO2B3_MASK, GPIO2B3_UART1_RXM0 << GPIO2B3_SHIFT);
559 rk_clrsetreg(&grf->gpio2b_iomux_h,
560 GPIO2B4_MASK, GPIO2B4_UART1_TXM0 << GPIO2B4_SHIFT);
561 #else
562 /* UART1 M1 */
563 rk_clrsetreg(&grf->iofunc_sel3, UART1_IO_SEL_MASK,
564 UART1_IO_SEL_M1 << UART1_IO_SEL_SHIFT);
565
566 /* Switch iomux */
567 rk_clrsetreg(&grf->gpio3d_iomux_h,
568 GPIO3D7_MASK | GPIO3D6_MASK,
569 GPIO3D7_UART1_RXM1 << GPIO3D7_SHIFT |
570 GPIO3D6_UART1_TXM1 << GPIO3D6_SHIFT);
571 #endif
572 #elif defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xfe660000)
573 static struct rk3568_grf * const grf = (void *)GRF_BASE;
574
575 #if defined(CONFIG_ROCKCHIP_UART_MUX_SEL_M) && \
576 (CONFIG_ROCKCHIP_UART_MUX_SEL_M == 0)
577 static struct rk3568_pmugrf * const pmugrf = (void *)PMUGRF_BASE;
578 /* UART2 M0 */
579 rk_clrsetreg(&grf->iofunc_sel3, UART2_IO_SEL_MASK,
580 UART2_IO_SEL_M0 << UART2_IO_SEL_SHIFT);
581
582 /* Switch iomux */
583 rk_clrsetreg(&pmugrf->pmu_gpio0d_iomux_l,
584 GPIO0D1_MASK | GPIO0D0_MASK,
585 GPIO0D1_UART2_TXM0 << GPIO0D1_SHIFT |
586 GPIO0D0_UART2_RXM0 << GPIO0D0_SHIFT);
587 #else
588 /* UART2 M1 */
589 rk_clrsetreg(&grf->iofunc_sel3, UART2_IO_SEL_MASK,
590 UART2_IO_SEL_M1 << UART2_IO_SEL_SHIFT);
591
592 /* Switch iomux */
593 rk_clrsetreg(&grf->gpio1d_iomux_h,
594 GPIO1D6_MASK | GPIO1D5_MASK,
595 GPIO1D6_UART2_RXM1 << GPIO1D6_SHIFT |
596 GPIO1D5_UART2_TXM1 << GPIO1D5_SHIFT);
597 #endif
598 #elif defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xfe670000)
599 static struct rk3568_grf * const grf = (void *)GRF_BASE;
600
601 #if defined(CONFIG_ROCKCHIP_UART_MUX_SEL_M) && \
602 (CONFIG_ROCKCHIP_UART_MUX_SEL_M == 0)
603 /* UART3 M0 */
604 rk_clrsetreg(&grf->iofunc_sel3, UART3_IO_SEL_MASK,
605 UART3_IO_SEL_M0 << UART3_IO_SEL_SHIFT);
606
607 /* Switch iomux */
608 rk_clrsetreg(&grf->gpio1a_iomux_l,
609 GPIO1A1_MASK | GPIO1A0_MASK,
610 GPIO1A1_UART3_TXM0 << GPIO1A1_SHIFT |
611 GPIO1A0_UART3_RXM0 << GPIO1A0_SHIFT);
612 #else
613 /* UART3 M1 */
614 rk_clrsetreg(&grf->iofunc_sel3, UART3_IO_SEL_MASK,
615 UART3_IO_SEL_M1 << UART3_IO_SEL_SHIFT);
616
617 /* Switch iomux */
618 rk_clrsetreg(&grf->gpio3b_iomux_h,
619 GPIO3B7_MASK, GPIO3B7_UART3_TXM1 << GPIO3B7_SHIFT);
620 rk_clrsetreg(&grf->gpio3c_iomux_l,
621 GPIO3C0_MASK, GPIO3C0_UART3_RXM1 << GPIO3C0_SHIFT);
622 #endif
623 #elif defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xfe680000)
624 static struct rk3568_grf * const grf = (void *)GRF_BASE;
625
626 #if defined(CONFIG_ROCKCHIP_UART_MUX_SEL_M) && \
627 (CONFIG_ROCKCHIP_UART_MUX_SEL_M == 0)
628 /* UART4 M0 */
629 rk_clrsetreg(&grf->iofunc_sel3, UART4_IO_SEL_MASK,
630 UART4_IO_SEL_M0 << UART4_IO_SEL_SHIFT);
631
632 /* Switch iomux */
633 rk_clrsetreg(&grf->gpio1a_iomux_h,
634 GPIO1A6_MASK | GPIO1A4_MASK,
635 GPIO1A6_UART4_TXM0 << GPIO1A6_SHIFT |
636 GPIO1A4_UART4_RXM0 << GPIO1A4_SHIFT);
637 #else
638 /* UART4 M1 */
639 rk_clrsetreg(&grf->iofunc_sel3, UART4_IO_SEL_MASK,
640 UART4_IO_SEL_M1 << UART4_IO_SEL_SHIFT);
641
642 /* Switch iomux */
643 rk_clrsetreg(&grf->gpio3b_iomux_l,
644 GPIO3B2_MASK | GPIO3B1_MASK,
645 GPIO3B2_UART4_TXM1 << GPIO3B2_SHIFT |
646 GPIO3B1_UART4_RXM1 << GPIO3B1_SHIFT);
647 #endif
648 #elif defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xfe690000)
649 static struct rk3568_grf * const grf = (void *)GRF_BASE;
650
651 #if defined(CONFIG_ROCKCHIP_UART_MUX_SEL_M) && \
652 (CONFIG_ROCKCHIP_UART_MUX_SEL_M == 0)
653 /* UART5 M0 */
654 rk_clrsetreg(&grf->iofunc_sel4, UART5_IO_SEL_MASK,
655 UART5_IO_SEL_M0 << UART5_IO_SEL_SHIFT);
656
657 /* Switch iomux */
658 rk_clrsetreg(&grf->gpio2a_iomux_l,
659 GPIO2A2_MASK | GPIO2A1_MASK,
660 GPIO2A2_UART5_TXM0 << GPIO2A2_SHIFT |
661 GPIO2A1_UART5_RXM0 << GPIO2A1_SHIFT);
662 #else
663 /* UART5 M1 */
664 rk_clrsetreg(&grf->iofunc_sel4, UART5_IO_SEL_MASK,
665 UART5_IO_SEL_M1 << UART5_IO_SEL_SHIFT);
666
667 /* Switch iomux */
668 rk_clrsetreg(&grf->gpio3c_iomux_l,
669 GPIO3C3_MASK | GPIO3C2_MASK,
670 GPIO3C3_UART5_RXM1 << GPIO3C3_SHIFT |
671 GPIO3C2_UART5_TXM1 << GPIO3C2_SHIFT);
672 #endif
673 #elif defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xfe6a0000)
674 static struct rk3568_grf * const grf = (void *)GRF_BASE;
675
676 #if defined(CONFIG_ROCKCHIP_UART_MUX_SEL_M) && \
677 (CONFIG_ROCKCHIP_UART_MUX_SEL_M == 0)
678 /* UART6 M0 */
679 rk_clrsetreg(&grf->iofunc_sel4, UART6_IO_SEL_MASK,
680 UART6_IO_SEL_M0 << UART6_IO_SEL_SHIFT);
681
682 /* Switch iomux */
683 rk_clrsetreg(&grf->gpio2a_iomux_l,
684 GPIO2A3_MASK, GPIO2A3_UART6_RXM0 << GPIO2A3_SHIFT);
685 rk_clrsetreg(&grf->gpio2a_iomux_h,
686 GPIO2A4_MASK, GPIO2A4_UART6_TXM0 << GPIO2A4_SHIFT);
687 #else
688 /* UART6 M1 */
689 rk_clrsetreg(&grf->iofunc_sel4, UART6_IO_SEL_MASK,
690 UART6_IO_SEL_M1 << UART6_IO_SEL_SHIFT);
691
692 /* Switch iomux */
693 rk_clrsetreg(&grf->gpio1d_iomux_h,
694 GPIO1D6_MASK | GPIO1D5_MASK,
695 GPIO1D6_UART6_RXM1 << GPIO1D6_SHIFT |
696 GPIO1D5_UART6_TXM1 << GPIO1D5_SHIFT);
697 #endif
698 #elif defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xfe6b0000)
699 static struct rk3568_grf * const grf = (void *)GRF_BASE;
700
701 #if defined(CONFIG_ROCKCHIP_UART_MUX_SEL_M) && \
702 (CONFIG_ROCKCHIP_UART_MUX_SEL_M == 0)
703 /* UART7 M0 */
704 rk_clrsetreg(&grf->iofunc_sel4, UART7_IO_SEL_MASK,
705 UART7_IO_SEL_M0 << UART7_IO_SEL_SHIFT);
706
707 /* Switch iomux */
708 rk_clrsetreg(&grf->gpio2a_iomux_h,
709 GPIO2A6_MASK | GPIO2A5_MASK,
710 GPIO2A6_UART7_TXM0 << GPIO2A6_SHIFT |
711 GPIO2A5_UART7_RXM0 << GPIO2A5_SHIFT);
712 #elif defined(CONFIG_ROCKCHIP_UART_MUX_SEL_M) && \
713 (CONFIG_ROCKCHIP_UART_MUX_SEL_M == 1)
714 /* UART7 M1 */
715 rk_clrsetreg(&grf->iofunc_sel4, UART7_IO_SEL_MASK,
716 UART7_IO_SEL_M1 << UART7_IO_SEL_SHIFT);
717
718 /* Switch iomux */
719 rk_clrsetreg(&grf->gpio3c_iomux_h,
720 GPIO3C5_MASK | GPIO3C4_MASK,
721 GPIO3C5_UART7_RXM1 << GPIO3C5_SHIFT |
722 GPIO3C4_UART7_TXM1 << GPIO3C4_SHIFT);
723 #else
724 /* UART7 M2 */
725 rk_clrsetreg(&grf->iofunc_sel4, UART7_IO_SEL_MASK,
726 UART7_IO_SEL_M2 << UART7_IO_SEL_SHIFT);
727
728 /* Switch iomux */
729 rk_clrsetreg(&grf->gpio4a_iomux_l,
730 GPIO4A3_MASK | GPIO4A2_MASK,
731 GPIO4A3_UART7_RXM2 << GPIO4A3_SHIFT |
732 GPIO4A2_UART7_TXM2 << GPIO4A2_SHIFT);
733 #endif
734 #elif defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xfe6c0000)
735 static struct rk3568_grf * const grf = (void *)GRF_BASE;
736
737 #if defined(CONFIG_ROCKCHIP_UART_MUX_SEL_M) && \
738 (CONFIG_ROCKCHIP_UART_MUX_SEL_M == 0)
739 /* UART8 M0 */
740 rk_clrsetreg(&grf->iofunc_sel4, UART8_IO_SEL_MASK,
741 UART8_IO_SEL_M0 << UART8_IO_SEL_SHIFT);
742
743 /* Switch iomux */
744 rk_clrsetreg(&grf->gpio2c_iomux_h,
745 GPIO2C6_MASK | GPIO2C5_MASK,
746 GPIO2C6_UART8_RXM0 << GPIO2C6_SHIFT |
747 GPIO2C5_UART8_TXM0 << GPIO2C5_SHIFT);
748 #else
749 /* UART8 M1 */
750 rk_clrsetreg(&grf->iofunc_sel4, UART8_IO_SEL_MASK,
751 UART8_IO_SEL_M1 << UART8_IO_SEL_SHIFT);
752
753 /* Switch iomux */
754 rk_clrsetreg(&grf->gpio2d_iomux_h,
755 GPIO2D7_MASK | GPIO3A0_MASK,
756 GPIO2D7_UART8_TXM1 << GPIO2D7_SHIFT |
757 GPIO3A0_UART8_RXM1 << GPIO3A0_SHIFT);
758 #endif
759 #elif defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xfe6d0000)
760 static struct rk3568_grf * const grf = (void *)GRF_BASE;
761
762 #if defined(CONFIG_ROCKCHIP_UART_MUX_SEL_M) && \
763 (CONFIG_ROCKCHIP_UART_MUX_SEL_M == 0)
764 /* UART9 M0 */
765 rk_clrsetreg(&grf->iofunc_sel4, UART9_IO_SEL_MASK,
766 UART9_IO_SEL_M0 << UART9_IO_SEL_SHIFT);
767
768 /* Switch iomux */
769 rk_clrsetreg(&grf->gpio2a_iomux_h,
770 GPIO2A7_MASK, GPIO2A7_UART9_RXM0 << GPIO2A7_SHIFT);
771 rk_clrsetreg(&grf->gpio2b_iomux_l,
772 GPIO2B0_MASK, GPIO2B0_UART9_TXM0 << GPIO2B0_SHIFT);
773 #elif defined(CONFIG_ROCKCHIP_UART_MUX_SEL_M) && \
774 (CONFIG_ROCKCHIP_UART_MUX_SEL_M == 1)
775 /* UART9 M1 */
776 rk_clrsetreg(&grf->iofunc_sel4, UART9_IO_SEL_MASK,
777 UART9_IO_SEL_M1 << UART9_IO_SEL_SHIFT);
778
779 /* Switch iomux */
780 rk_clrsetreg(&grf->gpio4c_iomux_h,
781 GPIO4C6_MASK | GPIO4C5_MASK,
782 GPIO4C6_UART9_RXM1 << GPIO4C6_SHIFT |
783 GPIO4C5_UART9_TXM1 << GPIO4C5_SHIFT);
784 #else
785 /* UART9 M2 */
786 rk_clrsetreg(&grf->iofunc_sel4, UART9_IO_SEL_MASK,
787 UART9_IO_SEL_M2 << UART9_IO_SEL_SHIFT);
788
789 /* Switch iomux */
790 rk_clrsetreg(&grf->gpio4a_iomux_h,
791 GPIO4A5_MASK | GPIO4A4_MASK,
792 GPIO4A5_UART9_RXM2 << GPIO4A5_SHIFT |
793 GPIO4A4_UART9_TXM2 << GPIO4A4_SHIFT);
794 #endif
795 #endif
796 }
797
fit_standalone_release(char * id,uintptr_t entry_point)798 int fit_standalone_release(char *id, uintptr_t entry_point)
799 {
800 /* risc-v configuration: */
801 /* Reset the scr1 */
802 writel(0x04000400, CRU_BASE + CRU_SOFTRST_CON26);
803 udelay(100);
804
805 /* set the scr1 addr */
806 writel((0xffff0000) | (entry_point >> 16), GRF_BASE + GRF_SOC_CON4);
807 udelay(10);
808
809 /* release the scr1 */
810 writel(0x04000000, CRU_BASE + CRU_SOFTRST_CON26);
811
812 return 0;
813 }
814
815 #if defined(CONFIG_SPL_BUILD) && !defined(CONFIG_TPL_BUILD)
qos_priority_init(void)816 static void qos_priority_init(void)
817 {
818 u32 delay;
819
820 /* enable all pd except npu and gpu */
821 writel(0xffff0000 & ~(BIT(0 + 16) | BIT(1 + 16)),
822 PMU_BASE_ADDR + PMU_PWR_GATE_SFTCON);
823 delay = 1000;
824 do {
825 udelay(1);
826 delay--;
827 if (delay == 0) {
828 printf("Fail to set domain.");
829 hang();
830 }
831 } while (readl(PMU_BASE_ADDR + PMU_PWR_DWN_ST) & ~(BIT(0) | BIT(1)));
832
833 /* release all idle request except npu and gpu */
834 writel(0xffff0000 & ~(BIT(1 + 16) | BIT(2 + 16)),
835 PMU_BASE_ADDR + PMU_BUS_IDLE_SFTCON0);
836
837 delay = 1000;
838 /* wait ack status */
839 do {
840 udelay(1);
841 delay--;
842 if (delay == 0) {
843 printf("Fail to get ack on domain.\n");
844 hang();
845 }
846 } while (readl(PMU_BASE_ADDR + PMU_BUS_IDLE_ACK) & ~(BIT(1) | BIT(2)));
847
848 delay = 1000;
849 /* wait idle status */
850 do {
851 udelay(1);
852 delay--;
853 if (delay == 0) {
854 printf("Fail to set idle on domain.\n");
855 hang();
856 }
857 } while (readl(PMU_BASE_ADDR + PMU_BUS_IDLE_ST) & ~(BIT(1) | BIT(2)));
858
859 writel(0x303, EBC_PRIORITY_REG);
860 }
861 #endif
862
arch_cpu_init(void)863 int arch_cpu_init(void)
864 {
865 #ifdef CONFIG_SPL_BUILD
866 /*
867 * When perform idle operation, corresponding clock can
868 * be opened or gated automatically.
869 */
870 writel(0xffffffff, PMU_BASE_ADDR + PMU_NOC_AUTO_CON0);
871 writel(0x000f000f, PMU_BASE_ADDR + PMU_NOC_AUTO_CON1);
872
873 /* Set the emmc sdmmc0 to secure */
874 writel(((0x3 << 11 | 0x1 << 4) << 16), SGRF_BASE + SGRF_SOC_CON4);
875 /* set the emmc ds to level 2 */
876 writel(0x3f3f0707, GRF_BASE + GRF_GPIO1B_DS_2);
877 writel(0x3f3f0707, GRF_BASE + GRF_GPIO1B_DS_3);
878 writel(0x3f3f0707, GRF_BASE + GRF_GPIO1C_DS_0);
879 writel(0x3f3f0707, GRF_BASE + GRF_GPIO1C_DS_1);
880 writel(0x3f3f0707, GRF_BASE + GRF_GPIO1C_DS_2);
881 writel(0x3f3f0707, GRF_BASE + GRF_GPIO1C_DS_3);
882
883 #if defined(CONFIG_ROCKCHIP_SFC)
884 /* Set the fspi to secure */
885 writel(((0x1 << 14) << 16) | (0x0 << 14), SGRF_BASE + SGRF_SOC_CON3);
886 #endif
887
888 #ifndef CONFIG_TPL_BUILD
889 /* set the fspi d0~3 cs0 to level 2 */
890 if (get_bootdev_by_brom_bootsource() == BOOT_TYPE_SPI_NOR ||
891 get_bootdev_by_brom_bootsource() == BOOT_TYPE_SPI_NAND) {
892 writel(0x3f000700, GRF_BASE + GRF_GPIO1C_DS_3);
893 writel(0x3f000700, GRF_BASE + GRF_GPIO1D_DS_0);
894 writel(0x3f3f0707, GRF_BASE + GRF_GPIO1D_DS_1);
895 writel(0x003f0007, GRF_BASE + GRF_GPIO1D_DS_2);
896 }
897 #endif
898
899 /* Set core pvtpll ring length */
900 writel(0x00ff002b, CPU_GRF_BASE + GRF_CORE_PVTPLL_CON0);
901
902 /*
903 * Assert reset the pipephy0, pipephy1 and pipephy2,
904 * and de-assert reset them in Kernel combphy driver.
905 */
906 writel(0x02a002a0, CRU_BASE + CRU_SOFTRST_CON28);
907
908 /*
909 * Set USB 2.0 PHY0 port1 and PHY1 port0 and port1
910 * enter suspend mode to to save power. And USB 2.0
911 * PHY0 port0 for OTG interface still in normal mode.
912 */
913 writel(0x01ff01d1, USBPHY_U3_GRF_CON1);
914 writel(0x01ff01d1, USBPHY_U2_GRF_CON0);
915 writel(0x01ff01d1, USBPHY_U2_GRF_CON1);
916
917 #ifndef CONFIG_TPL_BUILD
918 qos_priority_init();
919 #endif
920 #elif defined(CONFIG_SUPPORT_USBPLUG)
921 /*
922 * When perform idle operation, corresponding clock can
923 * be opened or gated automatically.
924 */
925 writel(0xffffffff, PMU_BASE_ADDR + PMU_NOC_AUTO_CON0);
926 writel(0x000f000f, PMU_BASE_ADDR + PMU_NOC_AUTO_CON1);
927
928 writel(0x00030000, SGRF_BASE + SGRF_SOC_CON4); /* usb3otg0 master secure setting */
929
930 /* Set the emmc sdmmc0 to secure */
931 writel(((0x3 << 11 | 0x1 << 4) << 16), SGRF_BASE + SGRF_SOC_CON4);
932 /* set the emmc ds to level 2 */
933 writel(0x3f3f0707, GRF_BASE + GRF_GPIO1B_DS_2);
934 writel(0x3f3f0707, GRF_BASE + GRF_GPIO1B_DS_3);
935 writel(0x3f3f0707, GRF_BASE + GRF_GPIO1C_DS_0);
936 writel(0x3f3f0707, GRF_BASE + GRF_GPIO1C_DS_1);
937 writel(0x3f3f0707, GRF_BASE + GRF_GPIO1C_DS_2);
938 writel(0x3f3f0707, GRF_BASE + GRF_GPIO1C_DS_3);
939
940 /* emmc and sfc iomux */
941 writel((0x7777UL << 16) | (0x1111), GRF_BASE + GRF_GPIO1B_IOMUX_H);
942 writel((0x7777UL << 16) | (0x1111), GRF_BASE + GRF_GPIO1C_IOMUX_L);
943 writel((0x7777UL << 16) | (0x2111), GRF_BASE + GRF_GPIO1C_IOMUX_H);
944 writel((0x7777UL << 16) | (0x1111), GRF_BASE + GRF_GPIO1D_IOMUX_L);
945 writel(((7 << 0) << 16) | (1 << 0), GRF_BASE + GRF_GPIO1D_IOMUX_H);
946
947 /* Set the fspi to secure */
948 writel(((0x1 << 14) << 16) | (0x0 << 14), SGRF_BASE + SGRF_SOC_CON3);
949 #else /* U-Boot */
950 /* uboot: config iomux */
951 #if defined(CONFIG_ROCKCHIP_SFC_IOMUX)
952 writel((0x70002000), GRF_BASE + GRF_GPIO1C_IOMUX_H);
953 writel((0x77771111), GRF_BASE + GRF_GPIO1D_IOMUX_L);
954 writel((0x00070001), GRF_BASE + GRF_GPIO1D_IOMUX_H);
955 #elif defined(CONFIG_ROCKCHIP_EMMC_IOMUX)
956 writel((0x77771111), GRF_BASE + GRF_GPIO1B_IOMUX_H);
957 writel((0x77771111), GRF_BASE + GRF_GPIO1C_IOMUX_L);
958 writel((0x07770111), GRF_BASE + GRF_GPIO1C_IOMUX_H);
959 #endif
960 /*
961 * Set SATA FBSCP and PORTS_IMPL for kernel drivers
962 */
963 writel(SATA_FBS_ENABLE, SATA0_BASE_ADDR + SATA_PORT_CMD);
964 writel(1, SATA0_BASE_ADDR + SATA_PI);
965 writel(SATA_FBS_ENABLE, SATA1_BASE_ADDR + SATA_PORT_CMD);
966 writel(1, SATA1_BASE_ADDR + SATA_PI);
967 writel(SATA_FBS_ENABLE, SATA2_BASE_ADDR + SATA_PORT_CMD);
968 writel(1, SATA2_BASE_ADDR + SATA_PI);
969 #endif
970
971 return 0;
972 }
973
974 #ifdef CONFIG_SPL_BUILD
spl_fit_standalone_release(char * id,uintptr_t entry_point)975 int spl_fit_standalone_release(char *id, uintptr_t entry_point)
976 {
977 /* Reset the scr1 */
978 writel(0x04000400, CRU_BASE + CRU_SOFTRST_CON26);
979 udelay(100);
980 /* set the scr1 addr */
981 writel((0xffff0000) | (entry_point >> 16), GRF_BASE + GRF_SOC_CON4);
982 udelay(10);
983 /* release the scr1 */
984 writel(0x04000000, CRU_BASE + CRU_SOFTRST_CON26);
985
986 return 0;
987 }
988 #endif
989
990 #if CONFIG_IS_ENABLED(CLK_SCMI)
991 #include <dm.h>
992 /*
993 * armclk: 1104M:
994 * rockchip,clk-init = <1104000000>,
995 * vdd_cpu : regulator-init-microvolt = <825000>;
996 * armclk: 1416M(by default):
997 * rockchip,clk-init = <1416000000>,
998 * vdd_cpu : regulator-init-microvolt = <900000>;
999 * armclk: 1608M:
1000 * rockchip,clk-init = <1608000000>,
1001 * vdd_cpu : regulator-init-microvolt = <975000>;
1002 */
1003
set_armclk_rate(void)1004 int set_armclk_rate(void)
1005 {
1006 struct clk clk;
1007 u32 *rates = NULL;
1008 int ret, size, num_rates;
1009
1010 ret = rockchip_get_scmi_clk(&clk.dev);
1011 if (ret) {
1012 printf("Failed to get scmi clk dev\n");
1013 return ret;
1014 }
1015
1016 size = dev_read_size(clk.dev, "rockchip,clk-init");
1017 if (size < 0)
1018 return 0;
1019
1020 num_rates = size / sizeof(u32);
1021 rates = calloc(num_rates, sizeof(u32));
1022 if (!rates)
1023 return -ENOMEM;
1024
1025 ret = dev_read_u32_array(clk.dev, "rockchip,clk-init",
1026 rates, num_rates);
1027 if (ret) {
1028 printf("Cannot get rockchip,clk-init reg\n");
1029 return -EINVAL;
1030 }
1031 clk.id = 0;
1032 ret = clk_set_rate(&clk, rates[clk.id]);
1033 if (ret < 0) {
1034 printf("Failed to set armclk\n");
1035 return ret;
1036 }
1037 return 0;
1038 }
1039 #endif
1040
1041 #define CRU_NODE_FDT_PATH "/clock-controller@fdd20000"
1042 #define CRU_RATE_CNT_MIN 6
1043 #define CRU_PARENT_CNT_MIN 3
1044
1045 #define RKVDEC_NODE_FDT_PATH "/rkvdec@fdf80200"
1046 #define RKVDEC_NORMAL_RATE_CNT_MIN 5
1047 #define RKVDEC_RATE_CNT_MIN 4
1048
1049 #define GMAC0_NODE_FDT_PATH "/ethernet@fe2a0000"
1050 #define GMAC1_NODE_FDT_PATH "/ethernet@fe010000"
1051
1052 #define GMAC0_CLKIN_NODE_FDT_PATH "/external-gmac0-clock"
1053 #define GMAC1_CLKIN_NODE_FDT_PATH "/external-gmac1-clock"
1054
1055 #define GMAC1M0_MIIM_PINCTRL_PATH "/pinctrl/gmac1/gmac1m0-miim"
1056
rk3568_board_fdt_fixup_ethernet(const void * blob,int id)1057 static int rk3568_board_fdt_fixup_ethernet(const void *blob, int id)
1058 {
1059 int gmac_node, clkin_node, miim_node, len;
1060 const char *gmac_path, *clkin_path;
1061 void *fdt = (void *)gd->fdt_blob;
1062 u32 phandle, *pp;
1063
1064 /* get the gmac node and clockin node path at DTB */
1065 if (id == 1) {
1066 gmac_path = GMAC1_NODE_FDT_PATH;
1067 clkin_path = GMAC1_CLKIN_NODE_FDT_PATH;
1068 } else {
1069 gmac_path = GMAC0_NODE_FDT_PATH;
1070 clkin_path = GMAC0_CLKIN_NODE_FDT_PATH;
1071 }
1072
1073 gmac_node = fdt_path_offset(gd->fdt_blob, gmac_path);
1074 if (gmac_node < 0)
1075 return 0;
1076
1077 /* only fixes the RGMII clock input mode for gmac node */
1078 if (fdt_stringlist_search(fdt, gmac_node,
1079 "status", "disabled") < 0) {
1080 if (fdt_stringlist_search(fdt, gmac_node,
1081 "phy-mode", "rgmii") >= 0) {
1082 if (fdt_stringlist_search(fdt, gmac_node,
1083 "clock_in_out", "output") >= 0) {
1084 struct rk3568_grf *grf = (void *)GRF_BASE;
1085
1086 clkin_node = fdt_path_offset(fdt, clkin_path);
1087 if (clkin_node < 0)
1088 return 0;
1089 phandle = fdt_get_phandle(blob, clkin_node);
1090 if (!phandle)
1091 return 0;
1092 /*
1093 * before fixed:
1094 * assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>, <&cru CLK_MAC0_2TOP>;
1095 * after fixed:
1096 * assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>, <&gmac_clkin 0>;
1097 */
1098 pp = (u32 *)fdt_getprop(blob, gmac_node,
1099 "assigned-clock-parents",
1100 &len);
1101 if (!pp)
1102 return 0;
1103 if ((len / 8) >= 2) {
1104 pp[2] = cpu_to_fdt32(phandle);
1105 pp[3] = cpu_to_fdt32(0);
1106 }
1107
1108 /*
1109 * before fixed:
1110 * clock_in_out = "output";
1111 * after fixed:
1112 * clock_in_out = "input";
1113 */
1114
1115 do_fixup_by_path(fdt, gmac_path, "clock_in_out",
1116 "input", 6, 0);
1117 /*
1118 * set gmac_clkinout pin iomux for rgmii
1119 * input mode.
1120 */
1121 if (!id) {
1122 rk_clrsetreg(&grf->gpio2c_iomux_l,
1123 GPIO2C2_MASK,
1124 GPIO2C2_GMAC0_MCLKINOUT << GPIO2C2_SHIFT);
1125 } else {
1126 /*
1127 * get the miim pins phandle to check
1128 * m0 or m1 for gmac1_clkinout.
1129 */
1130 miim_node = fdt_path_offset(fdt,
1131 GMAC1M0_MIIM_PINCTRL_PATH);
1132 if (miim_node < 0)
1133 goto gmac1_mclkinoutm1;
1134 phandle = fdt_get_phandle(blob, miim_node);
1135 if (!phandle)
1136 goto gmac1_mclkinoutm1;
1137
1138 pp = (u32 *)fdt_getprop(blob, gmac_node, "pinctrl-0", &len);
1139 if (!pp)
1140 goto gmac1_mclkinoutm1;
1141 if (pp[0] == cpu_to_fdt32(phandle)) {
1142 rk_clrsetreg(&grf->gpio3c_iomux_l,
1143 GPIO3C0_MASK,
1144 GPIO3C0_GMAC1_MCLKINOUTM0 << GPIO3C0_SHIFT);
1145 return 0;
1146 }
1147 gmac1_mclkinoutm1:
1148 rk_clrsetreg(&grf->gpio4c_iomux_l,
1149 GPIO4C1_MASK,
1150 GPIO4C1_GMAC1_MCLKINOUTM1 << GPIO4C1_SHIFT);
1151 }
1152 }
1153 }
1154 }
1155
1156 return 0;
1157 }
1158
rk_board_fdt_fixup(const void * blob)1159 int rk_board_fdt_fixup(const void *blob)
1160 {
1161 int node, len;
1162 u32 *pp;
1163
1164 /* Don't go further if new variant */
1165 if (rockchip_get_cpu_version() > 0)
1166 return 0;
1167
1168 node = fdt_path_offset(blob, CRU_NODE_FDT_PATH);
1169 if (node < 0)
1170 return 0;
1171
1172 /*
1173 * fixup as:
1174 * rate[1] = <400000000>; // ACLK_RKVDEC_PRE
1175 * rate[2] = <400000000>; // CLK_RKVDEC_CORE
1176 * rate[5] = <400000000>; // PLL_CPLL
1177 */
1178 pp = (u32 *)fdt_getprop(blob, node, "assigned-clock-rates", &len);
1179 if (!pp)
1180 return 0;
1181 if ((len / 4) >= CRU_RATE_CNT_MIN) {
1182 pp[1] = cpu_to_fdt32(400000000);
1183 pp[2] = cpu_to_fdt32(400000000);
1184 pp[5] = cpu_to_fdt32(400000000);
1185 }
1186
1187 /*
1188 * fixup as:
1189 * parents[1] = <&cru PLL_CPLL>;
1190 * parents[2] = <&cru PLL_CPLL>;
1191 */
1192 pp = (u32 *)fdt_getprop(blob, node, "assigned-clock-parents", &len);
1193 if (!pp)
1194 return 0;
1195 if ((len / 8) >= CRU_PARENT_CNT_MIN) {
1196 pp[3] = cpu_to_fdt32(PLL_CPLL);
1197 pp[5] = cpu_to_fdt32(PLL_CPLL);
1198 }
1199
1200 node = fdt_path_offset(blob, RKVDEC_NODE_FDT_PATH);
1201 if (node < 0)
1202 return 0;
1203 pp = (u32 *)fdt_getprop(blob, node, "rockchip,normal-rates", &len);
1204 if (!pp)
1205 return 0;
1206
1207 if ((len / 4) >= RKVDEC_NORMAL_RATE_CNT_MIN) {
1208 pp[0] = cpu_to_fdt32(400000000);
1209 pp[1] = cpu_to_fdt32(0);
1210 pp[2] = cpu_to_fdt32(400000000);
1211 pp[3] = cpu_to_fdt32(400000000);
1212 pp[4] = cpu_to_fdt32(400000000);
1213 }
1214
1215 pp = (u32 *)fdt_getprop(blob, node, "assigned-clock-rates", &len);
1216 if (!pp)
1217 return 0;
1218
1219 if ((len / 4) >= RKVDEC_RATE_CNT_MIN) {
1220 pp[0] = cpu_to_fdt32(400000000);
1221 pp[1] = cpu_to_fdt32(400000000);
1222 pp[2] = cpu_to_fdt32(400000000);
1223 pp[3] = cpu_to_fdt32(400000000);
1224 }
1225
1226 rk3568_board_fdt_fixup_ethernet(blob, 0);
1227 rk3568_board_fdt_fixup_ethernet(blob, 1);
1228
1229 return 0;
1230 }
1231
1232 #ifdef CONFIG_ROCKCHIP_OTP
soc_id_init(void)1233 int soc_id_init(void)
1234 {
1235 struct udevice *dev;
1236 u8 val, spec;
1237 int ret;
1238
1239 ret = uclass_get_device_by_driver(UCLASS_MISC,
1240 DM_GET_DRIVER(rockchip_otp),
1241 &dev);
1242 if (ret) {
1243 printf("No OTP device, ret=%d\n", ret);
1244 return ret;
1245 }
1246
1247 ret = misc_read(dev, REMARK_OTP_SPEC_NUM_OFFSET, &val, 1);
1248 if (ret) {
1249 printf("Fail to read otp remark-spec, ret=%d\n", ret);
1250 return ret;
1251 }
1252 if (!val) {
1253 ret = misc_read(dev, OTP_SPEC_NUM_OFFSET, &val, 1);
1254 if (ret) {
1255 printf("Fail to read otp spec, ret=%d\n", ret);
1256 return ret;
1257 }
1258 }
1259
1260 spec = val & OTP_SPEC_NUM_MASK;
1261 printf("otp spec: %x\n", spec);
1262 if (spec == 0x1b) {
1263 printf("SoC: rk3566pro\n");
1264 board_soc_id_init(ROCKCHIP_SOC_RK3566PRO);
1265 }
1266
1267 return 0;
1268 }
1269 #endif
1270
1271 #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_ROCKCHIP_DMC_FSP)
rk_board_init(void)1272 int rk_board_init(void)
1273 {
1274 struct udevice *dev;
1275 u32 ret = 0;
1276
1277 ret = uclass_get_device_by_driver(UCLASS_DMC, DM_GET_DRIVER(dmc_fsp), &dev);
1278 if (ret) {
1279 printf("dmc_fsp failed, ret=%d\n", ret);
1280 return 0;
1281 }
1282
1283 return 0;
1284 }
1285 #endif
1286