1 /*
2 * Copyright (c) 2019 Rockchip Electronics Co., Ltd
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6 #include <common.h>
7 #include <ramdisk.h>
8 #include <asm/io.h>
9 #include <asm/arch/boot_mode.h>
10 #include <asm/arch/hardware.h>
11 #include <asm/arch/grf_rv1126.h>
12
13 DECLARE_GLOBAL_DATA_PTR;
14
15 #define FIREWALL_APB_BASE 0xffa60000
16 #define FW_DDR_CON_REG 0x80
17
18 #define USB_HOST_PRIORITY_REG 0xfe810008
19 #define USB_OTG_PRIORITY_REG 0xfe810088
20 #define DECOM_PRIORITY_REG 0xfe820088
21 #define DMA_PRIORITY_REG 0xfe820108
22 #define MCU_DM_PRIORITY_REG 0xfe820188
23 #define MCU_IM_PRIORITY_REG 0xfe820208
24 #define A7_PRIORITY_REG 0xfe830008
25 #define GMAC_PRIORITY_REG 0xfe840008
26 #define NPU_PRIORITY_REG 0xfe850008
27 #define EMMC_PRIORITY_REG 0xfe860008
28 #define NANDC_PRIORITY_REG 0xfe860088
29 #define SFC_PRIORITY_REG 0xfe860208
30 #define SDMMC_PRIORITY_REG 0xfe868008
31 #define SDIO_PRIORITY_REG 0xfe86c008
32 #define VEPU_RD0_PRIORITY_REG 0xfe870008
33 #define VEPU_RD1_PRIORITY_REG 0xfe870088
34 #define VEPU_WR_PRIORITY_REG 0xfe870108
35 #define ISPP_M0_PRIORITY_REG 0xfe880008
36 #define ISPP_M1_PRIORITY_REG 0xfe880088
37 #define ISP_PRIORITY_REG 0xfe890008
38 #define CIF_LITE_PRIORITY_REG 0xfe890088
39 #define CIF_PRIORITY_REG 0xfe890108
40 #define IEP_PRIORITY_REG 0xfe8a0008
41 #define RGA_RD_PRIORITY_REG 0xfe8a0088
42 #define RGA_WR_PRIORITY_REG 0xfe8a0108
43 #define VOP_PRIORITY_REG 0xfe8a0188
44 #define VDPU_PRIORITY_REG 0xfe8b0008
45 #define JPEG_PRIORITY_REG 0xfe8c0008
46 #define CRYPTO_PRIORITY_REG 0xfe8d0008
47 /* external priority register */
48 #define ISPP_M0_PRIORITY_EX_REG 0xfe880018
49 #define ISPP_M1_PRIORITY_EX_REG 0xfe880098
50 #define ISP_PRIORITY_EX_REG 0xfe890018
51 #define CIF_LT_PRIORITY_EX_REG 0xfe890098
52 #define CIF_PRIORITY_EX_REG 0xfe890118
53 #define VOP_PRIORITY_EX_REG 0xfe8a0198
54 #define VDPU_PRIORITY_EX_REG 0xfe8b0018
55
56 #define PMU_BASE_ADDR 0xff3e0000
57
58 #define PMU_BUS_IDLE_SFTCON(n) (0xc0 + (n) * 4)
59 #define PMU_BUS_IDLE_ACK (0xd0)
60 #define PMU_BUS_IDLE_ST (0xd8)
61 #define PMU_NOC_AUTO_CON0 (0xe0)
62 #define PMU_NOC_AUTO_CON1 (0xe4)
63 #define PMU_PWR_DWN_ST (0x108)
64 #define PMU_PWR_GATE_SFTCON (0x110)
65
66 #define PMU_BUS_IDLE_NPU BIT(18)
67 #define PMU_BUS_IDLE_VEPU BIT(9)
68
69 #define CRU_BASE 0xFF490000
70 #define CRU_CLKSEL_CON02 0x108
71 #define CRU_CLKSEL_CON03 0x10c
72 #define CRU_CLKSEL_CON27 0x16c
73 #define CRU_CLKSEL_CON31 0x17c
74 #define CRU_CLKSEL_CON33 0x184
75 #define CRU_CLKSEL_CON40 0x1a0
76 #define CRU_CLKSEL_CON49 0x1c4
77 #define CRU_CLKSEL_CON50 0x1c8
78 #define CRU_CLKSEL_CON51 0x1cc
79 #define CRU_CLKSEL_CON54 0x1d8
80 #define CRU_CLKSEL_CON61 0x1f4
81 #define CRU_CLKSEL_CON63 0x1fc
82 #define CRU_CLKSEL_CON65 0x204
83 #define CRU_CLKSEL_CON67 0x20c
84 #define CRU_CLKSEL_CON68 0x210
85 #define CRU_CLKSEL_CON69 0x214
86 #define CRU_SOFTRST_CON02 0x308
87 #define CRU_SOFTRST_CON10 0x328
88
89 #define CRU_PMU_BASE 0xFF480000
90 #define CRU_PMU_GPLL_CON0 0x10
91 #define CRU_PMU_GPLL_CON1 0x14
92
93 #define GRF_BASE 0xFE000000
94 #define GRF_SOC_CON2 0x008
95 #define PMUGRF_BASE 0xFE020000
96 #define SGRF_BASE 0xFE0A0000
97 #define SGRF_CON_SCR1_BOOT_ADDR 0x0b0
98 #define SGRF_SOC_CON3 0x00c
99 #define CRU_SOFTRST_CON11 0xFF49032C
100 #define PMUGRF_SOC_CON1 0xFE020104
101 #define PMUGRF_RSTFUNC_STATUS 0xFE020230
102 #define PMUGRF_RSTFUNC_CLR 0xFE020234
103 #define WDT_RESET_SRC BIT(1)
104 #define WDT_RESET_SRC_CLR BIT(1)
105 #define GRF_IOFUNC_CON3 0xFF01026C
106 #define GRF1_GPIO0D_P 0xFE010104
107 #define OTP_NS_BASE 0xFF5C0000
108 #define OTP_S_BASE 0xFF5D0000
109 #define OTP_NVM_TRWH 0x28
110
111 #define PMU_GRF_BASE 0xFE020000
112 #define PMUGRF_GPIO0B_IOMUX_H 0xc
113
114 enum {
115 GPIO1A7_SHIFT = 12,
116 GPIO1A7_MASK = GENMASK(14, 12),
117 GPIO1A7_GPIO = 0,
118 GPIO1A7_SDMMC0_D3,
119 GPIO1A7_UART3_TX_M1,
120 GPIO1A7_A7_JTAG_TMS_M0,
121 GPIO1A7_RISCV_JTAG_TMS,
122
123 GPIO1A6_SHIFT = 8,
124 GPIO1A6_MASK = GENMASK(10, 8),
125 GPIO1A6_GPIO = 0,
126 GPIO1A6_SDMMC0_D2,
127 GPIO1A6_UART3_RX_M1,
128 GPIO1A6_A7_JTAG_TCK_M0,
129 GPIO1A6_RISCV_JTAG_TCK,
130
131 GPIO1A5_SHIFT = 4,
132 GPIO1A5_MASK = GENMASK(6, 4),
133 GPIO1A5_GPIO = 0,
134 GPIO1A5_SDMMC0_D1,
135 GPIO1A5_TEST_CLK0_OUT,
136 GPIO1A5_UART2_TX_M0,
137 GPIO1A5_RISCV_JTAG_TRSTN,
138
139 GPIO1A4_SHIFT = 0,
140 GPIO1A4_MASK = GENMASK(2, 0),
141 GPIO1A4_GPIO = 0,
142 GPIO1A4_SDMMC0_D0,
143 GPIO1A4_TEST_CLK1_OUT,
144 GPIO1A4_UART2_RX_M0,
145
146 GPIO1C3_SHIFT = 12,
147 GPIO1C3_MASK = GENMASK(14, 12),
148 GPIO1C3_GPIO = 0,
149 GPIO1C3_UART0_TX,
150
151 GPIO1C2_SHIFT = 8,
152 GPIO1C2_MASK = GENMASK(10, 8),
153 GPIO1C2_GPIO = 0,
154 GPIO1C2_UART0_RX,
155
156 GPIO1D5_SHIFT = 4,
157 GPIO1D5_MASK = GENMASK(6, 4),
158 GPIO1D5_GPIO = 0,
159 GPIO1D5_SPI0_CS1N_M1,
160 GPIO1D5_I2S1_MCLK_M1,
161 GPIO1D5_UART4_TX_M2,
162
163 GPIO1D4_SHIFT = 0,
164 GPIO1D4_MASK = GENMASK(2, 0),
165 GPIO1D4_GPIO = 0,
166 GPIO1D4_RESERVED0,
167 GPIO1D4_RESERVED1,
168 GPIO1D4_UART4_RX_M2,
169
170 GPIO1D1_SHIFT = 4,
171 GPIO1D1_MASK = GENMASK(6, 4),
172 GPIO1D1_GPIO = 0,
173 GPIO1D1_RESERVED0,
174 GPIO1D1_SDMMC1_PWR,
175 GPIO1D1_RESERVED1,
176 GPIO1D1_I2C5_SDA_M2,
177 GPIO1D1_UART1_RX_M1,
178
179 GPIO1D0_SHIFT = 0,
180 GPIO1D0_MASK = GENMASK(2, 0),
181 GPIO1D0_GPIO = 0,
182 GPIO1D0_I2S2_MCLK_M0,
183 GPIO1D0_SDMMC1_DET,
184 GPIO1D0_SPI1_CS1N_M1,
185 GPIO1D0_I2C5_SCL_M2,
186 GPIO1D0_UART1_TX_M1,
187
188 GPIO2A7_SHIFT = 12,
189 GPIO2A7_MASK = GENMASK(14, 12),
190 GPIO2A7_GPIO = 0,
191 GPIO2A7_LCDC_D3,
192 GPIO2A7_I2S2_SDO_M1,
193 GPIO2A7_RESERVED,
194 GPIO2A7_UART4_RX_M1,
195 GPIO2A7_PWM4_M1,
196 GPIO2A7_SPI0_CS0N_M2,
197
198 GPIO2A6_SHIFT = 8,
199 GPIO2A6_MASK = GENMASK(10, 8),
200 GPIO2A6_GPIO = 0,
201 GPIO2A6_LCDC_D2,
202 GPIO2A6_RGMII_COL_M1,
203 GPIO2A6_CIF_D2_M1,
204 GPIO2A6_UART4_TX_M1,
205 GPIO2A6_PWM5_M1,
206
207 GPIO2A1_SHIFT = 4,
208 GPIO2A1_MASK = GENMASK(6, 4),
209 GPIO2A1_GPIO = 0,
210 GPIO2A1_SPI0_CLK_M1,
211 GPIO2A1_I2S1_SDO_M1,
212 GPIO2A1_UART5_RX_M2,
213
214 GPIO2A0_SHIFT = 0,
215 GPIO2A0_MASK = GENMASK(2, 0),
216 GPIO2A0_GPIO = 0,
217 GPIO2A0_SPI0_CS0N_M1,
218 GPIO2A0_I2S1_SDI_M1,
219 GPIO2A0_UART5_TX_M2,
220
221 GPIO2B1_SHIFT = 4,
222 GPIO2B1_MASK = GENMASK(6, 4),
223 GPIO2B1_GPIO = 0,
224 GPIO2B1_LCDC_D5,
225 GPIO2B1_I2S2_SCLK_M1,
226 GPIO2B1_RESERVED,
227 GPIO2B1_UART5_RX_M1,
228 GPIO2B1_PWM2_M1,
229 GPIO2B1_SPI0_MISO_M2,
230
231 GPIO2B0_SHIFT = 0,
232 GPIO2B0_MASK = GENMASK(2, 0),
233 GPIO2B0_GPIO = 0,
234 GPIO2B0_LCDC_D4,
235 GPIO2B0_I2S2_SDI_M1,
236 GPIO2B0_RESERVED,
237 GPIO2B0_UART5_TX_M1,
238 GPIO2B0_PWM3_IR_M1,
239 GPIO2B0_SPI0_MOSI_M2,
240
241 GPIO3A7_SHIFT = 12,
242 GPIO3A7_MASK = GENMASK(14, 12),
243 GPIO3A7_GPIO = 0,
244 GPIO3A7_CIF_D3_M0,
245 GPIO3A7_RGMII_RXD2_M0,
246 GPIO3A7_I2S0_SDI0_M1,
247 GPIO3A7_UART5_RX_M0,
248 GPIO3A7_CAN_TXD_M1,
249 GPIO3A7_PWM11_IR_M0,
250
251 GPIO3A6_SHIFT = 8,
252 GPIO3A6_MASK = GENMASK(10, 8),
253 GPIO3A6_GPIO = 0,
254 GPIO3A6_CIF_D2_M0,
255 GPIO3A6_RGMII_COL_M0,
256 GPIO3A6_I2S0_SDO0_M1,
257 GPIO3A6_UART5_TX_M0,
258 GPIO3A6_CAN_RXD_M1,
259 GPIO3A6_PWM10_M0,
260
261 GPIO3A5_SHIFT = 4,
262 GPIO3A5_MASK = GENMASK(6, 4),
263 GPIO3A5_GPIO = 0,
264 GPIO3A5_CIF_D1_M0,
265 GPIO3A5_RGMII_CRS_M0,
266 GPIO3A5_I2S0_LRCK_TX_M1,
267 GPIO3A5_UART4_RX_M0,
268 GPIO3A5_I2C3_SDA_M0,
269 GPIO3A5_PWM9_M0,
270
271 GPIO3A4_SHIFT = 0,
272 GPIO3A4_MASK = GENMASK(2, 0),
273 GPIO3A4_GPIO = 0,
274 GPIO3A4_CIF_D0_M0,
275 GPIO3A4_RESERVED,
276 GPIO3A4_I2S0_SCLK_TX_M1,
277 GPIO3A4_UART4_TX_M0,
278 GPIO3A4_I2C3_SCL_M0,
279 GPIO3A4_PWM8_M0,
280
281 GPIO3A3_SHIFT = 12,
282 GPIO3A3_MASK = GENMASK(14, 12),
283 GPIO3A3_GPIO = 0,
284 GPIO3A3_UART2_RX_M1,
285 GPIO3A3_A7_JTAG_TMS_M1,
286
287 GPIO3A2_SHIFT = 8,
288 GPIO3A2_MASK = GENMASK(10, 8),
289 GPIO3A2_GPIO = 0,
290 GPIO3A2_UART2_TX_M1,
291 GPIO3A2_A7_JTAG_TCK_M1,
292
293 GPIO3A1_SHIFT = 4,
294 GPIO3A1_MASK = GENMASK(6, 4),
295 GPIO3A1_GPIO = 0,
296 GPIO3A1_RESERVED0,
297 GPIO3A1_RESERVED1,
298 GPIO3A1_CAN_TXD_M0,
299 GPIO3A1_UART3_RX_M2,
300 GPIO3A1_PWM6_M1,
301 GPIO3A1_RESERVED2,
302 GPIO3A1_I2C4_SDA_M0,
303
304 GPIO3A0_SHIFT = 0,
305 GPIO3A0_MASK = GENMASK(2, 0),
306 GPIO3A0_GPIO = 0,
307 GPIO3A0_RESERVED0,
308 GPIO3A0_RESERVED1,
309 GPIO3A0_CAN_RXD_M0,
310 GPIO3A0_UART3_TX_M2,
311 GPIO3A0_PWM7_IR_M1,
312 GPIO3A0_SPI1_CS1N_M2,
313 GPIO3A0_I2C4_SCL_M0,
314
315 GPIO3C7_SHIFT = 12,
316 GPIO3C7_MASK = GENMASK(14, 12),
317 GPIO3C7_GPIO = 0,
318 GPIO3C7_CIF_HSYNC_M0,
319 GPIO3C7_RGMII_RXCLK_M0,
320 GPIO3C7_RESERVED,
321 GPIO3C7_UART3_RX_M0,
322
323 GPIO3C6_SHIFT = 8,
324 GPIO3C6_MASK = GENMASK(10, 0),
325 GPIO3C6_GPIO = 0,
326 GPIO3C6_CIF_CLKOUT_M0,
327 GPIO3C6_RGMII_TXCLK_M0,
328 GPIO3C6_RESERVED,
329 GPIO3C6_UART3_TX_M0,
330
331 UART2_IO_SEL_SHIFT = 8,
332 UART2_IO_SEL_MASK = GENMASK(8, 8),
333 UART2_IO_SEL_M0 = 0,
334 UART2_IO_SEL_M1,
335
336 UART3_IO_SEL_SHIFT = 10,
337 UART3_IO_SEL_MASK = GENMASK(11, 10),
338 UART3_IO_SEL_M0 = 0,
339 UART3_IO_SEL_M1,
340 UART3_IO_SEL_M2,
341
342 UART4_IO_SEL_SHIFT = 12,
343 UART4_IO_SEL_MASK = GENMASK(13, 12),
344 UART4_IO_SEL_M0 = 0,
345 UART4_IO_SEL_M1,
346 UART4_IO_SEL_M2,
347
348 UART5_IO_SEL_SHIFT = 14,
349 UART5_IO_SEL_MASK = GENMASK(15, 14),
350 UART5_IO_SEL_M0 = 0,
351 UART5_IO_SEL_M1,
352 UART5_IO_SEL_M2,
353 };
354
355 enum {
356 UART1_IO_SEL_SHIFT = 2,
357 UART1_IO_SEL_MASK = GENMASK(2, 2),
358 UART1_IO_SEL_M0 = 0,
359 UART1_IO_SEL_M1,
360
361 GPIO0B7_SHIFT = 12,
362 GPIO0B7_MASK = GENMASK(14, 12),
363 GPIO0B7_GPIO = 0,
364 GPIO0B7_RESERVED,
365 GPIO0B7_UART1_RX_M0,
366 GPIO0B7_PWM1_M0,
367
368 GPIO0B6_SHIFT = 8,
369 GPIO0B6_MASK = GENMASK(10, 8),
370 GPIO0B6_GPIO = 0,
371 GPIO0B6_RESERVED,
372 GPIO0B6_UART1_TX_M0,
373 GPIO0B6_PWM0_M0,
374 };
375
board_debug_uart_init(void)376 void board_debug_uart_init(void)
377 {
378 #if defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff560000)
379 static struct rv1126_grf * const grf = (void *)GRF_BASE;
380
381 /* UART0 Switch iomux */
382 rk_clrsetreg(&grf->gpio1c_iomux_l,
383 GPIO1C3_MASK | GPIO1C2_MASK,
384 GPIO1C3_UART0_TX << GPIO1C3_SHIFT |
385 GPIO1C2_UART0_RX << GPIO1C2_SHIFT);
386
387 #elif defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff410000)
388 static struct rv1126_pmugrf * const pmugrf = (void *)PMUGRF_BASE;
389 static struct rv1126_grf * const grf = (void *)GRF_BASE;
390 #if defined(CONFIG_ROCKCHIP_UART_MUX_SEL_M) && \
391 (CONFIG_ROCKCHIP_UART_MUX_SEL_M == 0)
392 /* UART1 M0 */
393 rk_clrsetreg(&pmugrf->soc_con[6], UART1_IO_SEL_MASK,
394 UART1_IO_SEL_M0 << UART1_IO_SEL_SHIFT);
395
396 /* Switch iomux */
397 rk_clrsetreg(&pmugrf->gpio0b_iomux_h,
398 GPIO0B7_MASK | GPIO0B6_MASK,
399 GPIO0B7_UART1_RX_M0 << GPIO0B7_SHIFT |
400 GPIO0B6_UART1_TX_M0 << GPIO0B6_SHIFT);
401 #else
402 /* UART1 M1 */
403 rk_clrsetreg(&pmugrf->soc_con[6], UART1_IO_SEL_MASK,
404 UART1_IO_SEL_M1 << UART1_IO_SEL_SHIFT);
405
406 /* Switch iomux */
407 rk_clrsetreg(&grf->gpio1d_iomux_l,
408 GPIO1D1_MASK | GPIO1D0_MASK,
409 GPIO1D1_UART1_RX_M1 << GPIO1D1_SHIFT |
410 GPIO1D0_UART1_TX_M1 << GPIO1D0_SHIFT);
411 #endif
412
413 #elif defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff570000)
414 static struct rv1126_grf * const grf = (void *)GRF_BASE;
415 #if defined(CONFIG_ROCKCHIP_UART_MUX_SEL_M) && \
416 (CONFIG_ROCKCHIP_UART_MUX_SEL_M == 0)
417 /* Enable early UART2 channel m0 on the rv1126 */
418 rk_clrsetreg(&grf->iofunc_con2, UART2_IO_SEL_MASK,
419 UART2_IO_SEL_M0 << UART2_IO_SEL_SHIFT);
420
421 /* Switch iomux */
422 rk_clrsetreg(&grf->gpio1a_iomux_h,
423 GPIO1A5_MASK | GPIO1A4_MASK,
424 GPIO1A5_UART2_TX_M0 << GPIO1A5_SHIFT |
425 GPIO1A4_UART2_RX_M0 << GPIO1A4_SHIFT);
426 #else
427 /* Enable early UART2 channel m1 on the rv1126 */
428 rk_clrsetreg(&grf->iofunc_con2, UART2_IO_SEL_MASK,
429 UART2_IO_SEL_M1 << UART2_IO_SEL_SHIFT);
430
431 /* Switch iomux */
432 rk_clrsetreg(&grf->gpio3a_iomux_l,
433 GPIO3A3_MASK | GPIO3A2_MASK,
434 GPIO3A3_UART2_RX_M1 << GPIO3A3_SHIFT |
435 GPIO3A2_UART2_TX_M1 << GPIO3A2_SHIFT);
436 #endif
437
438 #elif defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff580000)
439 static struct rv1126_grf * const grf = (void *)GRF_BASE;
440 #if defined(CONFIG_ROCKCHIP_UART_MUX_SEL_M) && \
441 (CONFIG_ROCKCHIP_UART_MUX_SEL_M == 0)
442 /* UART3 m0*/
443 rk_clrsetreg(&grf->iofunc_con2, UART3_IO_SEL_MASK,
444 UART3_IO_SEL_M0 << UART3_IO_SEL_SHIFT);
445
446 /* Switch iomux */
447 rk_clrsetreg(&grf->gpio3c_iomux_h,
448 GPIO3C7_MASK | GPIO3C6_MASK,
449 GPIO3C7_UART3_RX_M0 << GPIO3C7_SHIFT |
450 GPIO3C6_UART3_TX_M0 << GPIO3C6_SHIFT);
451 #elif defined(CONFIG_ROCKCHIP_UART_MUX_SEL_M) && \
452 (CONFIG_ROCKCHIP_UART_MUX_SEL_M == 1)
453 /* UART3 m1*/
454 rk_clrsetreg(&grf->iofunc_con2, UART3_IO_SEL_MASK,
455 UART3_IO_SEL_M1 << UART3_IO_SEL_SHIFT);
456
457 /* Switch iomux */
458 rk_clrsetreg(&grf->gpio1a_iomux_h,
459 GPIO1A7_MASK | GPIO1A6_MASK,
460 GPIO1A7_UART3_TX_M1 << GPIO1A7_SHIFT |
461 GPIO1A6_UART3_RX_M1 << GPIO1A6_SHIFT);
462 #else
463 /* UART3 m2*/
464 rk_clrsetreg(&grf->iofunc_con2, UART3_IO_SEL_MASK,
465 UART3_IO_SEL_M2 << UART3_IO_SEL_SHIFT);
466
467 /* Switch iomux */
468 rk_clrsetreg(&grf->gpio3a_iomux_l,
469 GPIO3A1_MASK | GPIO3A0_MASK,
470 GPIO3A1_UART3_RX_M2 << GPIO3A1_SHIFT |
471 GPIO3A0_UART3_TX_M2 << GPIO3A0_SHIFT);
472 #endif
473
474 #elif defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff590000)
475 static struct rv1126_grf * const grf = (void *)GRF_BASE;
476 #if defined(CONFIG_ROCKCHIP_UART_MUX_SEL_M) && \
477 (CONFIG_ROCKCHIP_UART_MUX_SEL_M == 0)
478 /* UART4 m0*/
479 rk_clrsetreg(&grf->iofunc_con2, UART4_IO_SEL_MASK,
480 UART4_IO_SEL_M0 << UART4_IO_SEL_SHIFT);
481
482 /* Switch iomux */
483 rk_clrsetreg(&grf->gpio3a_iomux_h,
484 GPIO3A5_MASK | GPIO3A4_MASK,
485 GPIO3A5_UART4_RX_M0 << GPIO3A5_SHIFT |
486 GPIO3A4_UART4_TX_M0 << GPIO3A4_SHIFT);
487 #elif defined(CONFIG_ROCKCHIP_UART_MUX_SEL_M) && \
488 (CONFIG_ROCKCHIP_UART_MUX_SEL_M == 1)
489 /* UART4 m1*/
490 rk_clrsetreg(&grf->iofunc_con2, UART4_IO_SEL_MASK,
491 UART4_IO_SEL_M1 << UART4_IO_SEL_SHIFT);
492
493 /* Switch iomux */
494 rk_clrsetreg(&grf->gpio2a_iomux_h,
495 GPIO2A7_MASK | GPIO2A6_MASK,
496 GPIO2A7_UART4_RX_M1 << GPIO2A7_SHIFT |
497 GPIO2A6_UART4_TX_M1 << GPIO2A6_SHIFT);
498 #else
499 /* UART4 m2*/
500 rk_clrsetreg(&grf->iofunc_con2, UART4_IO_SEL_MASK,
501 UART4_IO_SEL_M2 << UART4_IO_SEL_SHIFT);
502
503 /* Switch iomux */
504 rk_clrsetreg(&grf->gpio1d_iomux_h,
505 GPIO1D5_MASK | GPIO1D4_MASK,
506 GPIO1D5_UART4_TX_M2 << GPIO1D5_SHIFT |
507 GPIO1D4_UART4_RX_M2 << GPIO1D4_SHIFT);
508 #endif
509
510 #elif defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff5a0000)
511 static struct rv1126_grf * const grf = (void *)GRF_BASE;
512 #if defined(CONFIG_ROCKCHIP_UART_MUX_SEL_M) && \
513 (CONFIG_ROCKCHIP_UART_MUX_SEL_M == 0)
514 /* UART5 m0*/
515 rk_clrsetreg(&grf->iofunc_con2, UART5_IO_SEL_MASK,
516 UART5_IO_SEL_M0 << UART5_IO_SEL_SHIFT);
517
518 /* Switch iomux */
519 rk_clrsetreg(&grf->gpio3a_iomux_h,
520 GPIO3A7_MASK | GPIO3A6_MASK,
521 GPIO3A7_UART5_RX_M0 << GPIO3A7_SHIFT |
522 GPIO3A6_UART5_TX_M0 << GPIO3A6_SHIFT);
523 #elif defined(CONFIG_ROCKCHIP_UART_MUX_SEL_M) && \
524 (CONFIG_ROCKCHIP_UART_MUX_SEL_M == 1)
525 /* UART5 m1*/
526 rk_clrsetreg(&grf->iofunc_con2, UART5_IO_SEL_MASK,
527 UART5_IO_SEL_M1 << UART5_IO_SEL_SHIFT);
528
529 /* Switch iomux */
530 rk_clrsetreg(&grf->gpio2b_iomux_l,
531 GPIO2B1_MASK | GPIO2B0_MASK,
532 GPIO2B1_UART5_RX_M1 << GPIO2B1_SHIFT |
533 GPIO2B0_UART5_TX_M1 << GPIO2B0_SHIFT);
534 #else
535 /* UART5 m2*/
536 rk_clrsetreg(&grf->iofunc_con2, UART5_IO_SEL_MASK,
537 UART5_IO_SEL_M2 << UART5_IO_SEL_SHIFT);
538
539 /* Switch iomux */
540 rk_clrsetreg(&grf->gpio2a_iomux_l,
541 GPIO2A1_MASK | GPIO2A0_MASK,
542 GPIO2A1_UART5_RX_M2 << GPIO2A1_SHIFT |
543 GPIO2A0_UART5_TX_M2 << GPIO2A0_SHIFT);
544 #endif
545 #endif /* CONFIG_DEBUG_UART_BASE && CONFIG_DEBUG_UART_BASE == ... */
546 }
547
board_set_iomux(enum if_type if_type,int devnum,int routing)548 void board_set_iomux(enum if_type if_type, int devnum, int routing)
549 {
550 static struct rv1126_grf * const grf = (void *)GRF_BASE;
551
552 switch (if_type) {
553 case IF_TYPE_MMC:
554 writel(0x0F0F0303, &grf->gpio0d_iomux_h);
555 writel(0xFFFF3333, &grf->gpio1a_iomux_l);
556 break;
557 case IF_TYPE_MTD:
558 if (devnum == 0) {
559 writel(0xFFFF1111, &grf->gpio0c_iomux_h);
560 writel(0xFFFF1111, &grf->gpio0d_iomux_l);
561 writel(0xF0FF1011, &grf->gpio0d_iomux_h);
562 writel(0xFFFF1111, &grf->gpio1a_iomux_l);
563 } else {
564 writel(0x0F0F0303, &grf->gpio0d_iomux_h);
565 writel(0xFFFF3333, &grf->gpio1a_iomux_l);
566 }
567 break;
568 default:
569 printf("Bootdev 0x%x is not support\n", if_type);
570 }
571 }
572
573 #ifndef CONFIG_TPL_BUILD
arch_cpu_init(void)574 int arch_cpu_init(void)
575 {
576 /*
577 * CONFIG_DM_RAMDISK: for ramboot that without SPL.
578 */
579 #if defined(CONFIG_SPL_BUILD) || defined(CONFIG_DM_RAMDISK)
580 u32 pd_st, idle_st;
581 int delay;
582
583 /*
584 * Don't rely on CONFIG_DM_RAMDISK since it can be a default
585 * configuration after disk/part_rkram.c was introduced.
586 *
587 * This is compatible code.
588 */
589 #ifndef CONFIG_SPL_BUILD
590 if (!dm_ramdisk_is_enabled())
591 return 0;
592 #endif
593
594 /* write BOOT_WATCHDOG to boot mode register, if reset by wdt */
595 if (readl(PMUGRF_RSTFUNC_STATUS) & WDT_RESET_SRC) {
596 writel(BOOT_WATCHDOG, CONFIG_ROCKCHIP_BOOT_MODE_REG);
597 /* clear flag for reset by wdt trigger */
598 writel(WDT_RESET_SRC_CLR, PMUGRF_RSTFUNC_CLR);
599 }
600
601 #ifdef CONFIG_SPL_BUILD
602 /* set otp tRWH to 0x9 for stable read */
603 writel(0x9, OTP_NS_BASE + OTP_NVM_TRWH);
604 writel(0x9, OTP_S_BASE + OTP_NVM_TRWH);
605
606 /*
607 * Just set region 0 to unsecure.
608 * (Note: only secure-world can access this register)
609 */
610 writel(0, FIREWALL_APB_BASE + FW_DDR_CON_REG);
611 #endif
612
613 /* disable force jtag mux route to both group0 and group1 */
614 writel(0x00300000, GRF_IOFUNC_CON3);
615
616 /* make npu aclk and sclk less then 300MHz when reset */
617 writel(0x00ff0055, CRU_BASE + CRU_CLKSEL_CON65);
618 writel(0x00ff0055, CRU_BASE + CRU_CLKSEL_CON67);
619
620 /*
621 * When perform idle operation, corresponding clock can
622 * be opened or gated automatically.
623 */
624 writel(0xffffffff, PMU_BASE_ADDR + PMU_NOC_AUTO_CON0);
625 writel(0xffffffff, PMU_BASE_ADDR + PMU_NOC_AUTO_CON1);
626
627 #ifdef CONFIG_SPL_KERNEL_BOOT
628 /* Adjust the parameters of GPLL's VCO for reduce power*/
629 writel(0x00030000, CRU_PMU_BASE);
630 writel(0xffff1063, CRU_PMU_BASE + CRU_PMU_GPLL_CON0);
631 writel(0xffff1442, CRU_PMU_BASE + CRU_PMU_GPLL_CON1);
632 writel(0x00030001, CRU_PMU_BASE);
633
634 /* mux clocks to none-cpll */
635 writel(0x00ff0003, CRU_BASE + CRU_CLKSEL_CON02);
636 writel(0x00ff0005, CRU_BASE + CRU_CLKSEL_CON03);
637 writel(0xffff8383, CRU_BASE + CRU_CLKSEL_CON27);
638 writel(0x00ff0083, CRU_BASE + CRU_CLKSEL_CON31);
639 writel(0x00ff0083, CRU_BASE + CRU_CLKSEL_CON33);
640 writel(0xffff4385, CRU_BASE + CRU_CLKSEL_CON40);
641 writel(0x00ff0043, CRU_BASE + CRU_CLKSEL_CON49);
642 writel(0x00ff0003, CRU_BASE + CRU_CLKSEL_CON50);
643 writel(0x00ff0003, CRU_BASE + CRU_CLKSEL_CON51);
644 writel(0xff000300, CRU_BASE + CRU_CLKSEL_CON54);
645 writel(0xff008900, CRU_BASE + CRU_CLKSEL_CON61);
646 writel(0x00ff0089, CRU_BASE + CRU_CLKSEL_CON63);
647 writel(0x00ff0045, CRU_BASE + CRU_CLKSEL_CON68);
648 writel(0x00ff0043, CRU_BASE + CRU_CLKSEL_CON69);
649
650 #endif
651 /* enable all pd */
652 writel(0xffff0000, PMU_BASE_ADDR + PMU_PWR_GATE_SFTCON);
653 delay = 1000;
654 do {
655 udelay(1);
656 delay--;
657 } while (delay && readl(PMU_BASE_ADDR + PMU_PWR_DWN_ST));
658
659 /* release all idle request */
660 writel(0xffff0000, PMU_BASE_ADDR + PMU_BUS_IDLE_SFTCON(0));
661 writel(0xffff0000, PMU_BASE_ADDR + PMU_BUS_IDLE_SFTCON(1));
662
663 delay = 1000;
664 /* wait ack status */
665 do {
666 udelay(1);
667 delay--;
668 } while (delay && readl(PMU_BASE_ADDR + PMU_BUS_IDLE_ACK));
669
670 delay = 1000;
671 /* wait idle status */
672 do {
673 udelay(1);
674 delay--;
675 } while (delay && readl(PMU_BASE_ADDR + PMU_BUS_IDLE_ST));
676
677 pd_st = readl(PMU_BASE_ADDR + PMU_PWR_DWN_ST);
678 idle_st = readl(PMU_BASE_ADDR + PMU_BUS_IDLE_ST);
679
680 if (pd_st || idle_st) {
681 printf("PMU_PWR_DOWN_ST: 0x%08x\n", pd_st);
682 printf("PMU_BUS_IDLE_ST: 0x%08x\n", idle_st);
683
684 if (idle_st & PMU_BUS_IDLE_NPU)
685 printf("Failed to enable PD_NPU, please check VDD_NPU is supplied\n");
686
687 if (idle_st & PMU_BUS_IDLE_VEPU)
688 printf("Failed to enable PD_VEPU, please check VDD_VEPU is supplied\n");
689
690 hang();
691 }
692
693 writel(0x303, USB_HOST_PRIORITY_REG);
694 writel(0x303, USB_OTG_PRIORITY_REG);
695 writel(0x101, DECOM_PRIORITY_REG);
696 writel(0x303, DMA_PRIORITY_REG);
697 writel(0x101, MCU_DM_PRIORITY_REG);
698 writel(0x101, MCU_IM_PRIORITY_REG);
699 writel(0x101, A7_PRIORITY_REG);
700 writel(0x303, GMAC_PRIORITY_REG);
701 writel(0x101, NPU_PRIORITY_REG);
702 writel(0x303, EMMC_PRIORITY_REG);
703 writel(0x303, NANDC_PRIORITY_REG);
704 writel(0x303, SFC_PRIORITY_REG);
705 writel(0x303, SDMMC_PRIORITY_REG);
706 writel(0x303, SDIO_PRIORITY_REG);
707 writel(0x101, VEPU_RD0_PRIORITY_REG);
708 writel(0x101, VEPU_RD1_PRIORITY_REG);
709 writel(0x101, VEPU_WR_PRIORITY_REG);
710 writel(0x101, ISPP_M0_PRIORITY_REG);
711 writel(0x101, ISPP_M1_PRIORITY_REG);
712 writel(0x101, ISP_PRIORITY_REG);
713 writel(0x202, CIF_LITE_PRIORITY_REG);
714 writel(0x202, CIF_PRIORITY_REG);
715 writel(0x101, IEP_PRIORITY_REG);
716 writel(0x101, RGA_RD_PRIORITY_REG);
717 writel(0x101, RGA_WR_PRIORITY_REG);
718 writel(0x202, VOP_PRIORITY_REG);
719 writel(0x101, VDPU_PRIORITY_REG);
720 writel(0x101, JPEG_PRIORITY_REG);
721 writel(0x101, CRYPTO_PRIORITY_REG);
722 /* enable dynamic priority */
723 writel(0x1, ISP_PRIORITY_EX_REG);
724
725 /*
726 * Init the i2c0 iomux and use it to control electronic voltmeter
727 * to detect voltage.
728 */
729 #if defined(CONFIG_SPL_KERNEL_BOOT) && defined(CONFIG_SPL_DM_FUEL_GAUGE)
730 writel(0x00770011, PMU_GRF_BASE + PMUGRF_GPIO0B_IOMUX_H);
731 #endif
732
733 #elif defined(CONFIG_SUPPORT_USBPLUG)
734 /* Just set region 0 to unsecure */
735 writel(0, FIREWALL_APB_BASE + FW_DDR_CON_REG);
736
737 /* reset usbphy_otg usbphypor_otg */
738 writel(((0x1 << 6 | (1 << 8)) << 16) | (0x1 << 6) | (1 << 8), CRU_SOFTRST_CON11);
739 udelay(50);
740 writel(((0x1 << 6 | (1 << 8)) << 16) | (0), CRU_SOFTRST_CON11);
741
742 /* hold pmugrf's io reset */
743 writel(0x1 << 7 | 1 << 23, PMUGRF_SOC_CON1);
744
745 #else /* U-Boot */
746 /* uboot: config iomux for sd boot upgrade firmware */
747 #if defined(CONFIG_ROCKCHIP_SFC_IOMUX)
748 static struct rv1126_grf * const grf = (void *)GRF_BASE;
749
750 writel(0x0F0F0303, &grf->gpio0d_iomux_h);
751 writel(0xFFFF3333, &grf->gpio1a_iomux_l);
752 #elif defined(CONFIG_ROCKCHIP_EMMC_IOMUX)
753 static struct rv1126_grf * const grf = (void *)GRF_BASE;
754
755 writel(0xFFFF2222, &grf->gpio0c_iomux_h);
756 writel(0xFFFF2222, &grf->gpio0d_iomux_l);
757 writel(0xF0F02020, &grf->gpio0d_iomux_h);
758 #elif defined(CONFIG_ROCKCHIP_NAND_IOMUX)
759 static struct rv1126_grf * const grf = (void *)GRF_BASE;
760
761 writel(0xFFFF1111, &grf->gpio0c_iomux_h);
762 writel(0xFFFF1111, &grf->gpio0d_iomux_l);
763 writel(0xF0FF1011, &grf->gpio0d_iomux_h);
764 writel(0xFFFF1111, &grf->gpio1a_iomux_l);
765 #endif
766
767 #endif
768 #if defined(CONFIG_ROCKCHIP_SFC)
769 /* GPIO0_D6 pull down in default, pull up it for SPI Flash */
770 writel(((0x3 << 12) << 16) | (0x1 << 12), GRF1_GPIO0D_P);
771 #endif
772 /* reset sdmmc0 to prevent power leak */
773 writel(0x00100010, CRU_BASE + CRU_SOFTRST_CON10);
774 udelay(1);
775 writel(0x00100000, CRU_BASE + CRU_SOFTRST_CON10);
776
777 return 0;
778 }
779 #endif
780
781 #ifdef CONFIG_SPL_BUILD
spl_fit_standalone_release(char * id,uintptr_t entry_point)782 int spl_fit_standalone_release(char *id, uintptr_t entry_point)
783 {
784 /*
785 * Fix mcu does not work probabilistically through reset the
786 * mcu debug module. If use the jtag debug, reset it.
787 */
788 writel(0x80008000, GRF_BASE + GRF_SOC_CON2);
789 /* Reset the scr1 */
790 writel(0x04000400, CRU_BASE + CRU_SOFTRST_CON02);
791 udelay(100);
792 /* set the scr1 addr */
793 writel(entry_point, SGRF_BASE + SGRF_CON_SCR1_BOOT_ADDR);
794 writel(0x00ff00bf, SGRF_BASE + SGRF_SOC_CON3);
795 udelay(10);
796 /* release the scr1 */
797 writel(0x04000000, CRU_BASE + CRU_SOFTRST_CON02);
798
799 return 0;
800 }
801 #endif
802