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Searched refs:DE (Results 1 – 7 of 7) sorted by relevance

/rk3399_rockchip-uboot/arch/arm/mach-sunxi/
H A Ddram_sunxi_dw.c131 MBUS_CONF( DE, true, HIGHEST, 3, 8192, 6120, 1024); in mctl_set_master_priority_h3()
156 MBUS_CONF( DE, true, HIGH, 2, 8192, 6144, 2048); in mctl_set_master_priority_a64()
186 MBUS_CONF( DE, true, HIGHEST, 3, 3400, 2400, 1024); in mctl_set_master_priority_h5()
219 MBUS_CONF( DE, true, HIGH, 0, 128, 48, 0); in mctl_set_master_priority_r40()
/rk3399_rockchip-uboot/drivers/ddr/marvell/axp/
H A Dddr3_read_leveling.c847 dram_info->rl_val[cs][idx][DE] = delay; in ddr3_read_leveling_single_cs_window_mode()
1102 DEBUG_RL_D((u32) dram_info->rl_val[cs][pup][DE], 2); in ddr3_read_leveling_single_cs_window_mode()
1119 MAX_DELAY_INV + dram_info->rl_val[cs][idx][DE]; in ddr3_read_leveling_single_cs_window_mode()
1136 MAX_DELAY + dram_info->rl_val[cs][idx][DE]; in ddr3_read_leveling_single_cs_window_mode()
1158 dram_info->rl_val[cs][idx][DE]; in ddr3_read_leveling_single_cs_window_mode()
H A Dddr3_hw_training.h120 #define DE 5 macro
/rk3399_rockchip-uboot/doc/
H A DREADME.mpc85xx7 - MSR[DE] must be set
11 To maximize the time during which this requirement is met, U-Boot sets MSR[DE]
H A DREADME.socfpga137 Here is an example for the DE-0 Nano SoC after the above rebuild process:
H A DREADME.odroid168 setenv usbethaddr 02:DE:AD:BE:EF:FF
174 Odroid # setenv usbethaddr 02:DE:AD:BE:EF:FF
/rk3399_rockchip-uboot/common/
H A Ddlmalloc.src3230 (wmglo@Dent.MED.Uni-Muenchen.DE).