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Searched refs:DCACHE (Results 1 – 5 of 5) sorted by relevance

/rk3399_rockchip-uboot/arch/nds32/lib/
H A Dcache.c141 line_size = CACHE_LINE_SIZE(DCACHE); in dcache_wbinval_all()
142 end = line_size * CACHE_WAY(DCACHE) * CACHE_SET(DCACHE); in dcache_wbinval_all()
164 line_size = CACHE_LINE_SIZE(DCACHE); in flush_dcache_range()
179 line_size = CACHE_LINE_SIZE(DCACHE); in invalidate_dcache_range()
/rk3399_rockchip-uboot/arch/mips/include/asm/
H A Dcachectl.h13 #define DCACHE (1<<1) /* writeback and flush data cache */ macro
14 #define BCACHE (ICACHE|DCACHE) /* flush both caches */
/rk3399_rockchip-uboot/arch/arm/cpu/armv7m/
H A Dcache.c42 DCACHE, enumerator
120 if (type == DCACHE) in get_cline_size()
149 type = DCACHE; in action_cache_range()
/rk3399_rockchip-uboot/arch/nds32/include/asm/
H A Dcache.h31 enum cache_t {ICACHE, DCACHE}; enumerator
/rk3399_rockchip-uboot/
H A DREADME4870 is this: Using DCACHE as initial RAM for Stack, etc, does not