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Searched refs:CRU_CPLL_CON1 (Results 1 – 2 of 2) sorted by relevance

/rk3399_rockchip-uboot/drivers/video/drm/rk628/
H A Drk628_cru.c95 rk628_i2c_read(rk628, offset + CRU_CPLL_CON1, &con1); in rk628_cru_clk_get_rate_pll()
158 rk628_i2c_write(rk628, offset + CRU_CPLL_CON1, PLL_PD(1)); in rk628_cru_clk_set_rate_pll()
162 rk628_i2c_write(rk628, offset + CRU_CPLL_CON1, PLL_PD(0)); in rk628_cru_clk_set_rate_pll()
164 rk628_i2c_read(rk628, offset + CRU_CPLL_CON1, &val); in rk628_cru_clk_set_rate_pll()
257 rk628_i2c_write(rk628, offset + CRU_CPLL_CON1, in rk628_cru_clk_set_rate_pll()
263 rk628_i2c_write(rk628, offset + CRU_CPLL_CON1, PLL_PD(0)); in rk628_cru_clk_set_rate_pll()
266 rk628_i2c_read(rk628, offset + CRU_CPLL_CON1, &val); in rk628_cru_clk_set_rate_pll()
H A Drk628_cru.h25 #define CRU_CPLL_CON1 CRU_REG(0x0004) macro