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Searched refs:CONCONTROL_UPDATE_MODE (Results 1 – 2 of 2) sorted by relevance

/rk3399_rockchip-uboot/arch/arm/mach-exynos/include/mach/
H A Ddmc.h453 #define CONCONTROL_UPDATE_MODE (1 << 3) macro
/rk3399_rockchip-uboot/arch/arm/mach-exynos/
H A Ddmc_init_ddr3.c858 val |= CONCONTROL_UPDATE_MODE; in ddr3_mem_ctrl_init()
861 val |= CONCONTROL_UPDATE_MODE; in ddr3_mem_ctrl_init()