Searched refs:CLK_V1PLL_DIV (Results 1 – 2 of 2) sorted by relevance
107 RK3506_CLK_DUMP(CLK_V1PLL_DIV, "clk_v1pll_div"),292 case CLK_V1PLL_DIV: in rk3506_pll_div_get_rate()329 case CLK_V1PLL_DIV: in rk3506_pll_div_set_rate()1044 case CLK_V1PLL_DIV: in rk3506_clk_get_rate()1120 case CLK_V1PLL_DIV: in rk3506_clk_set_rate()1212 priv->v1pll_div_hz = rk3506_pll_div_get_rate(priv, CLK_V1PLL_DIV); in rk3506_clk_init()
25 #define CLK_V1PLL_DIV 24 macro