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Searched refs:CLK_GPLL_DIV_100M_MASK (Results 1 – 2 of 2) sorted by relevance

/rk3399_rockchip-uboot/arch/arm/include/asm/arch-rockchip/
H A Dcru_rk3506.h111 CLK_GPLL_DIV_100M_MASK = 0xf << CLK_GPLL_DIV_100M_SHIFT, enumerator
/rk3399_rockchip-uboot/drivers/clk/rockchip/
H A Dclk_rk3506.c284 div = (con & CLK_GPLL_DIV_100M_MASK) >> CLK_GPLL_DIV_100M_SHIFT; in rk3506_pll_div_get_rate()
320 rk_clrsetreg(&cru->clksel_con[0], CLK_GPLL_DIV_100M_MASK, in rk3506_pll_div_set_rate()