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Searched refs:CLK_GPLL_DIV_100M (Results 1 – 2 of 2) sorted by relevance

/rk3399_rockchip-uboot/drivers/clk/rockchip/
H A Dclk_rk3506.c105 RK3506_CLK_DUMP(CLK_GPLL_DIV_100M, "clk_gpll_div_100m"),
282 case CLK_GPLL_DIV_100M: in rk3506_pll_div_get_rate()
317 case CLK_GPLL_DIV_100M: in rk3506_pll_div_set_rate()
1042 case CLK_GPLL_DIV_100M: in rk3506_clk_get_rate()
1118 case CLK_GPLL_DIV_100M: in rk3506_clk_set_rate()
1204 priv->gpll_div_100mhz = rk3506_pll_div_get_rate(priv, CLK_GPLL_DIV_100M); in rk3506_clk_init()
/rk3399_rockchip-uboot/include/dt-bindings/clock/
H A Drockchip,rk3506-cru.h23 #define CLK_GPLL_DIV_100M 22 macro