Searched refs:CGU_CLK_CPLL (Results 1 – 3 of 3) sorted by relevance
71 if (id == CGU_CLK_CPLL) { in rk628_cru_clk_get_rate_pll()150 if (id == CGU_CLK_CPLL) in rk628_cru_clk_set_rate_pll()286 parent_rate = rk628_cru_clk_get_rate_pll(rk628, CGU_CLK_CPLL); in rk628_cru_clk_set_rate_sclk_vop()307 parent_rate = rk628_cru_clk_get_rate_pll(rk628, CGU_CLK_CPLL); in rk628_cru_clk_get_rate_sclk_vop()328 parent_rate = rk628_cru_clk_get_rate_pll(rk628, CGU_CLK_CPLL); in rk628_cru_clk_get_rate_clk_imodet()349 parent_rate = rk628_cru_clk_get_rate_pll(rk628, CGU_CLK_CPLL); in rk628_cru_clk_set_rate_rx_read()369 parent_rate = rk628_cru_clk_get_rate_pll(rk628, CGU_CLK_CPLL); in rk628_cru_clk_get_rate_uart_src()442 parent_rate = rk628_cru_clk_get_rate_pll(rk628, CGU_CLK_CPLL); in rk628_cru_clk_get_rate_sclk_hdmirx_aud()463 parent_rate = rk628_cru_clk_get_rate_pll(rk628, CGU_CLK_CPLL); in rk628_cru_clk_get_rate_bt1120_dec_parent()502 case CGU_CLK_CPLL: in rk628_cru_clk_set_rate()[all …]
136 #define CGU_CLK_CPLL 1 macro
162 modetclk_hz = rk628_cru_clk_get_rate(rk628, CGU_CLK_CPLL) / 24; in rk628_hdmirx_get_timing()