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Searched refs:CACHE_LINE_SIZE (Results 1 – 4 of 4) sorted by relevance

/rk3399_rockchip-uboot/arch/powerpc/cpu/mpc86xx/
H A Dcache.S10 #ifndef CACHE_LINE_SIZE
11 # define CACHE_LINE_SIZE L1_CACHE_BYTES macro
14 #if CACHE_LINE_SIZE == 128
16 #elif CACHE_LINE_SIZE == 32
18 #elif CACHE_LINE_SIZE == 16
20 #elif CACHE_LINE_SIZE == 8
57 lis r5,CACHE_LINE_SIZE
62 lis r5,CACHE_LINE_SIZE
75 li r5,CACHE_LINE_SIZE-1
84 addi r3,r3,CACHE_LINE_SIZE
[all …]
/rk3399_rockchip-uboot/arch/nds32/lib/
H A Dcache.c31 static inline unsigned long CACHE_LINE_SIZE(enum cache_t cache) in CACHE_LINE_SIZE() function
46 line_size = CACHE_LINE_SIZE(ICACHE); in invalidate_icache_all()
66 line_size = CACHE_LINE_SIZE(ICACHE); in invalidate_icache_range()
141 line_size = CACHE_LINE_SIZE(DCACHE); in dcache_wbinval_all()
164 line_size = CACHE_LINE_SIZE(DCACHE); in flush_dcache_range()
179 line_size = CACHE_LINE_SIZE(DCACHE); in invalidate_dcache_range()
/rk3399_rockchip-uboot/drivers/ddr/marvell/axp/
H A Dddr3_sdram.c575 flush_l1_v7(line + CACHE_LINE_SIZE); in ddr3_flush_l1_line()
579 flush_l1_v6(line + CACHE_LINE_SIZE); in ddr3_flush_l1_line()
H A Dddr3_hw_training.h90 #define CACHE_LINE_SIZE 0x20 macro