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Searched refs:CACHELINE_SIZE (Results 1 – 2 of 2) sorted by relevance

/rk3399_rockchip-uboot/drivers/usb/dwc3/
H A Dio.h23 #define CACHELINE_SIZE CONFIG_SYS_CACHELINE_SIZE macro
53 invalidate_dcache_range(addr, addr + ROUND(length, CACHELINE_SIZE)); in dwc3_invalidate_cache()
58 flush_dcache_range(addr, addr + ROUND(length, CACHELINE_SIZE)); in dwc3_flush_cache()
/rk3399_rockchip-uboot/drivers/usb/host/
H A Dxhci-mem.c27 #define CACHELINE_SIZE CONFIG_SYS_CACHELINE_SIZE macro
39 flush_dcache_range(addr & ~(CACHELINE_SIZE - 1), in xhci_flush_cache()
40 ALIGN(addr + len, CACHELINE_SIZE)); in xhci_flush_cache()
54 invalidate_dcache_range(addr & ~(CACHELINE_SIZE - 1), in xhci_inval_cache()
55 ALIGN(addr + len, CACHELINE_SIZE)); in xhci_inval_cache()
193 size_t cacheline_size = max(XHCI_ALIGNMENT, CACHELINE_SIZE); in xhci_malloc()