1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * include/linux/mfd/serdes/gpio.h -- GPIO for different serdes chip 4 * 5 * Copyright (c) 2023-2028 Rockchip Electronics Co. Ltd. 6 * 7 * Author: luowei <lw@rock-chips.com> 8 * 9 */ 10 11 #ifndef __MFD_SERDES_ROHM_BU18RL82_H__ 12 #define __MFD_SERDES_ROHM_BU18RL82_H__ 13 #define BU18RL82_REG_RESET 0X000E 14 15 #define BU18RL82_BLOCK_EN_CLLRX0 0x0011 //h [0] 1’b1 16 #define BU18RL82_BLOCK_EN_LVDSTX0 0x0011 //h [1] 1’b0 17 #define BU18RL82_BLOCK_EN_VPLL0 0x0011 //h [3] 1’b0 18 #define BU18RL82_BLOCK_EN_SSCG0 0x0011 //h [4] 1’b0 19 #define BU18RL82_BLOCK_EN_CLLRX1 0x0012 //h [0] 1’b1 20 #define BU18RL82_BLOCK_EN_LVDSTX1 0x0012 //h [1] 1’b0 21 #define BU18RL82_BLOCK_EN_VPLL1 0x0012 //h [3] 1’b0 22 #define BU18RL82_BLOCK_EN_SSCG1 0x0012 //h [4] 1’b0 23 #define BU18RL82_BLOCK_EN_CLLTX 0x0013 //h [0] 1’b0 24 #define BU18RL82_BLOCK_EN_FSAFETY 0x0013 //h [1] 1’b0 25 26 #define BU18RL82_IO_SW_GPIO0 0x0057 //h [2:1] 2’b00 27 #define BU18RL82_IO_OEN_GPIO0 0x0057 //h [3] 1’b1 28 #define BU18RL82_IO_PDEN_GPIO0 0x0057 //h [4] 1’b1 29 #define BU18RL82_IO_SW_GPIO1 0x005A //h [2:1] 2’b00 30 #define BU18RL82_IO_OEN_GPIO1 0x005A //h [3] 1’b1 31 #define BU18RL82_IO_PDEN_GPIO1 0x005A //h [4] 1’b1 32 #define BU18RL82_IO_SW_GPIO2 0x005D //h [2:1] 2’b00 33 #define BU18RL82_IO_OEN_GPIO2 0x005D //h [3] 1’b1 34 #define BU18RL82_IO_PDEN_GPIO2 0x005D //h [4] 1’b1 35 #define BU18RL82_IO_SW_GPIO3 0x0060 //h [2:1] 2’b00 36 #define BU18RL82_IO_OEN_GPIO3 0x0060 //h [3] 1’b1 37 #define BU18RL82_IO_PDEN_GPIO3 0x0060 //h [4] 1’b1 38 #define BU18RL82_IO_SW_GPIO4 0x0063 //h [2:1] 2’b00 39 #define BU18RL82_IO_OEN_GPIO4 0x0063 //h [3] 1’b1 40 #define BU18RL82_IO_PDEN_GPIO4 0x0063 //h [4] 1’b1 41 #define BU18RL82_IO_SW_GPIO5 0x0066 //h [2:1] 2’b00 42 #define BU18RL82_IO_OEN_GPIO5 0x0066 //h [2:1] 2’b00 43 #define BU18RL82_IO_PDEN_GPIO5 0x0066 //h [3] 1’b1 44 #define BU18RL82_IO_SW_GPIO6 0x0069 //h [2:1] 2’b00 45 #define BU18RL82_IO_OEN_GPIO6 0x0069 //h [3] 1’b1 46 #define BU18RL82_IO_PDEN_GPIO6 0x0069 //h [4] 1’b1 47 #define BU18RL82_IO_SW_GPIO7 0x006C //h [2:1] 2’b00 48 #define BU18RL82_IO_OEN_GPIO7 0x006C //h [3] 1’b1 49 #define BU18RL82_IO_PDEN_GPIO7 0x006C //h [4] 1’b1 50 51 /* 52 * gpio register for define connection with des gpiox, 53 * 11bits such as 0x002c:002b=[b2..b0 b7...b0] 54 * default value: 55 * ser gpio0-->des gpio0 56 * ser gpio1-->des gpio1 57 * ser gpio2-->des gpio2 58 * ser gpio3-->des gpio3 59 */ 60 #define BU18RL82_GPIO_SEL0_HIGH 0x0059 //h [2:0], 61 #define BU18RL82_GPIO_SEL0_LOW 0x0058 //h [7:0]} 11’h002 62 #define BU18RL82_GPIO_SEL1_HIGH 0x005C //h [2:0], 63 #define BU18RL82_GPIO_SEL1_LOW 0x005B //h [7:0]} 11’h003 64 #define BU18RL82_GPIO_SEL2_HIGH 0x005F //h [2:0], 65 #define BU18RL82_GPIO_SEL2_LOW 0x005E //h [7:0]} 11’h012 66 #define BU18RL82_GPIO_SEL3_HIGH 0x0062 //h [2:0], 67 #define BU18RL82_GPIO_SEL3_LOW 0x0061 //h [7:0]} 11’h013 68 #define BU18RL82_GPIO_SEL4_HIGH 0x0065 //h [2:0], 69 #define BU18RL82_GPIO_SEL4_LOW 0x0064 //h [7:0]} 11’h006 70 #define BU18RL82_GPIO_SEL5_HIGH 0x0068 //h [2:0], 71 #define BU18RL82_GPIO_SEL5_LOW 0x0067 //h [7:0]} 11’h007 72 #define BU18RL82_GPIO_SEL6_HIGH 0x006B //h [2:0], 73 #define BU18RL82_GPIO_SEL6_LOW 0x006A //h [7:0]} 11’h008 74 #define BU18RL82_GPIO_SEL7_HIGH 0x006E //h [2:0], 75 #define BU18RL82_GPIO_SEL7_LOW 0x006D //h [7:0]} 11’h009 76 77 /*gpio register for define bu18rl82 gpio pin, and gpio0 to gpio0 default*/ 78 #define BU18RL82_BCCTX0__SEL_GPI0 0x042B //h [5:0] 6’h02 79 #define BU18RL82_BCCTX0__SEL_GPI1 0x042C //h [5:0] 6’h03 80 #define BU18RL82_BCCTX0__SEL_GPI2 0x042D //h [5:0] 6’h04 81 #define BU18RL82_BCCTX0__SEL_GPI3 0x042E //h [5:0] 6’h05 82 #define BU18RL82_BCCTX0__SEL_GPI4 0x042F //h [5:0] 6’h06 83 #define BU18RL82_BCCTX0__SEL_GPI5 0x0430 //h [5:0] 6’h07 84 #define BU18RL82_BCCTX0__SEL_GPI6 0x0431 //h [5:0] 6’h08 85 #define BU18RL82_BCCTX0__SEL_GPI7 0x0432 //h [5:0] 6’h09 86 #define BU18RL82_BCCTX1__SEL_GPI0 0x052B //h [5:0] 6’h02 87 #define BU18RL82_BCCTX1__SEL_GPI1 0x052C //h [5:0] 6’h03 88 #define BU18RL82_BCCTX1__SEL_GPI2 0x052D //h [5:0] 6’h04 89 #define BU18RL82_BCCTX1__SEL_GPI3 0x052E //h [5:0] 6’h05 90 #define BU18RL82_BCCTX1__SEL_GPI4 0x052F //h [5:0] 6’h06 91 #define BU18RL82_BCCTX1__SEL_GPI5 0x0530 //h [5:0] 6’h07 92 #define BU18RL82_BCCTX1__SEL_GPI6 0x0531 //h [5:0] 6’h08 93 #define BU18RL82_BCCTX1__SEL_GPI7 0x0532 //h [5:0] 6’h09 94 95 #define BU18RL82_IEN_CLLRX0_LINK_UNLOCK 0x0109 //h [1] 1’b0 96 #define BU18RL82_IEN_CLLRX0_BIT_ERR 0x0109 //h [3] 1’b0 97 #define BU18RL82_IEN_CLLRX0_ERR_CNT_OVF 0x0109 //h [4] 1’b0 98 #define BU18RL82_IEN_CLLRX1_LINK_UNLOCK 0x010B //h [1] 1’b0 99 #define BU18RL82_IEN_CLLRX1_BIT_ERR 0x010B //h [3] 1’b0 100 #define BU18RL82_IEN_CLLRX1_ERR_CNT_OVF 0x010B //h [4] 1’b0 101 #define BU18RL82_IEN_FCCRX0_CRCERR 0x010D //h [0] 1’b0 102 #define BU18RL82_IEN_FCCRX1_CRCERR 0x010E //h [0] 1’b0 103 #define BU18RL82_IEN_BCCDES0_ERR_CRC 0x010F //h [3] 1’b0 104 #define BU18RL82_IEN_CLLRX0_CRCERR_R 0x0110 //h [0] 1’b0 105 #define BU18RL82_IEN_CLLRX0_CRCERR_G 0x0110 //h [1] 1’b0 106 #define BU18RL82_IEN_CLLRX0_CRCERR_B 0x0110 //h [2] 1’b0 107 #define BU18RL82_IEN_CLLRX1_CRCERR_R 0x0111 //h [0] 1’b0 108 #define BU18RL82_IEN_CLLRX1_CRCERR_G 0x0111 //h [1] 1’b0 109 #define BU18RL82_IEN_CLLRX1_CRCERR_B 0x0111 //h [2] 1’b0 110 #define BU18RL82_IEN_FS_IMG_STATUS0 0x0112 //h [0] 1’b0 111 #define BU18RL82_IEN_FS_IMG_STATUS1 0x0112 //h [1] 1’b0 112 #define BU18RL82_IEN_FS_IMG_STATUS2 0x0112 //h [2] 1’b0 113 #define BU18RL82_IEN_FS_IMG_STATUS3 0x0112 //h [3] 1’b0 114 #define BU18RL82_IEN_FS_IMG_ERR_REGION0 0x0113 //h [0] 1’b0 115 #define BU18RL82_IEN_FS_IMG_ERR_REGION1 0x0113 //h [1] 1’b0 116 #define BU18RL82_IEN_FS_IMG_ERR_REGION2 0x0113 //h [2] 1’b0 117 #define BU18RL82_IEN_FS_IMG_ERR_REGION3 0x0113 //h [3] 1’b0 118 #define BU18RL82_IEN_FS_IMG_ERR_REGION4 0x0113 //h [4] 1’b0 119 #define BU18RL82_IEN_FS_IMG_ERR_REGION5 0x0113 //h [5] 1’b0 120 #define BU18RL82_IEN_FS_IMG_ERR_REGION6 0x0113 //h [6] 1’b0 121 #define BU18RL82_IEN_FS_IMG_ERR_REGION7 0x0113 //h [7] 1’b0 122 #define BU18RL82_IEN_IO_STUCK_GPIO0 0x0114 //h [0] 1’b0 123 #define BU18RL82_IEN_IO_STUCK_GPIO1 0x0114 //h [1] 1’b0 124 #define BU18RL82_IEN_IO_STUCK_GPIO2 0x0114 //h [2] 1’b0 125 #define BU18RL82_IEN_IO_STUCK_GPIO3 0x0114 //h [3] 1’b0 126 #define BU18RL82_IEN_IO_STUCK_GPIO4 0x0114 //h [4] 1’b0 127 #define BU18RL82_IEN_IO_STUCK_GPIO5 0x0114 //h [5] 1’b0 128 #define BU18RL82_IEN_IO_STUCK_GPIO6 0x0114 //h [6] 1’b0 129 #define BU18RL82_IEN_IO_STUCK_GPIO7 0x0114 //h [7] 1’b0 130 #define BU18RL82_IEN_IO_STUCK_IRQ 0x0115 //h [1] 1’b0 131 #define BU18RL82_IEN_IDS_UNSTABLE 0x0115 //h [7] 1’b0 132 #define BU18RL82_IEN_I2C_A_TIMEOUT 0x0116 //h [0] 1’b0 133 #define BU18RL82_IEN_I2C_A_XMIT_ERR 0x0116 //h [1] 1’b0 134 #define BU18RL82_IEN_REGCRC_ERR_PAGE0 0x0117 //h [0] 1’b0 135 #define BU18RL82_IEN_REGCRC_ERR_PAGE1 0x0117 //h [1] 1’b0 136 #define BU18RL82_IEN_REGCRC_ERR_PAGE2 0x0117 //h [2] 1’b0 137 #define BU18RL82_IEN_REGCRC_ERR_PAGE3 0x0117 //h [3] 1’b0 138 #define BU18RL82_IEN_REGCRC_ERR_PAGE4 0x0117 //h [4] 1’b0 139 #define BU18RL82_IEN_REGCRC_ERR_PAGE5 0x0117 //h [5] 1’b0 140 #define BU18RL82_IEN_REGCRC_ERR_PAGE6 0x0117 //h [6] 1’b0 141 #define BU18RL82_IEN_REGCRC_ERR_PAGE7 0x0117 //h [7] 1’b0 142 #define BU18RL82_IEN_CLKDETECT_CLKIN_STOP 0x0118 //h [0] 1’b0 143 #define BU18RL82_IEN_CLKDETECT_CLKIN_UNLOCK 0x0118 //h [1] 1’b0 144 #define BU18RL82_IEN_CLKDETECT_OSC_STOP 0x0118 //h [4] 1’b0 145 #define BU18RL82_IEN_CLKDETECT_OSC_UNLOCK 0x0118 //h [5] 1’b0 146 #define BU18RL82_IEN_CLKDETECT_CLLRX0_PCLK_STOP 0x0119 //h [0] 1’b0 147 #define BU18RL82_IEN_CLKDETECT_CLLRX0_PCLK_UNLOCK 0x0119 //h [1] 1’b0 148 #define BU18RL82_IEN_CLKDETECT_LVDSTX0_CLK_STOP 0x0119 //h [4] 1’b0 149 #define BU18RL82_IEN_CLKDETECT_LVDSTX0_CLK_UNLOCK 0x0119 //h [5] 1’b0 150 #define BU18RL82_IEN_CLKDETECT_CLLRX1_PCLK_STOP 0x011A //h [0] 1’b0 151 #define BU18RL82_IEN_CLKDETECT_CLLRX1_PCLK_UNLOCK 0x011A //h [1] 1’b0 152 #define BU18RL82_IEN_CLKDETECT_LVDSTX1_CLK_STOP 0x011A //h [4] 1’b0 153 #define BU18RL82_IEN_CLKDETECT_LVDSTX1_CLK_UNLOCK 0x011A //h [5] 1’b0 154 #define BU18RL82_IEN_CLKDETECT_CLLTX0_SCLK_STOP 0x011B //h [0] 1’b0 155 #define BU18RL82_IEN_CLKDETECT_CLLTX0_SCLK_UNLOCK 0x011B //h [1] 1’b0 156 #define BU18RL82_IEN_CLKDETECT_CLLTX0_PLLREF_STOP 0x011B //h [4] 1’b0 157 #define BU18RL82_IEN_CLKDETECT_CLLTX0_PLLREF_UNLOCK 0x011B //h [5] 1’b0 158 #define BU18RL82_IEN_CLKDETECT_LVDSTX0_PLLREF_STOP 0x011C //h [0] 1’b0 159 #define BU18RL82_IEN_CLKDETECT_LVDSTX0_PLLREF_UNLOCK0x011C //h [1] 1’b0 160 #define BU18RL82_IEN_CLKDETECT_LVDSTX1_PLLREF_STOP 0x011C //h [4] 1’b0 161 #define BU18RL82_IEN_CLKDETECT_LVDSTX1_PLLREF_UNLOCK 0x011C //h [5] 1’b0 162 163 #define BU18RL82_ISR_CLEAR_ALL 0x0105 //h [0] 1’b0 164 #define BU18RL82_ISR_CLLRX0_LINK_UNLOCK 0x0129 //h [1] 1’b0 165 #define BU18RL82_ISR_CLLRX0_BIT_ERR 0x0129 //h [3] 1’b0 166 #define BU18RL82_ISR_CLLRX0_ERR_CNT_OVF 0x0129 //h [4] 1’b0 167 #define BU18RL82_ISR_CLLRX1_ERR_CNT_OVF 0x012B //h [4] 1’b0 168 #define BU18RL82_ISR_CLLRX1_LINK_UNLOCK 0x012B //h [1] 1’b0 169 #define BU18RL82_ISR_CLLRX1_BIT_ERR 0x012B //h [3] 1’b0 170 #define BU18RL82_ISR_FCCRX0_CRCERR 0x012D //h [0] 1’b0 171 #define BU18RL82_ISR_FCCRX1_CRCERR 0x012E //h [0] 1’b0 172 #define BU18RL82_ISR_BCCDES0_ERR_CRC 0x012F //h [3] 1’b0 173 #define BU18RL82_ISR_CLLRX0_CRCERR_R 0x0130 //h [0] 1’b0 174 #define BU18RL82_ISR_CLLRX0_CRCERR_G 0x0130 //h [1] 1’b0 175 #define BU18RL82_ISR_CLLRX0_CRCERR_B 0x0130 //h [2] 1’b0 176 #define BU18RL82_ISR_CLLRX1_CRCERR_R 0x0131 //h [0] 1’b0 177 #define BU18RL82_ISR_CLLRX1_CRCERR_G 0x0131 //h [1] 1’b0 178 #define BU18RL82_ISR_CLLRX1_CRCERR_B 0x0131 //h [2] 1’b0 179 #define BU18RL82_ISR_FS_IMG_STATUS0 0x0132 //h [0] 1’b0 180 #define BU18RL82_ISR_FS_IMG_STATUS1 0x0132 //h [1] 1’b0 181 #define BU18RL82_ISR_FS_IMG_STATUS2 0x0132 //h [2] 1’b0 182 #define BU18RL82_ISR_FS_IMG_STATUS3 0x0132 //h [3] 1’b0 183 #define BU18RL82_ISR_FS_IMG_ERR_REGION0 0x0133 //h [0] 1’b0 184 #define BU18RL82_ISR_FS_IMG_ERR_REGION1 0x0133 //h [1] 1’b0 185 #define BU18RL82_ISR_FS_IMG_ERR_REGION2 0x0133 //h [2] 1’b0 186 #define BU18RL82_ISR_FS_IMG_ERR_REGION3 0x0133 //h [3] 1’b0 187 #define BU18RL82_ISR_FS_IMG_ERR_REGION4 0x0133 //h [4] 1’b0 188 #define BU18RL82_ISR_FS_IMG_ERR_REGION5 0x0133 //h [5] 1’b0 189 #define BU18RL82_ISR_FS_IMG_ERR_REGION6 0x0133 //h [6] 1’b0 190 #define BU18RL82_ISR_FS_IMG_ERR_REGION7 0x0133 //h [7] 1’b0 191 #define BU18RL82_ISR_IO_STUCK_GPIO0 0x0134 //h [0] 1’b0 192 #define BU18RL82_ISR_IO_STUCK_GPIO1 0x0134 //h [1] 1’b0 193 #define BU18RL82_ISR_IO_STUCK_GPIO2 0x0134 //h [2] 1’b0 194 #define BU18RL82_ISR_IO_STUCK_GPIO3 0x0134 //h [3] 1’b0 195 #define BU18RL82_ISR_IO_STUCK_GPIO4 0x0134 //h [4] 1’b0 196 #define BU18RL82_ISR_IO_STUCK_GPIO5 0x0134 //h [5] 1’b0 197 #define BU18RL82_ISR_IO_STUCK_GPIO6 0x0134 //h [6] 1’b0 198 #define BU18RL82_ISR_IO_STUCK_GPIO7 0x0134 //h [7] 1’b0 199 #define BU18RL82_ISR_IO_STUCK_IRQ 0x0135 //h [1] 1’b0 200 #define BU18RL82_ISR_IDS_UNSTABLE 0x0135 //h [7] 1’b0 201 #define BU18RL82_ISR_I2C_A_TIMEOUT 0x0136 //h [0] 1’b0 202 #define BU18RL82_ISR_I2C_A_XMIT_ERR 0x0136 //h [1] 1’b0 203 #define BU18RL82_ISR_REGCRC_ERR_PAGE0 0x0137 //h [0] 1’b0 204 #define BU18RL82_ISR_REGCRC_ERR_PAGE1 0x0137 //h [1] 1’b0 205 #define BU18RL82_ISR_REGCRC_ERR_PAGE2 0x0137 //h [2] 1’b0 206 #define BU18RL82_ISR_REGCRC_ERR_PAGE3 0x0137 //h [3] 1’b0 207 #define BU18RL82_ISR_REGCRC_ERR_PAGE4 0x0137 //h [4] 1’b0 208 #define BU18RL82_ISR_REGCRC_ERR_PAGE5 0x0137 //h [5] 1’b0 209 #define BU18RL82_ISR_REGCRC_ERR_PAGE6 0x0137 //h [6] 1’b0 210 #define BU18RL82_ISR_REGCRC_ERR_PAGE7 0x0137 //h [7] 1’b0 211 #define BU18RL82_ISR_CLKDETECT_CLKIN_STOP 0x0138 //h [0] 1’b0 212 #define BU18RL82_ISR_CLKDETECT_CLKIN_UNLOCK 0x0138 //h [1] 1’b0 213 #define BU18RL82_ISR_CLKDETECT_OSC_STOP 0x0138 //h [4] 1’b0 214 #define BU18RL82_ISR_CLKDETECT_OSC_UNLOCK 0x0138 //h [5] 1’b0 215 #define BU18RL82_ISR_CLKDETECT_CLLRX0_PCLK_STOP 0x0139 //h [0] 1’b0 216 #define BU18RL82_ISR_CLKDETECT_CLLRX0_PCLK_UNLOCK 0x0139 //h [1] 1’b0 217 #define BU18RL82_ISR_CLKDETECT_LVDSTX0_CLK_STOP 0x0139 //h [4] 1’b0 218 #define BU18RL82_ISR_CLKDETECT_LVDSTX0_CLK_UNLOCK 0x0139 //h [5] 1’b0 219 #define BU18RL82_ISR_CLKDETECT_CLLRX1_PCLK_STOP 0x013A //h [0] 1’b0 220 #define BU18RL82_ISR_CLKDETECT_CLLRX1_PCLK_UNLOCK 0x013A //h [1] 1’b0 221 #define BU18RL82_ISR_CLKDETECT_LVDSTX1_CLK_STOP 0x013A //h [4] 1’b0 222 #define BU18RL82_ISR_CLKDETECT_LVDSTX1_CLK_UNLOCK 0x013A //h [5] 1’b0 223 #define BU18RL82_ISR_CLKDETECT_CLLTX0_SCLK_STOP 0x013B //h [0] 1’b0 224 #define BU18RL82_ISR_CLKDETECT_CLLTX0_SCLK_UNLOCK 0x013B //h [1] 1’b0 225 #define BU18RL82_ISR_CLKDETECT_CLLTX0_PLLREF_STOP 0x013B //h [4] 1’b0 226 #define BU18RL82_ISR_CLKDETECT_CLLTX0_PLLREF_UNLOCK 0x013B //h [5] 1’b0 227 #define BU18RL82_ISR_CLKDETECT_LVDSTX0_PLLREF_STOP 0x013C //h [0] 1’b0 228 #define BU18RL82_ISR_CLKDETECT_LVDSTX0_PLLREF_UNLOCK0x013C //h [1] 1’b0 229 #define BU18RL82_ISR_CLKDETECT_LVDSTX1_PLLREF_STOP 0x013C //h [4] 1’b0 230 #define BU18RL82_ISR_CLKDETECT_LVDSTX1_PLLREF_UNLOCK 0x013C //h [5] 1’b0 231 232 struct bu18rl82_gpio_sw_reg { 233 unsigned int reg; 234 unsigned int mask; //2/4/6/8ma 235 }; 236 237 struct bu18rl82_gpio_oen_reg { 238 unsigned int reg; 239 unsigned int mask; //0:output 1:input 240 }; 241 242 struct bu18rl82_gpio_pden_reg { 243 unsigned int reg; 244 unsigned int mask; //0:no pulldown 1:connect pulldown 245 }; 246 247 struct bu18rl82_gpio_id_low_reg { 248 unsigned int reg; 249 unsigned int mask; //b2b1b0 250 }; 251 252 struct bu18rl82_gpio_id_high_reg { 253 unsigned int reg; 254 unsigned int mask; //b11b10b9b8b7b6b5b4b3 255 }; 256 257 static const struct bu18rl82_gpio_sw_reg bu18rl82_gpio_sw[8] = { 258 {BU18RL82_IO_SW_GPIO0, BIT(2) | BIT(1)}, 259 {BU18RL82_IO_SW_GPIO1, BIT(2) | BIT(1)}, 260 {BU18RL82_IO_SW_GPIO2, BIT(2) | BIT(1)}, 261 {BU18RL82_IO_SW_GPIO3, BIT(2) | BIT(1)}, 262 {BU18RL82_IO_SW_GPIO4, BIT(2) | BIT(1)}, 263 {BU18RL82_IO_SW_GPIO5, BIT(2) | BIT(1)}, 264 {BU18RL82_IO_SW_GPIO6, BIT(2) | BIT(1)}, 265 {BU18RL82_IO_SW_GPIO7, BIT(2) | BIT(1)}, 266 }; 267 268 static const struct bu18rl82_gpio_oen_reg bu18rl82_gpio_oen[8] = { 269 {BU18RL82_IO_OEN_GPIO0, BIT(3)}, 270 {BU18RL82_IO_OEN_GPIO1, BIT(3)}, 271 {BU18RL82_IO_OEN_GPIO2, BIT(3)}, 272 {BU18RL82_IO_OEN_GPIO3, BIT(3)}, 273 {BU18RL82_IO_OEN_GPIO4, BIT(3)}, 274 {BU18RL82_IO_OEN_GPIO5, BIT(3)}, 275 {BU18RL82_IO_OEN_GPIO6, BIT(3)}, 276 {BU18RL82_IO_OEN_GPIO7, BIT(3)}, 277 }; 278 279 static const struct bu18rl82_gpio_pden_reg bu18rl82_gpio_pden[8] = { 280 {BU18RL82_IO_PDEN_GPIO0, BIT(4)}, 281 {BU18RL82_IO_PDEN_GPIO1, BIT(4)}, 282 {BU18RL82_IO_PDEN_GPIO2, BIT(4)}, 283 {BU18RL82_IO_PDEN_GPIO3, BIT(4)}, 284 {BU18RL82_IO_PDEN_GPIO4, BIT(4)}, 285 {BU18RL82_IO_PDEN_GPIO5, BIT(4)}, 286 {BU18RL82_IO_PDEN_GPIO6, BIT(4)}, 287 {BU18RL82_IO_PDEN_GPIO7, BIT(4)}, 288 }; 289 290 static const struct bu18rl82_gpio_id_low_reg bu18rl82_gpio_id_low[8] = { 291 {BU18RL82_GPIO_SEL0_LOW, GENMASK(7, 0)}, 292 {BU18RL82_GPIO_SEL1_LOW, GENMASK(7, 0)}, 293 {BU18RL82_GPIO_SEL2_LOW, GENMASK(7, 0)}, 294 {BU18RL82_GPIO_SEL3_LOW, GENMASK(7, 0)}, 295 {BU18RL82_GPIO_SEL4_LOW, GENMASK(7, 0)}, 296 {BU18RL82_GPIO_SEL5_LOW, GENMASK(7, 0)}, 297 {BU18RL82_GPIO_SEL6_LOW, GENMASK(7, 0)}, 298 {BU18RL82_GPIO_SEL7_LOW, GENMASK(7, 0)}, 299 }; 300 301 static const struct bu18rl82_gpio_id_high_reg bu18rl82_gpio_id_high[8] = { 302 {BU18RL82_GPIO_SEL0_HIGH, GENMASK(2, 0)}, 303 {BU18RL82_GPIO_SEL1_HIGH, GENMASK(2, 0)}, 304 {BU18RL82_GPIO_SEL2_HIGH, GENMASK(2, 0)}, 305 {BU18RL82_GPIO_SEL3_HIGH, GENMASK(2, 0)}, 306 {BU18RL82_GPIO_SEL4_HIGH, GENMASK(2, 0)}, 307 {BU18RL82_GPIO_SEL5_HIGH, GENMASK(2, 0)}, 308 {BU18RL82_GPIO_SEL6_HIGH, GENMASK(2, 0)}, 309 {BU18RL82_GPIO_SEL7_HIGH, GENMASK(2, 0)}, 310 }; 311 312 struct bu18rl82_ien_reg { 313 unsigned int reg; 314 unsigned int ien; 315 }; 316 317 struct bu18rl82_isr_reg { 318 unsigned int reg; 319 unsigned int isr; 320 }; 321 322 struct bu18rl82_gpio_reg { 323 unsigned int reg; 324 unsigned int val; 325 }; 326 327 static const struct bu18rl82_ien_reg bu18rl82_reg_ien[18] = { 328 {BU18RL82_IEN_CLLRX0_LINK_UNLOCK, 329 BIT(1) | BIT(3) | BIT(4)}, 330 {BU18RL82_IEN_CLLRX1_LINK_UNLOCK, 331 BIT(1) | BIT(3) | BIT(4)}, 332 {BU18RL82_IEN_FCCRX0_CRCERR, BIT(0)}, 333 {BU18RL82_IEN_FCCRX1_CRCERR, BIT(0)}, 334 335 {BU18RL82_IEN_BCCDES0_ERR_CRC, BIT(3)}, 336 {BU18RL82_IEN_CLLRX0_CRCERR_R, 337 BIT(0) | BIT(1) | BIT(2)}, 338 {BU18RL82_IEN_CLLRX1_CRCERR_R, 339 BIT(0) | BIT(1) | BIT(2)}, 340 341 {BU18RL82_IEN_FS_IMG_STATUS0, 342 BIT(0) | BIT(1) | BIT(2) | BIT(3)}, 343 {BU18RL82_IEN_FS_IMG_ERR_REGION0, 0xff}, 344 {BU18RL82_IEN_IO_STUCK_GPIO0, 0xff}, 345 {BU18RL82_IEN_IO_STUCK_IRQ, BIT(1) | BIT(7)}, 346 {BU18RL82_IEN_I2C_A_TIMEOUT, BIT(0) | BIT(1)}, 347 348 {BU18RL82_IEN_REGCRC_ERR_PAGE0, 0xff}, 349 {BU18RL82_IEN_CLKDETECT_CLKIN_STOP, 350 BIT(0) | BIT(1) | BIT(4) | BIT(5)}, 351 {BU18RL82_IEN_CLKDETECT_CLLRX0_PCLK_STOP, 352 BIT(0) | BIT(1) | BIT(4) | BIT(5)}, 353 {BU18RL82_IEN_CLKDETECT_CLLRX1_PCLK_STOP, 354 BIT(0) | BIT(1) | BIT(4) | BIT(5)}, 355 {BU18RL82_IEN_CLKDETECT_CLLTX0_SCLK_STOP, 356 BIT(0) | BIT(1) | BIT(4) | BIT(5)}, 357 {BU18RL82_IEN_CLKDETECT_LVDSTX0_PLLREF_STOP, 358 BIT(0) | BIT(1) | BIT(4) | BIT(5)}, 359 }; 360 361 static const struct bu18rl82_isr_reg bu18rl82_reg_isr[18] = { 362 {BU18RL82_ISR_CLLRX0_LINK_UNLOCK, 363 BIT(1) | BIT(3) | BIT(4)}, 364 {BU18RL82_ISR_CLLRX1_LINK_UNLOCK, 365 BIT(1) | BIT(3) | BIT(4)}, 366 {BU18RL82_ISR_FCCRX0_CRCERR, BIT(0)}, 367 {BU18RL82_ISR_FCCRX1_CRCERR, BIT(0)}, 368 369 {BU18RL82_ISR_BCCDES0_ERR_CRC, BIT(3)}, 370 {BU18RL82_ISR_CLLRX0_CRCERR_R, 371 BIT(0) | BIT(1) | BIT(2)}, 372 {BU18RL82_ISR_CLLRX1_CRCERR_R, 373 BIT(0) | BIT(1) | BIT(2)}, 374 375 {BU18RL82_ISR_FS_IMG_STATUS0, 376 BIT(0) | BIT(1) | BIT(2) | BIT(3)}, 377 {BU18RL82_ISR_FS_IMG_ERR_REGION0, 0xff}, 378 {BU18RL82_ISR_IO_STUCK_GPIO0, 0xff}, 379 {BU18RL82_ISR_IO_STUCK_IRQ, BIT(1) | BIT(7)}, 380 {BU18RL82_ISR_I2C_A_TIMEOUT, BIT(0) | BIT(1)}, 381 382 {BU18RL82_ISR_REGCRC_ERR_PAGE0, 0xff}, 383 {BU18RL82_ISR_CLKDETECT_CLKIN_STOP, 384 BIT(0) | BIT(1) | BIT(4) | BIT(5)}, 385 {BU18RL82_ISR_CLKDETECT_CLLRX0_PCLK_STOP, 386 BIT(0) | BIT(1) | BIT(4) | BIT(5)}, 387 {BU18RL82_ISR_CLKDETECT_CLLRX1_PCLK_STOP, 388 BIT(0) | BIT(1) | BIT(4) | BIT(5)}, 389 {BU18RL82_ISR_CLKDETECT_CLLTX0_SCLK_STOP, 390 BIT(0) | BIT(1) | BIT(4) | BIT(5)}, 391 {BU18RL82_ISR_CLKDETECT_LVDSTX0_PLLREF_STOP, 392 BIT(0) | BIT(1) | BIT(4) | BIT(5)}, 393 }; 394 395 #endif 396