Searched refs:BL (Results 1 – 9 of 9) sorted by relevance
152 DIV_ROUND_UP(T_WTR_TCK, 2)) + WL + BL; in ddr2_ctrl_init()154 wr2prech = DIV_ROUND_UP(T_WR, T_CK_CTRL) + WL + BL; in ddr2_ctrl_init()156 DIV_ROUND_UP(T_RTP_TCK, 2)) + BL - 2; in ddr2_ctrl_init()164 ((BL - 1) << 8) | in ddr2_ctrl_init()165 (BL << 12) | in ddr2_ctrl_init()166 ((BL - 1) << 16) | in ddr2_ctrl_init()167 ((BL - 1) << 20) | in ddr2_ctrl_init()168 ((BL + 2) << 24) | in ddr2_ctrl_init()
16 #define BL 2 macro34 #define T_RTP_TCK (BL / 2)
94 ! BL bit off (init = ON) (?!?)96 stc sr, r0 ! BL bit off(init=ON)
122 ! BL bit off (init = ON) (?!?)124 stc sr, r0 ! BL bit off(init=ON)
108 ! BL bit off (init = ON) (?!?)110 stc sr, r0 ! BL bit off(init=ON)
59 * CAS=3 BL=4
133 /* SDE_1=0; ROW=3; BL=1; DSIZ=2 -> 64 bit */
142 #define BL(x) (((x) & 0x7) << 8) macro
67 Separate the definitions for memory regions used for the BL stage