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Searched refs:AR934X_SRIF_DDR_DPLL1_REG (Results 1 – 2 of 2) sorted by relevance

/rk3399_rockchip-uboot/arch/mips/mach-ath79/ar934x/
H A Dclk.c195 ar934x_srif_pll_cfg(srif_regs + AR934X_SRIF_DDR_DPLL1_REG, ddr_srif); in ar934x_pll_init()
/rk3399_rockchip-uboot/arch/mips/mach-ath79/include/mach/
H A Dar71xx_regs.h1129 #define AR934X_SRIF_DDR_DPLL1_REG 0x240 macro