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Searched refs:AR934X_PLL_DDR_CONFIG_REG (Results 1 – 2 of 2) sorted by relevance

/rk3399_rockchip-uboot/arch/mips/mach-ath79/ar934x/
H A Dclk.c180 pll_regs + AR934X_PLL_DDR_CONFIG_REG); in ar934x_pll_init()
270 ddr = readl(regs + AR934X_PLL_DDR_CONFIG_REG); in ar934x_update_clock()
/rk3399_rockchip-uboot/arch/mips/mach-ath79/include/mach/
H A Dar71xx_regs.h352 #define AR934X_PLL_DDR_CONFIG_REG 0x04 macro