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Searched refs:AR71XX_PLL_BASE (Results 1 – 7 of 7) sorted by relevance

/rk3399_rockchip-uboot/arch/mips/mach-ath79/
H A Dreset.c78 void __iomem *pregs = map_physmem(AR71XX_PLL_BASE, AR71XX_PLL_SIZE, in eth_init_ar933x()
113 void __iomem *pregs = map_physmem(AR71XX_PLL_BASE, AR71XX_PLL_SIZE, in eth_init_ar934x()
209 void __iomem *pregs = map_physmem(AR71XX_PLL_BASE, AR71XX_PLL_SIZE, in usb_reset_qca953x()
/rk3399_rockchip-uboot/arch/mips/mach-ath79/ar933x/
H A Dclk.c37 regs = map_physmem(AR71XX_PLL_BASE, AR71XX_PLL_SIZE, in get_clocks()
H A Dlowlevel_init.S158 li t0, CKSEG1ADDR(AR71XX_PLL_BASE)
272 li t0, CKSEG1ADDR(AR71XX_PLL_BASE)
/rk3399_rockchip-uboot/arch/mips/mach-ath79/qca953x/
H A Dclk.c37 regs = map_physmem(AR71XX_PLL_BASE, AR71XX_PLL_SIZE, in get_clocks()
H A Dlowlevel_init.S135 li t0, CKSEG1ADDR(AR71XX_PLL_BASE)
/rk3399_rockchip-uboot/arch/mips/mach-ath79/ar934x/
H A Dclk.c108 void __iomem *pll_regs = map_physmem(AR71XX_PLL_BASE, in ar934x_pll_init()
266 regs = map_physmem(AR71XX_PLL_BASE, AR71XX_PLL_SIZE, in ar934x_update_clock()
/rk3399_rockchip-uboot/arch/mips/mach-ath79/include/mach/
H A Dar71xx_regs.h47 #define AR71XX_PLL_BASE \ macro