Home
last modified time | relevance | path

Searched refs:tWR_IN_NS (Results 1 – 3 of 3) sorted by relevance

/rk3399_ARM-atf/plat/intel/soc/agilex5/soc/
H A Dagilex5_memory_controller.c31 #define tWR_IN_NS 15 macro
245 tw_rin_clk_cycles = (((tWR_IN_NS * 1333) % 1000) >= 500) ? in configure_ddr_sched_ctrl_regs()
246 ((tWR_IN_NS * 1333) / 1000) + 1 : in configure_ddr_sched_ctrl_regs()
247 ((tWR_IN_NS * 1333) / 1000); in configure_ddr_sched_ctrl_regs()
253 tw_rin_clk_cycles = (((tWR_IN_NS * 1066) % 1000) >= 500) ? in configure_ddr_sched_ctrl_regs()
254 ((tWR_IN_NS * 1066) / 1000) + 1 : in configure_ddr_sched_ctrl_regs()
255 ((tWR_IN_NS * 1066) / 1000); in configure_ddr_sched_ctrl_regs()
/rk3399_ARM-atf/plat/intel/soc/agilex/soc/
H A Dagilex_memory_controller.c30 #define tWR_IN_NS 15 macro
244 tw_rin_clk_cycles = (((tWR_IN_NS * 1333) % 1000) >= 500) ? in configure_ddr_sched_ctrl_regs()
245 ((tWR_IN_NS * 1333) / 1000) + 1 : in configure_ddr_sched_ctrl_regs()
246 ((tWR_IN_NS * 1333) / 1000); in configure_ddr_sched_ctrl_regs()
252 tw_rin_clk_cycles = (((tWR_IN_NS * 1066) % 1000) >= 500) ? in configure_ddr_sched_ctrl_regs()
253 ((tWR_IN_NS * 1066) / 1000) + 1 : in configure_ddr_sched_ctrl_regs()
254 ((tWR_IN_NS * 1066) / 1000); in configure_ddr_sched_ctrl_regs()
/rk3399_ARM-atf/plat/intel/soc/stratix10/soc/
H A Ds10_memory_controller.c34 #define tWR_IN_NS 15 macro
273 tw_rin_clk_cycles = (((tWR_IN_NS * 1333) % 1000) >= 500) ? in configure_ddr_sched_ctrl_regs()
274 ((tWR_IN_NS * 1333) / 1000) + 1 : in configure_ddr_sched_ctrl_regs()
275 ((tWR_IN_NS * 1333) / 1000); in configure_ddr_sched_ctrl_regs()
281 tw_rin_clk_cycles = (((tWR_IN_NS * 1066) % 1000) >= 500) ? in configure_ddr_sched_ctrl_regs()
282 ((tWR_IN_NS * 1066) / 1000) + 1 : in configure_ddr_sched_ctrl_regs()
283 ((tWR_IN_NS * 1066) / 1000); in configure_ddr_sched_ctrl_regs()