1 #ifndef __ODY_CSRS_SMMU_H__
2 #define __ODY_CSRS_SMMU_H__
3 /* This file is auto-generated. Do not edit */
4
5 /***********************license start***********************************
6 * Copyright (C) 2021-2026 Marvell.
7 * SPDX-License-Identifier: BSD-3-Clause
8 * https://spdx.org/licenses
9 ***********************license end**************************************/
10
11
12 /**
13 * @file
14 *
15 * Configuration and status register (CSR) address and type definitions for
16 * SMMU.
17 *
18 * This file is auto generated. Do not edit.
19 *
20 */
21
22 /**
23 * Enumeration smmu_bar_e
24 *
25 * SMMU Base Address Register Enumeration
26 * Enumerates the base address registers.
27 */
28 #define ODY_SMMU_BAR_E_SMMUX_PF_BAR0(a) (0x830000000000ll + 0x1000000000ll * (a))
29 #define ODY_SMMU_BAR_E_SMMUX_PF_BAR0_SIZE 0x200000ull
30
31 /**
32 * Enumeration smmu_cerror_e
33 *
34 * SMMU Command Queue Error Enumeration
35 */
36 #define ODY_SMMU_CERROR_E_ABT (2)
37 #define ODY_SMMU_CERROR_E_CERROR_ATC_INV_SYNC (3)
38 #define ODY_SMMU_CERROR_E_ILL (1)
39 #define ODY_SMMU_CERROR_E_NONE (0)
40
41 /**
42 * Enumeration smmu_cmd_e
43 *
44 * SMMU Command Queue Codes Enumeration
45 */
46 #define ODY_SMMU_CMD_E_ATC_INV (0x40)
47 #define ODY_SMMU_CMD_E_CFGI_CD (5)
48 #define ODY_SMMU_CMD_E_CFGI_CD_ALL (6)
49 #define ODY_SMMU_CMD_E_CFGI_STE (3)
50 #define ODY_SMMU_CMD_E_CFGI_STE_RANGE (4)
51 #define ODY_SMMU_CMD_E_CFGI_VMS_PIDM (7)
52 #define ODY_SMMU_CMD_E_PREFETCH_ADDR (2)
53 #define ODY_SMMU_CMD_E_PREFETCH_CONFIG (1)
54 #define ODY_SMMU_CMD_E_PRI_RESP (0x41)
55 #define ODY_SMMU_CMD_E_RESUME (0x44)
56 #define ODY_SMMU_CMD_E_STALL_TERM (0x45)
57 #define ODY_SMMU_CMD_E_SYNC (0x46)
58 #define ODY_SMMU_CMD_E_TLBI_EL2_ALL (0x20)
59 #define ODY_SMMU_CMD_E_TLBI_EL2_ASID (0x21)
60 #define ODY_SMMU_CMD_E_TLBI_EL2_VA (0x22)
61 #define ODY_SMMU_CMD_E_TLBI_EL2_VAA (0x23)
62 #define ODY_SMMU_CMD_E_TLBI_EL3_ALL (0x18)
63 #define ODY_SMMU_CMD_E_TLBI_EL3_VA (0x1a)
64 #define ODY_SMMU_CMD_E_TLBI_NH_ALL (0x10)
65 #define ODY_SMMU_CMD_E_TLBI_NH_ASID (0x11)
66 #define ODY_SMMU_CMD_E_TLBI_NH_VA (0x12)
67 #define ODY_SMMU_CMD_E_TLBI_NH_VAA (0x13)
68 #define ODY_SMMU_CMD_E_TLBI_NSNH_ALL (0x30)
69 #define ODY_SMMU_CMD_E_TLBI_S12_VMALL (0x28)
70 #define ODY_SMMU_CMD_E_TLBI_S2_IPA (0x2a)
71 #define ODY_SMMU_CMD_E_TLBI_SNH_ALL (0x60)
72 #define ODY_SMMU_CMD_E_TLBI_S_EL2_ALL (0x50)
73 #define ODY_SMMU_CMD_E_TLBI_S_EL2_ASID (0x51)
74 #define ODY_SMMU_CMD_E_TLBI_S_EL2_VA (0x52)
75 #define ODY_SMMU_CMD_E_TLBI_S_EL2_VAA (0x53)
76 #define ODY_SMMU_CMD_E_TLBI_S_S12_VMALL (0x58)
77 #define ODY_SMMU_CMD_E_TLBI_S_S2_IPA (0x5a)
78
79 /**
80 * Enumeration smmu_event_e
81 *
82 * SMMU Event Record Codes Enumeration
83 * Enumerates event record types.
84 */
85 #define ODY_SMMU_EVENT_E_C_BAD_CD (0xa)
86 #define ODY_SMMU_EVENT_E_C_BAD_STE (4)
87 #define ODY_SMMU_EVENT_E_C_BAD_STREAMID (2)
88 #define ODY_SMMU_EVENT_E_C_BAD_SUBSTREAMID (8)
89 #define ODY_SMMU_EVENT_E_E_PAGE_REQUEST (0x24)
90 #define ODY_SMMU_EVENT_E_F_ACCESS (0x12)
91 #define ODY_SMMU_EVENT_E_F_ADDR_SIZE (0x11)
92 #define ODY_SMMU_EVENT_E_F_BAD_ATS_TREQ (5)
93 #define ODY_SMMU_EVENT_E_F_CD_FETCH (9)
94 #define ODY_SMMU_EVENT_E_F_CFG_CONFLICT (0x21)
95 #define ODY_SMMU_EVENT_E_F_PERMISSION (0x13)
96 #define ODY_SMMU_EVENT_E_F_STE_FETCH (3)
97 #define ODY_SMMU_EVENT_E_F_STREAM_DISABLED (6)
98 #define ODY_SMMU_EVENT_E_F_TLB_CONFLICT (0x20)
99 #define ODY_SMMU_EVENT_E_F_TRANSLATION (0x10)
100 #define ODY_SMMU_EVENT_E_F_TRANSL_FORBIDDEN (7)
101 #define ODY_SMMU_EVENT_E_F_UUT (1)
102 #define ODY_SMMU_EVENT_E_F_VMS_FETCH (0x25)
103 #define ODY_SMMU_EVENT_E_F_WALK_EABT (0xb)
104 #define ODY_SMMU_EVENT_E_INTERNAL_ERR (0xfd)
105 #define ODY_SMMU_EVENT_E_INV_REQ (0xff)
106 #define ODY_SMMU_EVENT_E_INV_STAGE (0xfe)
107
108 /**
109 * Enumeration smmu_pmcg_e
110 *
111 * SMMU PMCG Events Enumeration
112 * Enumerates counter types.
113 */
114 #define ODY_SMMU_PMCG_E_ACTIVE_CLOCKS (0x80)
115 #define ODY_SMMU_PMCG_E_ATS_TR (6)
116 #define ODY_SMMU_PMCG_E_ATS_TT (7)
117 #define ODY_SMMU_PMCG_E_CFG_DOUBLE_HIT (0x9a)
118 #define ODY_SMMU_PMCG_E_CFG_HIT (0x98)
119 #define ODY_SMMU_PMCG_E_CFG_MISS (3)
120 #define ODY_SMMU_PMCG_E_CFG_READ (5)
121 #define ODY_SMMU_PMCG_E_CLOCKS (0)
122 #define ODY_SMMU_PMCG_E_TLB_FXL_TTD2B (0x93)
123 #define ODY_SMMU_PMCG_E_TLB_FXL_TTD2T (0x92)
124 #define ODY_SMMU_PMCG_E_TLB_FXL_TTD3P (0x91)
125 #define ODY_SMMU_PMCG_E_TLB_FXL_TTDNONE (0x97)
126 #define ODY_SMMU_PMCG_E_TLB_MISS (2)
127 #define ODY_SMMU_PMCG_E_TLB_WLK_TTD0T (0x86)
128 #define ODY_SMMU_PMCG_E_TLB_WLK_TTD1B (0x85)
129 #define ODY_SMMU_PMCG_E_TLB_WLK_TTD1T (0x84)
130 #define ODY_SMMU_PMCG_E_TLB_WLK_TTD2B (0x83)
131 #define ODY_SMMU_PMCG_E_TLB_WLK_TTD2T (0x82)
132 #define ODY_SMMU_PMCG_E_TLB_WLK_TTD3P (0x81)
133 #define ODY_SMMU_PMCG_E_TLB_WLK_TTDNONE (0x87)
134 #define ODY_SMMU_PMCG_E_TRANSLATION_REQUESTS (1)
135 #define ODY_SMMU_PMCG_E_TTD_READ (4)
136 #define ODY_SMMU_PMCG_E_UTLB_HIT (0x9b)
137
138 /**
139 * Register (NCB32b) smmu#_agbpa
140 *
141 * SMMU Alternate Global Bypass Attribute Register
142 * This register is intended to allow an implementation to apply an additional non
143 * architected attributes or tag to bypassing transactions, for example a traffic
144 * routing identifier.
145 *
146 * If this field is unsupported by an implementation, it is RES0. It is not
147 * intended for this register to be used to further modify existing architected
148 * bypass attributes which are controlled using GPBA.
149 */
150 union ody_smmux_agbpa {
151 uint32_t u;
152 struct ody_smmux_agbpa_s {
153 uint32_t qos : 4;
154 uint32_t reserved_4_31 : 28;
155 } s;
156 /* struct ody_smmux_agbpa_s cn; */
157 };
158 typedef union ody_smmux_agbpa ody_smmux_agbpa_t;
159
160 static inline uint64_t ODY_SMMUX_AGBPA(uint64_t a) __attribute__ ((pure, always_inline));
ODY_SMMUX_AGBPA(uint64_t a)161 static inline uint64_t ODY_SMMUX_AGBPA(uint64_t a)
162 {
163 if (a <= 3)
164 return 0x830000000048ll + 0x1000000000ll * ((a) & 0x3);
165 __ody_csr_fatal("SMMUX_AGBPA", 1, a, 0, 0, 0, 0, 0);
166 }
167
168 #define typedef_ODY_SMMUX_AGBPA(a) ody_smmux_agbpa_t
169 #define bustype_ODY_SMMUX_AGBPA(a) CSR_TYPE_NCB32b
170 #define basename_ODY_SMMUX_AGBPA(a) "SMMUX_AGBPA"
171 #define device_bar_ODY_SMMUX_AGBPA(a) 0x0 /* PF_BAR0 */
172 #define busnum_ODY_SMMUX_AGBPA(a) (a)
173 #define arguments_ODY_SMMUX_AGBPA(a) (a), -1, -1, -1
174
175 /**
176 * Register (NCB32b) smmu#_aidr
177 *
178 * SMMU Auxiliary Identification Register
179 * This register identifies the SMMU architecture version to which the implementation conforms.
180 */
181 union ody_smmux_aidr {
182 uint32_t u;
183 struct ody_smmux_aidr_s {
184 uint32_t archminorrev : 4;
185 uint32_t archmajorrev : 4;
186 uint32_t reserved_8_31 : 24;
187 } s;
188 /* struct ody_smmux_aidr_s cn; */
189 };
190 typedef union ody_smmux_aidr ody_smmux_aidr_t;
191
192 static inline uint64_t ODY_SMMUX_AIDR(uint64_t a) __attribute__ ((pure, always_inline));
ODY_SMMUX_AIDR(uint64_t a)193 static inline uint64_t ODY_SMMUX_AIDR(uint64_t a)
194 {
195 if (a <= 3)
196 return 0x83000000001cll + 0x1000000000ll * ((a) & 0x3);
197 __ody_csr_fatal("SMMUX_AIDR", 1, a, 0, 0, 0, 0, 0);
198 }
199
200 #define typedef_ODY_SMMUX_AIDR(a) ody_smmux_aidr_t
201 #define bustype_ODY_SMMUX_AIDR(a) CSR_TYPE_NCB32b
202 #define basename_ODY_SMMUX_AIDR(a) "SMMUX_AIDR"
203 #define device_bar_ODY_SMMUX_AIDR(a) 0x0 /* PF_BAR0 */
204 #define busnum_ODY_SMMUX_AIDR(a) (a)
205 #define arguments_ODY_SMMUX_AIDR(a) (a), -1, -1, -1
206
207 /**
208 * Register (NCB32b) smmu#_cidr0
209 *
210 * SMMU Component Identification Register 0
211 */
212 union ody_smmux_cidr0 {
213 uint32_t u;
214 struct ody_smmux_cidr0_s {
215 uint32_t preamble : 8;
216 uint32_t reserved_8_31 : 24;
217 } s;
218 /* struct ody_smmux_cidr0_s cn; */
219 };
220 typedef union ody_smmux_cidr0 ody_smmux_cidr0_t;
221
222 static inline uint64_t ODY_SMMUX_CIDR0(uint64_t a) __attribute__ ((pure, always_inline));
ODY_SMMUX_CIDR0(uint64_t a)223 static inline uint64_t ODY_SMMUX_CIDR0(uint64_t a)
224 {
225 if (a <= 3)
226 return 0x830000000ff0ll + 0x1000000000ll * ((a) & 0x3);
227 __ody_csr_fatal("SMMUX_CIDR0", 1, a, 0, 0, 0, 0, 0);
228 }
229
230 #define typedef_ODY_SMMUX_CIDR0(a) ody_smmux_cidr0_t
231 #define bustype_ODY_SMMUX_CIDR0(a) CSR_TYPE_NCB32b
232 #define basename_ODY_SMMUX_CIDR0(a) "SMMUX_CIDR0"
233 #define device_bar_ODY_SMMUX_CIDR0(a) 0x0 /* PF_BAR0 */
234 #define busnum_ODY_SMMUX_CIDR0(a) (a)
235 #define arguments_ODY_SMMUX_CIDR0(a) (a), -1, -1, -1
236
237 /**
238 * Register (NCB32b) smmu#_cidr1
239 *
240 * SMMU Component Identification Register 1
241 */
242 union ody_smmux_cidr1 {
243 uint32_t u;
244 struct ody_smmux_cidr1_s {
245 uint32_t preamble : 4;
246 uint32_t component_class : 4;
247 uint32_t reserved_8_31 : 24;
248 } s;
249 /* struct ody_smmux_cidr1_s cn; */
250 };
251 typedef union ody_smmux_cidr1 ody_smmux_cidr1_t;
252
253 static inline uint64_t ODY_SMMUX_CIDR1(uint64_t a) __attribute__ ((pure, always_inline));
ODY_SMMUX_CIDR1(uint64_t a)254 static inline uint64_t ODY_SMMUX_CIDR1(uint64_t a)
255 {
256 if (a <= 3)
257 return 0x830000000ff4ll + 0x1000000000ll * ((a) & 0x3);
258 __ody_csr_fatal("SMMUX_CIDR1", 1, a, 0, 0, 0, 0, 0);
259 }
260
261 #define typedef_ODY_SMMUX_CIDR1(a) ody_smmux_cidr1_t
262 #define bustype_ODY_SMMUX_CIDR1(a) CSR_TYPE_NCB32b
263 #define basename_ODY_SMMUX_CIDR1(a) "SMMUX_CIDR1"
264 #define device_bar_ODY_SMMUX_CIDR1(a) 0x0 /* PF_BAR0 */
265 #define busnum_ODY_SMMUX_CIDR1(a) (a)
266 #define arguments_ODY_SMMUX_CIDR1(a) (a), -1, -1, -1
267
268 /**
269 * Register (NCB32b) smmu#_cidr2
270 *
271 * SMMU Component Identification Register 2
272 */
273 union ody_smmux_cidr2 {
274 uint32_t u;
275 struct ody_smmux_cidr2_s {
276 uint32_t preamble : 8;
277 uint32_t reserved_8_31 : 24;
278 } s;
279 /* struct ody_smmux_cidr2_s cn; */
280 };
281 typedef union ody_smmux_cidr2 ody_smmux_cidr2_t;
282
283 static inline uint64_t ODY_SMMUX_CIDR2(uint64_t a) __attribute__ ((pure, always_inline));
ODY_SMMUX_CIDR2(uint64_t a)284 static inline uint64_t ODY_SMMUX_CIDR2(uint64_t a)
285 {
286 if (a <= 3)
287 return 0x830000000ff8ll + 0x1000000000ll * ((a) & 0x3);
288 __ody_csr_fatal("SMMUX_CIDR2", 1, a, 0, 0, 0, 0, 0);
289 }
290
291 #define typedef_ODY_SMMUX_CIDR2(a) ody_smmux_cidr2_t
292 #define bustype_ODY_SMMUX_CIDR2(a) CSR_TYPE_NCB32b
293 #define basename_ODY_SMMUX_CIDR2(a) "SMMUX_CIDR2"
294 #define device_bar_ODY_SMMUX_CIDR2(a) 0x0 /* PF_BAR0 */
295 #define busnum_ODY_SMMUX_CIDR2(a) (a)
296 #define arguments_ODY_SMMUX_CIDR2(a) (a), -1, -1, -1
297
298 /**
299 * Register (NCB32b) smmu#_cidr3
300 *
301 * SMMU Component Identification Register 3
302 */
303 union ody_smmux_cidr3 {
304 uint32_t u;
305 struct ody_smmux_cidr3_s {
306 uint32_t preamble : 8;
307 uint32_t reserved_8_31 : 24;
308 } s;
309 /* struct ody_smmux_cidr3_s cn; */
310 };
311 typedef union ody_smmux_cidr3 ody_smmux_cidr3_t;
312
313 static inline uint64_t ODY_SMMUX_CIDR3(uint64_t a) __attribute__ ((pure, always_inline));
ODY_SMMUX_CIDR3(uint64_t a)314 static inline uint64_t ODY_SMMUX_CIDR3(uint64_t a)
315 {
316 if (a <= 3)
317 return 0x830000000ffcll + 0x1000000000ll * ((a) & 0x3);
318 __ody_csr_fatal("SMMUX_CIDR3", 1, a, 0, 0, 0, 0, 0);
319 }
320
321 #define typedef_ODY_SMMUX_CIDR3(a) ody_smmux_cidr3_t
322 #define bustype_ODY_SMMUX_CIDR3(a) CSR_TYPE_NCB32b
323 #define basename_ODY_SMMUX_CIDR3(a) "SMMUX_CIDR3"
324 #define device_bar_ODY_SMMUX_CIDR3(a) 0x0 /* PF_BAR0 */
325 #define busnum_ODY_SMMUX_CIDR3(a) (a)
326 #define arguments_ODY_SMMUX_CIDR3(a) (a), -1, -1, -1
327
328 /**
329 * Register (NCB) smmu#_cmdq_base
330 *
331 * SMMU Command Queue Base Register
332 */
333 union ody_smmux_cmdq_base {
334 uint64_t u;
335 struct ody_smmux_cmdq_base_s {
336 uint64_t log2size : 5;
337 uint64_t addr : 47;
338 uint64_t reserved_52_61 : 10;
339 uint64_t ra : 1;
340 uint64_t reserved_63 : 1;
341 } s;
342 /* struct ody_smmux_cmdq_base_s cn; */
343 };
344 typedef union ody_smmux_cmdq_base ody_smmux_cmdq_base_t;
345
346 static inline uint64_t ODY_SMMUX_CMDQ_BASE(uint64_t a) __attribute__ ((pure, always_inline));
ODY_SMMUX_CMDQ_BASE(uint64_t a)347 static inline uint64_t ODY_SMMUX_CMDQ_BASE(uint64_t a)
348 {
349 if (a <= 3)
350 return 0x830000000090ll + 0x1000000000ll * ((a) & 0x3);
351 __ody_csr_fatal("SMMUX_CMDQ_BASE", 1, a, 0, 0, 0, 0, 0);
352 }
353
354 #define typedef_ODY_SMMUX_CMDQ_BASE(a) ody_smmux_cmdq_base_t
355 #define bustype_ODY_SMMUX_CMDQ_BASE(a) CSR_TYPE_NCB
356 #define basename_ODY_SMMUX_CMDQ_BASE(a) "SMMUX_CMDQ_BASE"
357 #define device_bar_ODY_SMMUX_CMDQ_BASE(a) 0x0 /* PF_BAR0 */
358 #define busnum_ODY_SMMUX_CMDQ_BASE(a) (a)
359 #define arguments_ODY_SMMUX_CMDQ_BASE(a) (a), -1, -1, -1
360
361 /**
362 * Register (NCB32b) smmu#_cmdq_cons
363 *
364 * SMMU Command Queue Consumer Register
365 */
366 union ody_smmux_cmdq_cons {
367 uint32_t u;
368 struct ody_smmux_cmdq_cons_s {
369 uint32_t rd : 20;
370 uint32_t reserved_20_23 : 4;
371 uint32_t errx : 7;
372 uint32_t reserved_31 : 1;
373 } s;
374 /* struct ody_smmux_cmdq_cons_s cn; */
375 };
376 typedef union ody_smmux_cmdq_cons ody_smmux_cmdq_cons_t;
377
378 static inline uint64_t ODY_SMMUX_CMDQ_CONS(uint64_t a) __attribute__ ((pure, always_inline));
ODY_SMMUX_CMDQ_CONS(uint64_t a)379 static inline uint64_t ODY_SMMUX_CMDQ_CONS(uint64_t a)
380 {
381 if (a <= 3)
382 return 0x83000000009cll + 0x1000000000ll * ((a) & 0x3);
383 __ody_csr_fatal("SMMUX_CMDQ_CONS", 1, a, 0, 0, 0, 0, 0);
384 }
385
386 #define typedef_ODY_SMMUX_CMDQ_CONS(a) ody_smmux_cmdq_cons_t
387 #define bustype_ODY_SMMUX_CMDQ_CONS(a) CSR_TYPE_NCB32b
388 #define basename_ODY_SMMUX_CMDQ_CONS(a) "SMMUX_CMDQ_CONS"
389 #define device_bar_ODY_SMMUX_CMDQ_CONS(a) 0x0 /* PF_BAR0 */
390 #define busnum_ODY_SMMUX_CMDQ_CONS(a) (a)
391 #define arguments_ODY_SMMUX_CMDQ_CONS(a) (a), -1, -1, -1
392
393 /**
394 * Register (NCB) smmu#_cmdq_control_page_base#
395 *
396 * SMMU CMDQ Control Page Base Register
397 * Provides information about the Enhanced Command queue interface for the SMMU Non-
398 * secure programming interface.
399 */
400 union ody_smmux_cmdq_control_page_basex {
401 uint64_t u;
402 struct ody_smmux_cmdq_control_page_basex_s {
403 uint64_t cmdq_control_page_preset : 1;
404 uint64_t cmdqgs : 2;
405 uint64_t reserved_3_15 : 13;
406 uint64_t addr : 36;
407 uint64_t reserved_52_63 : 12;
408 } s;
409 /* struct ody_smmux_cmdq_control_page_basex_s cn; */
410 };
411 typedef union ody_smmux_cmdq_control_page_basex ody_smmux_cmdq_control_page_basex_t;
412
413 static inline uint64_t ODY_SMMUX_CMDQ_CONTROL_PAGE_BASEX(uint64_t a, uint64_t b) __attribute__ ((pure, always_inline));
ODY_SMMUX_CMDQ_CONTROL_PAGE_BASEX(uint64_t a,uint64_t b)414 static inline uint64_t ODY_SMMUX_CMDQ_CONTROL_PAGE_BASEX(uint64_t a, uint64_t b)
415 {
416 if ((a <= 3) && (b == 0))
417 return 0x830000004000ll + 0x1000000000ll * ((a) & 0x3);
418 __ody_csr_fatal("SMMUX_CMDQ_CONTROL_PAGE_BASEX", 2, a, b, 0, 0, 0, 0);
419 }
420
421 #define typedef_ODY_SMMUX_CMDQ_CONTROL_PAGE_BASEX(a, b) ody_smmux_cmdq_control_page_basex_t
422 #define bustype_ODY_SMMUX_CMDQ_CONTROL_PAGE_BASEX(a, b) CSR_TYPE_NCB
423 #define basename_ODY_SMMUX_CMDQ_CONTROL_PAGE_BASEX(a, b) "SMMUX_CMDQ_CONTROL_PAGE_BASEX"
424 #define device_bar_ODY_SMMUX_CMDQ_CONTROL_PAGE_BASEX(a, b) 0x0 /* PF_BAR0 */
425 #define busnum_ODY_SMMUX_CMDQ_CONTROL_PAGE_BASEX(a, b) (a)
426 #define arguments_ODY_SMMUX_CMDQ_CONTROL_PAGE_BASEX(a, b) (a), (b), -1, -1
427
428 /**
429 * Register (NCB32b) smmu#_cmdq_control_page_cfg#
430 *
431 * SMMU CMDQ Control Page Configuration Register
432 * Control for Enhanced Command queue interface for the SMMU Non-secure programming interface.
433 */
434 union ody_smmux_cmdq_control_page_cfgx {
435 uint32_t u;
436 struct ody_smmux_cmdq_control_page_cfgx_s {
437 uint32_t en : 1;
438 uint32_t reserved_1_31 : 31;
439 } s;
440 /* struct ody_smmux_cmdq_control_page_cfgx_s cn; */
441 };
442 typedef union ody_smmux_cmdq_control_page_cfgx ody_smmux_cmdq_control_page_cfgx_t;
443
444 static inline uint64_t ODY_SMMUX_CMDQ_CONTROL_PAGE_CFGX(uint64_t a, uint64_t b) __attribute__ ((pure, always_inline));
ODY_SMMUX_CMDQ_CONTROL_PAGE_CFGX(uint64_t a,uint64_t b)445 static inline uint64_t ODY_SMMUX_CMDQ_CONTROL_PAGE_CFGX(uint64_t a, uint64_t b)
446 {
447 if ((a <= 3) && (b == 0))
448 return 0x830000004008ll + 0x1000000000ll * ((a) & 0x3);
449 __ody_csr_fatal("SMMUX_CMDQ_CONTROL_PAGE_CFGX", 2, a, b, 0, 0, 0, 0);
450 }
451
452 #define typedef_ODY_SMMUX_CMDQ_CONTROL_PAGE_CFGX(a, b) ody_smmux_cmdq_control_page_cfgx_t
453 #define bustype_ODY_SMMUX_CMDQ_CONTROL_PAGE_CFGX(a, b) CSR_TYPE_NCB32b
454 #define basename_ODY_SMMUX_CMDQ_CONTROL_PAGE_CFGX(a, b) "SMMUX_CMDQ_CONTROL_PAGE_CFGX"
455 #define device_bar_ODY_SMMUX_CMDQ_CONTROL_PAGE_CFGX(a, b) 0x0 /* PF_BAR0 */
456 #define busnum_ODY_SMMUX_CMDQ_CONTROL_PAGE_CFGX(a, b) (a)
457 #define arguments_ODY_SMMUX_CMDQ_CONTROL_PAGE_CFGX(a, b) (a), (b), -1, -1
458
459 /**
460 * Register (NCB32b) smmu#_cmdq_control_page_status#
461 *
462 * SMMU CMDQ Control Page Status Register
463 * Status of Enhanced Command queue interface for the SMMU Non-secure programming interface.
464 */
465 union ody_smmux_cmdq_control_page_statusx {
466 uint32_t u;
467 struct ody_smmux_cmdq_control_page_statusx_s {
468 uint32_t enack : 1;
469 uint32_t reserved_1_31 : 31;
470 } s;
471 /* struct ody_smmux_cmdq_control_page_statusx_s cn; */
472 };
473 typedef union ody_smmux_cmdq_control_page_statusx ody_smmux_cmdq_control_page_statusx_t;
474
475 static inline uint64_t ODY_SMMUX_CMDQ_CONTROL_PAGE_STATUSX(uint64_t a, uint64_t b) __attribute__ ((pure, always_inline));
ODY_SMMUX_CMDQ_CONTROL_PAGE_STATUSX(uint64_t a,uint64_t b)476 static inline uint64_t ODY_SMMUX_CMDQ_CONTROL_PAGE_STATUSX(uint64_t a, uint64_t b)
477 {
478 if ((a <= 3) && (b == 0))
479 return 0x83000000400cll + 0x1000000000ll * ((a) & 0x3);
480 __ody_csr_fatal("SMMUX_CMDQ_CONTROL_PAGE_STATUSX", 2, a, b, 0, 0, 0, 0);
481 }
482
483 #define typedef_ODY_SMMUX_CMDQ_CONTROL_PAGE_STATUSX(a, b) ody_smmux_cmdq_control_page_statusx_t
484 #define bustype_ODY_SMMUX_CMDQ_CONTROL_PAGE_STATUSX(a, b) CSR_TYPE_NCB32b
485 #define basename_ODY_SMMUX_CMDQ_CONTROL_PAGE_STATUSX(a, b) "SMMUX_CMDQ_CONTROL_PAGE_STATUSX"
486 #define device_bar_ODY_SMMUX_CMDQ_CONTROL_PAGE_STATUSX(a, b) 0x0 /* PF_BAR0 */
487 #define busnum_ODY_SMMUX_CMDQ_CONTROL_PAGE_STATUSX(a, b) (a)
488 #define arguments_ODY_SMMUX_CMDQ_CONTROL_PAGE_STATUSX(a, b) (a), (b), -1, -1
489
490 /**
491 * Register (NCB32b) smmu#_cmdq_prod
492 *
493 * SMMU Command Queue Producer Register
494 */
495 union ody_smmux_cmdq_prod {
496 uint32_t u;
497 struct ody_smmux_cmdq_prod_s {
498 uint32_t wr : 20;
499 uint32_t reserved_20_31 : 12;
500 } s;
501 /* struct ody_smmux_cmdq_prod_s cn; */
502 };
503 typedef union ody_smmux_cmdq_prod ody_smmux_cmdq_prod_t;
504
505 static inline uint64_t ODY_SMMUX_CMDQ_PROD(uint64_t a) __attribute__ ((pure, always_inline));
ODY_SMMUX_CMDQ_PROD(uint64_t a)506 static inline uint64_t ODY_SMMUX_CMDQ_PROD(uint64_t a)
507 {
508 if (a <= 3)
509 return 0x830000000098ll + 0x1000000000ll * ((a) & 0x3);
510 __ody_csr_fatal("SMMUX_CMDQ_PROD", 1, a, 0, 0, 0, 0, 0);
511 }
512
513 #define typedef_ODY_SMMUX_CMDQ_PROD(a) ody_smmux_cmdq_prod_t
514 #define bustype_ODY_SMMUX_CMDQ_PROD(a) CSR_TYPE_NCB32b
515 #define basename_ODY_SMMUX_CMDQ_PROD(a) "SMMUX_CMDQ_PROD"
516 #define device_bar_ODY_SMMUX_CMDQ_PROD(a) 0x0 /* PF_BAR0 */
517 #define busnum_ODY_SMMUX_CMDQ_PROD(a) (a)
518 #define arguments_ODY_SMMUX_CMDQ_PROD(a) (a), -1, -1, -1
519
520 /**
521 * Register (NCB32b) smmu#_cr0
522 *
523 * SMMU Control 0 Register
524 * Each field in this register has a corresponding field in SMMU()_CR0ACK. An
525 * individual field is said to be "updated" after the value of the field observed in
526 * SMMU()_CR0ACK matches the value that was written to the field in
527 * SMMU()_CR0. Reserved fields in SMMU()_CR0 are not reflected in SMMU()_CR0ACK. To
528 * ensure a field change has taken effect, software must poll the equivalent field in
529 * SMMU()_CR0ACK after writing the field in this register.
530 *
531 * Each field in this register is independent and unaffected by ongoing update
532 * procedures of adjacent fields.
533 *
534 * Update of a field must complete in reasonable time, but is not required to occur
535 * immediately. The update process may have side effects which are guaranteed to be
536 * complete by the time update completes. See below for details of any side effects.
537 *
538 * A field that has been written is considered to be in a transitional state until
539 * update has completed. Anything depending on its value observes the old value until
540 * the new value takes effect at an unpredictable point before update completes
541 * whereupon the new value is guaranteed to be used, therefore:
542 *
543 * A written field cannot be assumed to have taken the new value until update completes.
544 *
545 * A written field cannot be assumed not to have taken the new value after the write is
546 * observed by the SMMU.
547 *
548 * Anywhere behavior depending on a field value (for example, a rule of the form "REG
549 * must only be changed if SMMUEN=0"), it is the post-update value that is referred
550 * to. In this example, the rule would be broken were REG to be changed after the point
551 * that SMMU()_(S_)SMMUEN has been written to one even if update has not
552 * completed. Similarly, a field that has been written and is still in a transitional
553 * state (pre-update completion) must be considered to still have the old value for the
554 * purposes of constraints the old value places upon software. For example,
555 * SMMU()_CMDQ_CONS must not be written when CMDQEN=1, or during an as -yet incomplete
556 * transition to 0 (as [CMDQEN] must still be considered to be one).
557 *
558 * After altering a field value, software must not alter the field's value again before
559 * the initial alteration's update is complete. Behavior on doing so is constrained
560 * unpredictable and one of the following occurs: The new value is stored and the
561 * update completes with any of the values written.
562 *
563 * The effective field value in use might not match that read back from this register.
564 * The new value is ignored and update completes using the first value (reflected in
565 * SMMU()_CR0ACK). Cease update if the new value is the same as the original value
566 * before the first write. This means no update side effects would occur.
567 *
568 * A write with the same value (i.e. not altered) is permitted; this might occur when
569 * altering an unrelated field in the same register whilst an earlier field update is
570 * in process.
571 */
572 union ody_smmux_cr0 {
573 uint32_t u;
574 struct ody_smmux_cr0_s {
575 uint32_t smmuen : 1;
576 uint32_t priqen : 1;
577 uint32_t eventqen : 1;
578 uint32_t cmdqen : 1;
579 uint32_t atschk : 1;
580 uint32_t reserved_5 : 1;
581 uint32_t vmw : 3;
582 uint32_t reserved_9_31 : 23;
583 } s;
584 /* struct ody_smmux_cr0_s cn; */
585 };
586 typedef union ody_smmux_cr0 ody_smmux_cr0_t;
587
588 static inline uint64_t ODY_SMMUX_CR0(uint64_t a) __attribute__ ((pure, always_inline));
ODY_SMMUX_CR0(uint64_t a)589 static inline uint64_t ODY_SMMUX_CR0(uint64_t a)
590 {
591 if (a <= 3)
592 return 0x830000000020ll + 0x1000000000ll * ((a) & 0x3);
593 __ody_csr_fatal("SMMUX_CR0", 1, a, 0, 0, 0, 0, 0);
594 }
595
596 #define typedef_ODY_SMMUX_CR0(a) ody_smmux_cr0_t
597 #define bustype_ODY_SMMUX_CR0(a) CSR_TYPE_NCB32b
598 #define basename_ODY_SMMUX_CR0(a) "SMMUX_CR0"
599 #define device_bar_ODY_SMMUX_CR0(a) 0x0 /* PF_BAR0 */
600 #define busnum_ODY_SMMUX_CR0(a) (a)
601 #define arguments_ODY_SMMUX_CR0(a) (a), -1, -1, -1
602
603 /**
604 * Register (NCB32b) smmu#_cr0ack
605 *
606 * SMMU Control 0 Acknowledgement Register
607 * This register is a read-only copy of SMMU()_CR0.
608 */
609 union ody_smmux_cr0ack {
610 uint32_t u;
611 struct ody_smmux_cr0ack_s {
612 uint32_t smmuen : 1;
613 uint32_t priqen : 1;
614 uint32_t eventqen : 1;
615 uint32_t cmdqen : 1;
616 uint32_t atschk : 1;
617 uint32_t reserved_5 : 1;
618 uint32_t vmw : 3;
619 uint32_t reserved_9_31 : 23;
620 } s;
621 /* struct ody_smmux_cr0ack_s cn; */
622 };
623 typedef union ody_smmux_cr0ack ody_smmux_cr0ack_t;
624
625 static inline uint64_t ODY_SMMUX_CR0ACK(uint64_t a) __attribute__ ((pure, always_inline));
ODY_SMMUX_CR0ACK(uint64_t a)626 static inline uint64_t ODY_SMMUX_CR0ACK(uint64_t a)
627 {
628 if (a <= 3)
629 return 0x830000000024ll + 0x1000000000ll * ((a) & 0x3);
630 __ody_csr_fatal("SMMUX_CR0ACK", 1, a, 0, 0, 0, 0, 0);
631 }
632
633 #define typedef_ODY_SMMUX_CR0ACK(a) ody_smmux_cr0ack_t
634 #define bustype_ODY_SMMUX_CR0ACK(a) CSR_TYPE_NCB32b
635 #define basename_ODY_SMMUX_CR0ACK(a) "SMMUX_CR0ACK"
636 #define device_bar_ODY_SMMUX_CR0ACK(a) 0x0 /* PF_BAR0 */
637 #define busnum_ODY_SMMUX_CR0ACK(a) (a)
638 #define arguments_ODY_SMMUX_CR0ACK(a) (a), -1, -1, -1
639
640 /**
641 * Register (NCB32b) smmu#_cr1
642 *
643 * SMMU Control 1 Register
644 */
645 union ody_smmux_cr1 {
646 uint32_t u;
647 struct ody_smmux_cr1_s {
648 uint32_t queue_ic : 2;
649 uint32_t queue_oc : 2;
650 uint32_t queue_sh : 2;
651 uint32_t table_ic : 2;
652 uint32_t table_oc : 2;
653 uint32_t table_sh : 2;
654 uint32_t reserved_12_31 : 20;
655 } s;
656 /* struct ody_smmux_cr1_s cn; */
657 };
658 typedef union ody_smmux_cr1 ody_smmux_cr1_t;
659
660 static inline uint64_t ODY_SMMUX_CR1(uint64_t a) __attribute__ ((pure, always_inline));
ODY_SMMUX_CR1(uint64_t a)661 static inline uint64_t ODY_SMMUX_CR1(uint64_t a)
662 {
663 if (a <= 3)
664 return 0x830000000028ll + 0x1000000000ll * ((a) & 0x3);
665 __ody_csr_fatal("SMMUX_CR1", 1, a, 0, 0, 0, 0, 0);
666 }
667
668 #define typedef_ODY_SMMUX_CR1(a) ody_smmux_cr1_t
669 #define bustype_ODY_SMMUX_CR1(a) CSR_TYPE_NCB32b
670 #define basename_ODY_SMMUX_CR1(a) "SMMUX_CR1"
671 #define device_bar_ODY_SMMUX_CR1(a) 0x0 /* PF_BAR0 */
672 #define busnum_ODY_SMMUX_CR1(a) (a)
673 #define arguments_ODY_SMMUX_CR1(a) (a), -1, -1, -1
674
675 /**
676 * Register (NCB32b) smmu#_cr2
677 *
678 * SMMU Control 2 Register
679 */
680 union ody_smmux_cr2 {
681 uint32_t u;
682 struct ody_smmux_cr2_s {
683 uint32_t e2h : 1;
684 uint32_t recinvsid : 1;
685 uint32_t ptm : 1;
686 uint32_t reserved_3_31 : 29;
687 } s;
688 /* struct ody_smmux_cr2_s cn; */
689 };
690 typedef union ody_smmux_cr2 ody_smmux_cr2_t;
691
692 static inline uint64_t ODY_SMMUX_CR2(uint64_t a) __attribute__ ((pure, always_inline));
ODY_SMMUX_CR2(uint64_t a)693 static inline uint64_t ODY_SMMUX_CR2(uint64_t a)
694 {
695 if (a <= 3)
696 return 0x83000000002cll + 0x1000000000ll * ((a) & 0x3);
697 __ody_csr_fatal("SMMUX_CR2", 1, a, 0, 0, 0, 0, 0);
698 }
699
700 #define typedef_ODY_SMMUX_CR2(a) ody_smmux_cr2_t
701 #define bustype_ODY_SMMUX_CR2(a) CSR_TYPE_NCB32b
702 #define basename_ODY_SMMUX_CR2(a) "SMMUX_CR2"
703 #define device_bar_ODY_SMMUX_CR2(a) 0x0 /* PF_BAR0 */
704 #define busnum_ODY_SMMUX_CR2(a) (a)
705 #define arguments_ODY_SMMUX_CR2(a) (a), -1, -1, -1
706
707 /**
708 * Register (NCB) smmu#_ecmdq_base#
709 *
710 * SMMU Enhanced Command Queue Base Register
711 * Configuration of the Command queue base address.
712 */
713 union ody_smmux_ecmdq_basex {
714 uint64_t u;
715 struct ody_smmux_ecmdq_basex_s {
716 uint64_t log2size : 5;
717 uint64_t addr : 47;
718 uint64_t reserved_52_61 : 10;
719 uint64_t ra : 1;
720 uint64_t reserved_63 : 1;
721 } s;
722 /* struct ody_smmux_ecmdq_basex_s cn; */
723 };
724 typedef union ody_smmux_ecmdq_basex ody_smmux_ecmdq_basex_t;
725
726 static inline uint64_t ODY_SMMUX_ECMDQ_BASEX(uint64_t a, uint64_t b) __attribute__ ((pure, always_inline));
ODY_SMMUX_ECMDQ_BASEX(uint64_t a,uint64_t b)727 static inline uint64_t ODY_SMMUX_ECMDQ_BASEX(uint64_t a, uint64_t b)
728 {
729 if ((a <= 3) && (b <= 127))
730 return 0x830000180000ll + 0x1000000000ll * ((a) & 0x3) + 0x200ll * ((b) & 0x7f);
731 __ody_csr_fatal("SMMUX_ECMDQ_BASEX", 2, a, b, 0, 0, 0, 0);
732 }
733
734 #define typedef_ODY_SMMUX_ECMDQ_BASEX(a, b) ody_smmux_ecmdq_basex_t
735 #define bustype_ODY_SMMUX_ECMDQ_BASEX(a, b) CSR_TYPE_NCB
736 #define basename_ODY_SMMUX_ECMDQ_BASEX(a, b) "SMMUX_ECMDQ_BASEX"
737 #define device_bar_ODY_SMMUX_ECMDQ_BASEX(a, b) 0x0 /* PF_BAR0 */
738 #define busnum_ODY_SMMUX_ECMDQ_BASEX(a, b) (a)
739 #define arguments_ODY_SMMUX_ECMDQ_BASEX(a, b) (a), (b), -1, -1
740
741 /**
742 * Register (NCB32b) smmu#_ecmdq_cons#
743 *
744 * SMMU Enhanced Command Queue Consumer Register
745 * Command queue consumer read index.
746 */
747 union ody_smmux_ecmdq_consx {
748 uint32_t u;
749 struct ody_smmux_ecmdq_consx_s {
750 uint32_t rd : 20;
751 uint32_t reserved_20_22 : 3;
752 uint32_t errx : 1;
753 uint32_t err_reason : 3;
754 uint32_t reserved_27_30 : 4;
755 uint32_t enack : 1;
756 } s;
757 /* struct ody_smmux_ecmdq_consx_s cn; */
758 };
759 typedef union ody_smmux_ecmdq_consx ody_smmux_ecmdq_consx_t;
760
761 static inline uint64_t ODY_SMMUX_ECMDQ_CONSX(uint64_t a, uint64_t b) __attribute__ ((pure, always_inline));
ODY_SMMUX_ECMDQ_CONSX(uint64_t a,uint64_t b)762 static inline uint64_t ODY_SMMUX_ECMDQ_CONSX(uint64_t a, uint64_t b)
763 {
764 if ((a <= 3) && (b <= 127))
765 return 0x83000018000cll + 0x1000000000ll * ((a) & 0x3) + 0x200ll * ((b) & 0x7f);
766 __ody_csr_fatal("SMMUX_ECMDQ_CONSX", 2, a, b, 0, 0, 0, 0);
767 }
768
769 #define typedef_ODY_SMMUX_ECMDQ_CONSX(a, b) ody_smmux_ecmdq_consx_t
770 #define bustype_ODY_SMMUX_ECMDQ_CONSX(a, b) CSR_TYPE_NCB32b
771 #define basename_ODY_SMMUX_ECMDQ_CONSX(a, b) "SMMUX_ECMDQ_CONSX"
772 #define device_bar_ODY_SMMUX_ECMDQ_CONSX(a, b) 0x0 /* PF_BAR0 */
773 #define busnum_ODY_SMMUX_ECMDQ_CONSX(a, b) (a)
774 #define arguments_ODY_SMMUX_ECMDQ_CONSX(a, b) (a), (b), -1, -1
775
776 /**
777 * Register (NCB32b) smmu#_ecmdq_prod#
778 *
779 * SMMU Enhanced Command Queue Producer Register
780 * Allows Command queue producer to update the write index.
781 */
782 union ody_smmux_ecmdq_prodx {
783 uint32_t u;
784 struct ody_smmux_ecmdq_prodx_s {
785 uint32_t wr : 20;
786 uint32_t reserved_20_22 : 3;
787 uint32_t errack : 1;
788 uint32_t reserved_24_30 : 7;
789 uint32_t en : 1;
790 } s;
791 /* struct ody_smmux_ecmdq_prodx_s cn; */
792 };
793 typedef union ody_smmux_ecmdq_prodx ody_smmux_ecmdq_prodx_t;
794
795 static inline uint64_t ODY_SMMUX_ECMDQ_PRODX(uint64_t a, uint64_t b) __attribute__ ((pure, always_inline));
ODY_SMMUX_ECMDQ_PRODX(uint64_t a,uint64_t b)796 static inline uint64_t ODY_SMMUX_ECMDQ_PRODX(uint64_t a, uint64_t b)
797 {
798 if ((a <= 3) && (b <= 127))
799 return 0x830000180008ll + 0x1000000000ll * ((a) & 0x3) + 0x200ll * ((b) & 0x7f);
800 __ody_csr_fatal("SMMUX_ECMDQ_PRODX", 2, a, b, 0, 0, 0, 0);
801 }
802
803 #define typedef_ODY_SMMUX_ECMDQ_PRODX(a, b) ody_smmux_ecmdq_prodx_t
804 #define bustype_ODY_SMMUX_ECMDQ_PRODX(a, b) CSR_TYPE_NCB32b
805 #define basename_ODY_SMMUX_ECMDQ_PRODX(a, b) "SMMUX_ECMDQ_PRODX"
806 #define device_bar_ODY_SMMUX_ECMDQ_PRODX(a, b) 0x0 /* PF_BAR0 */
807 #define busnum_ODY_SMMUX_ECMDQ_PRODX(a, b) (a)
808 #define arguments_ODY_SMMUX_ECMDQ_PRODX(a, b) (a), (b), -1, -1
809
810 /**
811 * Register (NCB) smmu#_eventq_base
812 *
813 * SMMU Event Queue Base Register
814 */
815 union ody_smmux_eventq_base {
816 uint64_t u;
817 struct ody_smmux_eventq_base_s {
818 uint64_t log2size : 5;
819 uint64_t addr : 47;
820 uint64_t reserved_52_61 : 10;
821 uint64_t wa : 1;
822 uint64_t reserved_63 : 1;
823 } s;
824 /* struct ody_smmux_eventq_base_s cn; */
825 };
826 typedef union ody_smmux_eventq_base ody_smmux_eventq_base_t;
827
828 static inline uint64_t ODY_SMMUX_EVENTQ_BASE(uint64_t a) __attribute__ ((pure, always_inline));
ODY_SMMUX_EVENTQ_BASE(uint64_t a)829 static inline uint64_t ODY_SMMUX_EVENTQ_BASE(uint64_t a)
830 {
831 if (a <= 3)
832 return 0x8300000000a0ll + 0x1000000000ll * ((a) & 0x3);
833 __ody_csr_fatal("SMMUX_EVENTQ_BASE", 1, a, 0, 0, 0, 0, 0);
834 }
835
836 #define typedef_ODY_SMMUX_EVENTQ_BASE(a) ody_smmux_eventq_base_t
837 #define bustype_ODY_SMMUX_EVENTQ_BASE(a) CSR_TYPE_NCB
838 #define basename_ODY_SMMUX_EVENTQ_BASE(a) "SMMUX_EVENTQ_BASE"
839 #define device_bar_ODY_SMMUX_EVENTQ_BASE(a) 0x0 /* PF_BAR0 */
840 #define busnum_ODY_SMMUX_EVENTQ_BASE(a) (a)
841 #define arguments_ODY_SMMUX_EVENTQ_BASE(a) (a), -1, -1, -1
842
843 /**
844 * Register (NCB32b) smmu#_eventq_cons
845 *
846 * SMMU Event Queue Consumer Register
847 */
848 union ody_smmux_eventq_cons {
849 uint32_t u;
850 struct ody_smmux_eventq_cons_s {
851 uint32_t rd : 20;
852 uint32_t reserved_20_30 : 11;
853 uint32_t ovackflg : 1;
854 } s;
855 /* struct ody_smmux_eventq_cons_s cn; */
856 };
857 typedef union ody_smmux_eventq_cons ody_smmux_eventq_cons_t;
858
859 static inline uint64_t ODY_SMMUX_EVENTQ_CONS(uint64_t a) __attribute__ ((pure, always_inline));
ODY_SMMUX_EVENTQ_CONS(uint64_t a)860 static inline uint64_t ODY_SMMUX_EVENTQ_CONS(uint64_t a)
861 {
862 if (a <= 3)
863 return 0x8300000100acll + 0x1000000000ll * ((a) & 0x3);
864 __ody_csr_fatal("SMMUX_EVENTQ_CONS", 1, a, 0, 0, 0, 0, 0);
865 }
866
867 #define typedef_ODY_SMMUX_EVENTQ_CONS(a) ody_smmux_eventq_cons_t
868 #define bustype_ODY_SMMUX_EVENTQ_CONS(a) CSR_TYPE_NCB32b
869 #define basename_ODY_SMMUX_EVENTQ_CONS(a) "SMMUX_EVENTQ_CONS"
870 #define device_bar_ODY_SMMUX_EVENTQ_CONS(a) 0x0 /* PF_BAR0 */
871 #define busnum_ODY_SMMUX_EVENTQ_CONS(a) (a)
872 #define arguments_ODY_SMMUX_EVENTQ_CONS(a) (a), -1, -1, -1
873
874 /**
875 * Register (NCB) smmu#_eventq_irq_cfg0
876 *
877 * SMMU Event Queue Interrupt Configuration 0 Register
878 */
879 union ody_smmux_eventq_irq_cfg0 {
880 uint64_t u;
881 struct ody_smmux_eventq_irq_cfg0_s {
882 uint64_t reserved_0_1 : 2;
883 uint64_t addr : 50;
884 uint64_t reserved_52_63 : 12;
885 } s;
886 /* struct ody_smmux_eventq_irq_cfg0_s cn; */
887 };
888 typedef union ody_smmux_eventq_irq_cfg0 ody_smmux_eventq_irq_cfg0_t;
889
890 static inline uint64_t ODY_SMMUX_EVENTQ_IRQ_CFG0(uint64_t a) __attribute__ ((pure, always_inline));
ODY_SMMUX_EVENTQ_IRQ_CFG0(uint64_t a)891 static inline uint64_t ODY_SMMUX_EVENTQ_IRQ_CFG0(uint64_t a)
892 {
893 if (a <= 3)
894 return 0x8300000000b0ll + 0x1000000000ll * ((a) & 0x3);
895 __ody_csr_fatal("SMMUX_EVENTQ_IRQ_CFG0", 1, a, 0, 0, 0, 0, 0);
896 }
897
898 #define typedef_ODY_SMMUX_EVENTQ_IRQ_CFG0(a) ody_smmux_eventq_irq_cfg0_t
899 #define bustype_ODY_SMMUX_EVENTQ_IRQ_CFG0(a) CSR_TYPE_NCB
900 #define basename_ODY_SMMUX_EVENTQ_IRQ_CFG0(a) "SMMUX_EVENTQ_IRQ_CFG0"
901 #define device_bar_ODY_SMMUX_EVENTQ_IRQ_CFG0(a) 0x0 /* PF_BAR0 */
902 #define busnum_ODY_SMMUX_EVENTQ_IRQ_CFG0(a) (a)
903 #define arguments_ODY_SMMUX_EVENTQ_IRQ_CFG0(a) (a), -1, -1, -1
904
905 /**
906 * Register (NCB32b) smmu#_eventq_irq_cfg1
907 *
908 * SMMU Event Queue Interrupt Configuration 1 Register
909 */
910 union ody_smmux_eventq_irq_cfg1 {
911 uint32_t u;
912 struct ody_smmux_eventq_irq_cfg1_s {
913 uint32_t data : 32;
914 } s;
915 /* struct ody_smmux_eventq_irq_cfg1_s cn; */
916 };
917 typedef union ody_smmux_eventq_irq_cfg1 ody_smmux_eventq_irq_cfg1_t;
918
919 static inline uint64_t ODY_SMMUX_EVENTQ_IRQ_CFG1(uint64_t a) __attribute__ ((pure, always_inline));
ODY_SMMUX_EVENTQ_IRQ_CFG1(uint64_t a)920 static inline uint64_t ODY_SMMUX_EVENTQ_IRQ_CFG1(uint64_t a)
921 {
922 if (a <= 3)
923 return 0x8300000000b8ll + 0x1000000000ll * ((a) & 0x3);
924 __ody_csr_fatal("SMMUX_EVENTQ_IRQ_CFG1", 1, a, 0, 0, 0, 0, 0);
925 }
926
927 #define typedef_ODY_SMMUX_EVENTQ_IRQ_CFG1(a) ody_smmux_eventq_irq_cfg1_t
928 #define bustype_ODY_SMMUX_EVENTQ_IRQ_CFG1(a) CSR_TYPE_NCB32b
929 #define basename_ODY_SMMUX_EVENTQ_IRQ_CFG1(a) "SMMUX_EVENTQ_IRQ_CFG1"
930 #define device_bar_ODY_SMMUX_EVENTQ_IRQ_CFG1(a) 0x0 /* PF_BAR0 */
931 #define busnum_ODY_SMMUX_EVENTQ_IRQ_CFG1(a) (a)
932 #define arguments_ODY_SMMUX_EVENTQ_IRQ_CFG1(a) (a), -1, -1, -1
933
934 /**
935 * Register (NCB32b) smmu#_eventq_irq_cfg2
936 *
937 * SMMU Event Queue Interrupt Configuration 2 Register
938 */
939 union ody_smmux_eventq_irq_cfg2 {
940 uint32_t u;
941 struct ody_smmux_eventq_irq_cfg2_s {
942 uint32_t memattr : 4;
943 uint32_t sh : 2;
944 uint32_t reserved_6_31 : 26;
945 } s;
946 /* struct ody_smmux_eventq_irq_cfg2_s cn; */
947 };
948 typedef union ody_smmux_eventq_irq_cfg2 ody_smmux_eventq_irq_cfg2_t;
949
950 static inline uint64_t ODY_SMMUX_EVENTQ_IRQ_CFG2(uint64_t a) __attribute__ ((pure, always_inline));
ODY_SMMUX_EVENTQ_IRQ_CFG2(uint64_t a)951 static inline uint64_t ODY_SMMUX_EVENTQ_IRQ_CFG2(uint64_t a)
952 {
953 if (a <= 3)
954 return 0x8300000000bcll + 0x1000000000ll * ((a) & 0x3);
955 __ody_csr_fatal("SMMUX_EVENTQ_IRQ_CFG2", 1, a, 0, 0, 0, 0, 0);
956 }
957
958 #define typedef_ODY_SMMUX_EVENTQ_IRQ_CFG2(a) ody_smmux_eventq_irq_cfg2_t
959 #define bustype_ODY_SMMUX_EVENTQ_IRQ_CFG2(a) CSR_TYPE_NCB32b
960 #define basename_ODY_SMMUX_EVENTQ_IRQ_CFG2(a) "SMMUX_EVENTQ_IRQ_CFG2"
961 #define device_bar_ODY_SMMUX_EVENTQ_IRQ_CFG2(a) 0x0 /* PF_BAR0 */
962 #define busnum_ODY_SMMUX_EVENTQ_IRQ_CFG2(a) (a)
963 #define arguments_ODY_SMMUX_EVENTQ_IRQ_CFG2(a) (a), -1, -1, -1
964
965 /**
966 * Register (NCB32b) smmu#_eventq_prod
967 *
968 * SMMU Event Queue Producer Register
969 */
970 union ody_smmux_eventq_prod {
971 uint32_t u;
972 struct ody_smmux_eventq_prod_s {
973 uint32_t wr : 20;
974 uint32_t reserved_20_30 : 11;
975 uint32_t ovflg : 1;
976 } s;
977 /* struct ody_smmux_eventq_prod_s cn; */
978 };
979 typedef union ody_smmux_eventq_prod ody_smmux_eventq_prod_t;
980
981 static inline uint64_t ODY_SMMUX_EVENTQ_PROD(uint64_t a) __attribute__ ((pure, always_inline));
ODY_SMMUX_EVENTQ_PROD(uint64_t a)982 static inline uint64_t ODY_SMMUX_EVENTQ_PROD(uint64_t a)
983 {
984 if (a <= 3)
985 return 0x8300000100a8ll + 0x1000000000ll * ((a) & 0x3);
986 __ody_csr_fatal("SMMUX_EVENTQ_PROD", 1, a, 0, 0, 0, 0, 0);
987 }
988
989 #define typedef_ODY_SMMUX_EVENTQ_PROD(a) ody_smmux_eventq_prod_t
990 #define bustype_ODY_SMMUX_EVENTQ_PROD(a) CSR_TYPE_NCB32b
991 #define basename_ODY_SMMUX_EVENTQ_PROD(a) "SMMUX_EVENTQ_PROD"
992 #define device_bar_ODY_SMMUX_EVENTQ_PROD(a) 0x0 /* PF_BAR0 */
993 #define busnum_ODY_SMMUX_EVENTQ_PROD(a) (a)
994 #define arguments_ODY_SMMUX_EVENTQ_PROD(a) (a), -1, -1, -1
995
996 /**
997 * Register (NCB) smmu#_gatos_addr
998 *
999 * SMMU GATOS Address Register
1000 */
1001 union ody_smmux_gatos_addr {
1002 uint64_t u;
1003 struct ody_smmux_gatos_addr_s {
1004 uint64_t reserved_0_3 : 4;
1005 uint64_t ns_ind : 1;
1006 uint64_t reserved_5 : 1;
1007 uint64_t httui : 1;
1008 uint64_t ind : 1;
1009 uint64_t rnw : 1;
1010 uint64_t pnu : 1;
1011 uint64_t rtype : 2;
1012 uint64_t addr : 52;
1013 } s;
1014 /* struct ody_smmux_gatos_addr_s cn; */
1015 };
1016 typedef union ody_smmux_gatos_addr ody_smmux_gatos_addr_t;
1017
1018 static inline uint64_t ODY_SMMUX_GATOS_ADDR(uint64_t a) __attribute__ ((pure, always_inline));
ODY_SMMUX_GATOS_ADDR(uint64_t a)1019 static inline uint64_t ODY_SMMUX_GATOS_ADDR(uint64_t a)
1020 {
1021 if (a <= 3)
1022 return 0x830000000110ll + 0x1000000000ll * ((a) & 0x3);
1023 __ody_csr_fatal("SMMUX_GATOS_ADDR", 1, a, 0, 0, 0, 0, 0);
1024 }
1025
1026 #define typedef_ODY_SMMUX_GATOS_ADDR(a) ody_smmux_gatos_addr_t
1027 #define bustype_ODY_SMMUX_GATOS_ADDR(a) CSR_TYPE_NCB
1028 #define basename_ODY_SMMUX_GATOS_ADDR(a) "SMMUX_GATOS_ADDR"
1029 #define device_bar_ODY_SMMUX_GATOS_ADDR(a) 0x0 /* PF_BAR0 */
1030 #define busnum_ODY_SMMUX_GATOS_ADDR(a) (a)
1031 #define arguments_ODY_SMMUX_GATOS_ADDR(a) (a), -1, -1, -1
1032
1033 /**
1034 * Register (NCB32b) smmu#_gatos_ctrl
1035 *
1036 * SMMU GATOS Control Register
1037 */
1038 union ody_smmux_gatos_ctrl {
1039 uint32_t u;
1040 struct ody_smmux_gatos_ctrl_s {
1041 uint32_t run : 1;
1042 uint32_t reserved_1_31 : 31;
1043 } s;
1044 /* struct ody_smmux_gatos_ctrl_s cn; */
1045 };
1046 typedef union ody_smmux_gatos_ctrl ody_smmux_gatos_ctrl_t;
1047
1048 static inline uint64_t ODY_SMMUX_GATOS_CTRL(uint64_t a) __attribute__ ((pure, always_inline));
ODY_SMMUX_GATOS_CTRL(uint64_t a)1049 static inline uint64_t ODY_SMMUX_GATOS_CTRL(uint64_t a)
1050 {
1051 if (a <= 3)
1052 return 0x830000000100ll + 0x1000000000ll * ((a) & 0x3);
1053 __ody_csr_fatal("SMMUX_GATOS_CTRL", 1, a, 0, 0, 0, 0, 0);
1054 }
1055
1056 #define typedef_ODY_SMMUX_GATOS_CTRL(a) ody_smmux_gatos_ctrl_t
1057 #define bustype_ODY_SMMUX_GATOS_CTRL(a) CSR_TYPE_NCB32b
1058 #define basename_ODY_SMMUX_GATOS_CTRL(a) "SMMUX_GATOS_CTRL"
1059 #define device_bar_ODY_SMMUX_GATOS_CTRL(a) 0x0 /* PF_BAR0 */
1060 #define busnum_ODY_SMMUX_GATOS_CTRL(a) (a)
1061 #define arguments_ODY_SMMUX_GATOS_CTRL(a) (a), -1, -1, -1
1062
1063 /**
1064 * Register (NCB) smmu#_gatos_par
1065 *
1066 * SMMU GATOS Address Register
1067 */
1068 union ody_smmux_gatos_par {
1069 uint64_t u;
1070 struct ody_smmux_gatos_par_s {
1071 uint64_t par : 64;
1072 } s;
1073 /* struct ody_smmux_gatos_par_s cn; */
1074 };
1075 typedef union ody_smmux_gatos_par ody_smmux_gatos_par_t;
1076
1077 static inline uint64_t ODY_SMMUX_GATOS_PAR(uint64_t a) __attribute__ ((pure, always_inline));
ODY_SMMUX_GATOS_PAR(uint64_t a)1078 static inline uint64_t ODY_SMMUX_GATOS_PAR(uint64_t a)
1079 {
1080 if (a <= 3)
1081 return 0x830000000118ll + 0x1000000000ll * ((a) & 0x3);
1082 __ody_csr_fatal("SMMUX_GATOS_PAR", 1, a, 0, 0, 0, 0, 0);
1083 }
1084
1085 #define typedef_ODY_SMMUX_GATOS_PAR(a) ody_smmux_gatos_par_t
1086 #define bustype_ODY_SMMUX_GATOS_PAR(a) CSR_TYPE_NCB
1087 #define basename_ODY_SMMUX_GATOS_PAR(a) "SMMUX_GATOS_PAR"
1088 #define device_bar_ODY_SMMUX_GATOS_PAR(a) 0x0 /* PF_BAR0 */
1089 #define busnum_ODY_SMMUX_GATOS_PAR(a) (a)
1090 #define arguments_ODY_SMMUX_GATOS_PAR(a) (a), -1, -1, -1
1091
1092 /**
1093 * Register (NCB) smmu#_gatos_sid
1094 *
1095 * SMMU GATOS SID Register
1096 */
1097 union ody_smmux_gatos_sid {
1098 uint64_t u;
1099 struct ody_smmux_gatos_sid_s {
1100 uint64_t streamid : 22;
1101 uint64_t reserved_22_31 : 10;
1102 uint64_t substreamid : 20;
1103 uint64_t ssid_valid : 1;
1104 uint64_t reserved_53_63 : 11;
1105 } s;
1106 /* struct ody_smmux_gatos_sid_s cn; */
1107 };
1108 typedef union ody_smmux_gatos_sid ody_smmux_gatos_sid_t;
1109
1110 static inline uint64_t ODY_SMMUX_GATOS_SID(uint64_t a) __attribute__ ((pure, always_inline));
ODY_SMMUX_GATOS_SID(uint64_t a)1111 static inline uint64_t ODY_SMMUX_GATOS_SID(uint64_t a)
1112 {
1113 if (a <= 3)
1114 return 0x830000000108ll + 0x1000000000ll * ((a) & 0x3);
1115 __ody_csr_fatal("SMMUX_GATOS_SID", 1, a, 0, 0, 0, 0, 0);
1116 }
1117
1118 #define typedef_ODY_SMMUX_GATOS_SID(a) ody_smmux_gatos_sid_t
1119 #define bustype_ODY_SMMUX_GATOS_SID(a) CSR_TYPE_NCB
1120 #define basename_ODY_SMMUX_GATOS_SID(a) "SMMUX_GATOS_SID"
1121 #define device_bar_ODY_SMMUX_GATOS_SID(a) 0x0 /* PF_BAR0 */
1122 #define busnum_ODY_SMMUX_GATOS_SID(a) (a)
1123 #define arguments_ODY_SMMUX_GATOS_SID(a) (a), -1, -1, -1
1124
1125 /**
1126 * Register (NCB32b) smmu#_gbpa
1127 *
1128 * SMMU Global Bypass Attribute Register
1129 */
1130 union ody_smmux_gbpa {
1131 uint32_t u;
1132 struct ody_smmux_gbpa_s {
1133 uint32_t memattr : 4;
1134 uint32_t mtcfg : 1;
1135 uint32_t reserved_5_7 : 3;
1136 uint32_t alloccfg : 4;
1137 uint32_t shcfg : 2;
1138 uint32_t reserved_14_15 : 2;
1139 uint32_t privcfg : 2;
1140 uint32_t instcfg : 2;
1141 uint32_t abrt : 1;
1142 uint32_t reserved_21_30 : 10;
1143 uint32_t update : 1;
1144 } s;
1145 /* struct ody_smmux_gbpa_s cn; */
1146 };
1147 typedef union ody_smmux_gbpa ody_smmux_gbpa_t;
1148
1149 static inline uint64_t ODY_SMMUX_GBPA(uint64_t a) __attribute__ ((pure, always_inline));
ODY_SMMUX_GBPA(uint64_t a)1150 static inline uint64_t ODY_SMMUX_GBPA(uint64_t a)
1151 {
1152 if (a <= 3)
1153 return 0x830000000044ll + 0x1000000000ll * ((a) & 0x3);
1154 __ody_csr_fatal("SMMUX_GBPA", 1, a, 0, 0, 0, 0, 0);
1155 }
1156
1157 #define typedef_ODY_SMMUX_GBPA(a) ody_smmux_gbpa_t
1158 #define bustype_ODY_SMMUX_GBPA(a) CSR_TYPE_NCB32b
1159 #define basename_ODY_SMMUX_GBPA(a) "SMMUX_GBPA"
1160 #define device_bar_ODY_SMMUX_GBPA(a) 0x0 /* PF_BAR0 */
1161 #define busnum_ODY_SMMUX_GBPA(a) (a)
1162 #define arguments_ODY_SMMUX_GBPA(a) (a), -1, -1, -1
1163
1164 /**
1165 * Register (NCB32b) smmu#_gbpmpam
1166 *
1167 * SMMU Global Bypass MPAM Configuration for Non-secure state Register
1168 */
1169 union ody_smmux_gbpmpam {
1170 uint32_t u;
1171 struct ody_smmux_gbpmpam_s {
1172 uint32_t gbp_partid : 9;
1173 uint32_t reserved_9_15 : 7;
1174 uint32_t gbp_pmg : 1;
1175 uint32_t reserved_17_30 : 14;
1176 uint32_t update : 1;
1177 } s;
1178 /* struct ody_smmux_gbpmpam_s cn; */
1179 };
1180 typedef union ody_smmux_gbpmpam ody_smmux_gbpmpam_t;
1181
1182 static inline uint64_t ODY_SMMUX_GBPMPAM(uint64_t a) __attribute__ ((pure, always_inline));
ODY_SMMUX_GBPMPAM(uint64_t a)1183 static inline uint64_t ODY_SMMUX_GBPMPAM(uint64_t a)
1184 {
1185 if (a <= 3)
1186 return 0x83000000013cll + 0x1000000000ll * ((a) & 0x3);
1187 __ody_csr_fatal("SMMUX_GBPMPAM", 1, a, 0, 0, 0, 0, 0);
1188 }
1189
1190 #define typedef_ODY_SMMUX_GBPMPAM(a) ody_smmux_gbpmpam_t
1191 #define bustype_ODY_SMMUX_GBPMPAM(a) CSR_TYPE_NCB32b
1192 #define basename_ODY_SMMUX_GBPMPAM(a) "SMMUX_GBPMPAM"
1193 #define device_bar_ODY_SMMUX_GBPMPAM(a) 0x0 /* PF_BAR0 */
1194 #define busnum_ODY_SMMUX_GBPMPAM(a) (a)
1195 #define arguments_ODY_SMMUX_GBPMPAM(a) (a), -1, -1, -1
1196
1197 /**
1198 * Register (NCB32b) smmu#_gerror
1199 *
1200 * SMMU Global Error Register
1201 * This register, in conjunction with SMMU()_(S_)GERRORN, indicates whether global error
1202 * conditions exist.
1203 *
1204 * The SMMU toggles SMMU()_(S_)GERROR[x] when an error becomes active. Software is
1205 * expected to toggle SMMU()_(S_)GERRORN[x] in response, to acknowledge the error.
1206 *
1207 * The SMMU does not toggle a bit when an error is already active. An error is only
1208 * activated if it is in an inactive state (i.e. a prior error has been
1209 * acknowledged/de-activated).
1210 *
1211 * Software is not intended to trigger interrupts by arranging for SMMU()_GERRORN\<x\> to differ
1212 * from SMMU()_GERROR\<x\>.
1213 */
1214 union ody_smmux_gerror {
1215 uint32_t u;
1216 struct ody_smmux_gerror_s {
1217 uint32_t cmdq_err : 1;
1218 uint32_t reserved_1 : 1;
1219 uint32_t eventq_abt_err : 1;
1220 uint32_t priq_abt_err : 1;
1221 uint32_t msi_cmdq_abt_err : 1;
1222 uint32_t msi_eventq_abt_err : 1;
1223 uint32_t msi_priq_abt_err : 1;
1224 uint32_t msi_gerror_abt_err : 1;
1225 uint32_t sfm_err : 1;
1226 uint32_t cmdqp_err : 1;
1227 uint32_t reserved_10_31 : 22;
1228 } s;
1229 /* struct ody_smmux_gerror_s cn; */
1230 };
1231 typedef union ody_smmux_gerror ody_smmux_gerror_t;
1232
1233 static inline uint64_t ODY_SMMUX_GERROR(uint64_t a) __attribute__ ((pure, always_inline));
ODY_SMMUX_GERROR(uint64_t a)1234 static inline uint64_t ODY_SMMUX_GERROR(uint64_t a)
1235 {
1236 if (a <= 3)
1237 return 0x830000000060ll + 0x1000000000ll * ((a) & 0x3);
1238 __ody_csr_fatal("SMMUX_GERROR", 1, a, 0, 0, 0, 0, 0);
1239 }
1240
1241 #define typedef_ODY_SMMUX_GERROR(a) ody_smmux_gerror_t
1242 #define bustype_ODY_SMMUX_GERROR(a) CSR_TYPE_NCB32b
1243 #define basename_ODY_SMMUX_GERROR(a) "SMMUX_GERROR"
1244 #define device_bar_ODY_SMMUX_GERROR(a) 0x0 /* PF_BAR0 */
1245 #define busnum_ODY_SMMUX_GERROR(a) (a)
1246 #define arguments_ODY_SMMUX_GERROR(a) (a), -1, -1, -1
1247
1248 /**
1249 * Register (NCB) smmu#_gerror_irq_cfg0
1250 *
1251 * SMMU Global Error IRQ Configuration 0 Register
1252 * Registers SMMU()_S_GERROR_IRQ_CFG0/1/2 are guarded by the respective
1253 * SMMU()_S_IRQ_CTRL[GERROR_IRQEN] and must only be modified when
1254 * SMMU()_S_IRQ_CTRL[GERROR_IRQEN]=0.
1255 */
1256 union ody_smmux_gerror_irq_cfg0 {
1257 uint64_t u;
1258 struct ody_smmux_gerror_irq_cfg0_s {
1259 uint64_t reserved_0_1 : 2;
1260 uint64_t addr : 50;
1261 uint64_t reserved_52_63 : 12;
1262 } s;
1263 /* struct ody_smmux_gerror_irq_cfg0_s cn; */
1264 };
1265 typedef union ody_smmux_gerror_irq_cfg0 ody_smmux_gerror_irq_cfg0_t;
1266
1267 static inline uint64_t ODY_SMMUX_GERROR_IRQ_CFG0(uint64_t a) __attribute__ ((pure, always_inline));
ODY_SMMUX_GERROR_IRQ_CFG0(uint64_t a)1268 static inline uint64_t ODY_SMMUX_GERROR_IRQ_CFG0(uint64_t a)
1269 {
1270 if (a <= 3)
1271 return 0x830000000068ll + 0x1000000000ll * ((a) & 0x3);
1272 __ody_csr_fatal("SMMUX_GERROR_IRQ_CFG0", 1, a, 0, 0, 0, 0, 0);
1273 }
1274
1275 #define typedef_ODY_SMMUX_GERROR_IRQ_CFG0(a) ody_smmux_gerror_irq_cfg0_t
1276 #define bustype_ODY_SMMUX_GERROR_IRQ_CFG0(a) CSR_TYPE_NCB
1277 #define basename_ODY_SMMUX_GERROR_IRQ_CFG0(a) "SMMUX_GERROR_IRQ_CFG0"
1278 #define device_bar_ODY_SMMUX_GERROR_IRQ_CFG0(a) 0x0 /* PF_BAR0 */
1279 #define busnum_ODY_SMMUX_GERROR_IRQ_CFG0(a) (a)
1280 #define arguments_ODY_SMMUX_GERROR_IRQ_CFG0(a) (a), -1, -1, -1
1281
1282 /**
1283 * Register (NCB32b) smmu#_gerror_irq_cfg1
1284 *
1285 * SMMU Global Error IRQ Configuration 1 Register
1286 */
1287 union ody_smmux_gerror_irq_cfg1 {
1288 uint32_t u;
1289 struct ody_smmux_gerror_irq_cfg1_s {
1290 uint32_t data : 32;
1291 } s;
1292 /* struct ody_smmux_gerror_irq_cfg1_s cn; */
1293 };
1294 typedef union ody_smmux_gerror_irq_cfg1 ody_smmux_gerror_irq_cfg1_t;
1295
1296 static inline uint64_t ODY_SMMUX_GERROR_IRQ_CFG1(uint64_t a) __attribute__ ((pure, always_inline));
ODY_SMMUX_GERROR_IRQ_CFG1(uint64_t a)1297 static inline uint64_t ODY_SMMUX_GERROR_IRQ_CFG1(uint64_t a)
1298 {
1299 if (a <= 3)
1300 return 0x830000000070ll + 0x1000000000ll * ((a) & 0x3);
1301 __ody_csr_fatal("SMMUX_GERROR_IRQ_CFG1", 1, a, 0, 0, 0, 0, 0);
1302 }
1303
1304 #define typedef_ODY_SMMUX_GERROR_IRQ_CFG1(a) ody_smmux_gerror_irq_cfg1_t
1305 #define bustype_ODY_SMMUX_GERROR_IRQ_CFG1(a) CSR_TYPE_NCB32b
1306 #define basename_ODY_SMMUX_GERROR_IRQ_CFG1(a) "SMMUX_GERROR_IRQ_CFG1"
1307 #define device_bar_ODY_SMMUX_GERROR_IRQ_CFG1(a) 0x0 /* PF_BAR0 */
1308 #define busnum_ODY_SMMUX_GERROR_IRQ_CFG1(a) (a)
1309 #define arguments_ODY_SMMUX_GERROR_IRQ_CFG1(a) (a), -1, -1, -1
1310
1311 /**
1312 * Register (NCB32b) smmu#_gerror_irq_cfg2
1313 *
1314 * SMMU Global Error IRQ Configuration 2 Register
1315 */
1316 union ody_smmux_gerror_irq_cfg2 {
1317 uint32_t u;
1318 struct ody_smmux_gerror_irq_cfg2_s {
1319 uint32_t memattr : 4;
1320 uint32_t sh : 2;
1321 uint32_t reserved_6_31 : 26;
1322 } s;
1323 /* struct ody_smmux_gerror_irq_cfg2_s cn; */
1324 };
1325 typedef union ody_smmux_gerror_irq_cfg2 ody_smmux_gerror_irq_cfg2_t;
1326
1327 static inline uint64_t ODY_SMMUX_GERROR_IRQ_CFG2(uint64_t a) __attribute__ ((pure, always_inline));
ODY_SMMUX_GERROR_IRQ_CFG2(uint64_t a)1328 static inline uint64_t ODY_SMMUX_GERROR_IRQ_CFG2(uint64_t a)
1329 {
1330 if (a <= 3)
1331 return 0x830000000074ll + 0x1000000000ll * ((a) & 0x3);
1332 __ody_csr_fatal("SMMUX_GERROR_IRQ_CFG2", 1, a, 0, 0, 0, 0, 0);
1333 }
1334
1335 #define typedef_ODY_SMMUX_GERROR_IRQ_CFG2(a) ody_smmux_gerror_irq_cfg2_t
1336 #define bustype_ODY_SMMUX_GERROR_IRQ_CFG2(a) CSR_TYPE_NCB32b
1337 #define basename_ODY_SMMUX_GERROR_IRQ_CFG2(a) "SMMUX_GERROR_IRQ_CFG2"
1338 #define device_bar_ODY_SMMUX_GERROR_IRQ_CFG2(a) 0x0 /* PF_BAR0 */
1339 #define busnum_ODY_SMMUX_GERROR_IRQ_CFG2(a) (a)
1340 #define arguments_ODY_SMMUX_GERROR_IRQ_CFG2(a) (a), -1, -1, -1
1341
1342 /**
1343 * Register (NCB32b) smmu#_gerrorn
1344 *
1345 * SMMU Global Error Acknowledge Register
1346 * Same fields as SMMU()_GERROR.
1347 *
1348 * Software must not toggle fields in this register that correspond to errors that are
1349 * inactive. It is constrained unpredictable whether or not an SMMU activates errors
1350 * if this is done.
1351 *
1352 * The SMMU does not alter fields in this register.
1353 *
1354 * Software might maintain an internal copy of the last value written to this register,
1355 * for comparison against values read from SMMU()_GERROR when probing for errors.
1356 */
1357 union ody_smmux_gerrorn {
1358 uint32_t u;
1359 struct ody_smmux_gerrorn_s {
1360 uint32_t cmdq_err : 1;
1361 uint32_t reserved_1 : 1;
1362 uint32_t eventq_abt_err : 1;
1363 uint32_t priq_abt_err : 1;
1364 uint32_t msi_cmdq_abt_err : 1;
1365 uint32_t msi_eventq_abt_err : 1;
1366 uint32_t msi_priq_abt_err : 1;
1367 uint32_t msi_gerror_abt_err : 1;
1368 uint32_t sfm_err : 1;
1369 uint32_t cmdqp_err : 1;
1370 uint32_t reserved_10_31 : 22;
1371 } s;
1372 /* struct ody_smmux_gerrorn_s cn; */
1373 };
1374 typedef union ody_smmux_gerrorn ody_smmux_gerrorn_t;
1375
1376 static inline uint64_t ODY_SMMUX_GERRORN(uint64_t a) __attribute__ ((pure, always_inline));
ODY_SMMUX_GERRORN(uint64_t a)1377 static inline uint64_t ODY_SMMUX_GERRORN(uint64_t a)
1378 {
1379 if (a <= 3)
1380 return 0x830000000064ll + 0x1000000000ll * ((a) & 0x3);
1381 __ody_csr_fatal("SMMUX_GERRORN", 1, a, 0, 0, 0, 0, 0);
1382 }
1383
1384 #define typedef_ODY_SMMUX_GERRORN(a) ody_smmux_gerrorn_t
1385 #define bustype_ODY_SMMUX_GERRORN(a) CSR_TYPE_NCB32b
1386 #define basename_ODY_SMMUX_GERRORN(a) "SMMUX_GERRORN"
1387 #define device_bar_ODY_SMMUX_GERRORN(a) 0x0 /* PF_BAR0 */
1388 #define busnum_ODY_SMMUX_GERRORN(a) (a)
1389 #define arguments_ODY_SMMUX_GERRORN(a) (a), -1, -1, -1
1390
1391 /**
1392 * Register (NCB32b) smmu#_gmpam
1393 *
1394 * SMMU Global MPAM Configuration for Non-secure state Register
1395 */
1396 union ody_smmux_gmpam {
1397 uint32_t u;
1398 struct ody_smmux_gmpam_s {
1399 uint32_t so_partid : 9;
1400 uint32_t reserved_9_15 : 7;
1401 uint32_t so_pmg : 1;
1402 uint32_t reserved_17_30 : 14;
1403 uint32_t update : 1;
1404 } s;
1405 /* struct ody_smmux_gmpam_s cn; */
1406 };
1407 typedef union ody_smmux_gmpam ody_smmux_gmpam_t;
1408
1409 static inline uint64_t ODY_SMMUX_GMPAM(uint64_t a) __attribute__ ((pure, always_inline));
ODY_SMMUX_GMPAM(uint64_t a)1410 static inline uint64_t ODY_SMMUX_GMPAM(uint64_t a)
1411 {
1412 if (a <= 3)
1413 return 0x830000000138ll + 0x1000000000ll * ((a) & 0x3);
1414 __ody_csr_fatal("SMMUX_GMPAM", 1, a, 0, 0, 0, 0, 0);
1415 }
1416
1417 #define typedef_ODY_SMMUX_GMPAM(a) ody_smmux_gmpam_t
1418 #define bustype_ODY_SMMUX_GMPAM(a) CSR_TYPE_NCB32b
1419 #define basename_ODY_SMMUX_GMPAM(a) "SMMUX_GMPAM"
1420 #define device_bar_ODY_SMMUX_GMPAM(a) 0x0 /* PF_BAR0 */
1421 #define busnum_ODY_SMMUX_GMPAM(a) (a)
1422 #define arguments_ODY_SMMUX_GMPAM(a) (a), -1, -1, -1
1423
1424 /**
1425 * Register (NCB32b) smmu#_idr0
1426 *
1427 * SMMU Identification 0 Register
1428 */
1429 union ody_smmux_idr0 {
1430 uint32_t u;
1431 struct ody_smmux_idr0_s {
1432 uint32_t s2p : 1;
1433 uint32_t s1p : 1;
1434 uint32_t ttf : 2;
1435 uint32_t cohacc : 1;
1436 uint32_t btm : 1;
1437 uint32_t httu : 2;
1438 uint32_t dormhint : 1;
1439 uint32_t hyp : 1;
1440 uint32_t ats : 1;
1441 uint32_t ns1ats : 1;
1442 uint32_t asid16 : 1;
1443 uint32_t msi : 1;
1444 uint32_t sev : 1;
1445 uint32_t atos : 1;
1446 uint32_t pri : 1;
1447 uint32_t vmw : 1;
1448 uint32_t vmid16 : 1;
1449 uint32_t cd2l : 1;
1450 uint32_t vatos : 1;
1451 uint32_t ttendian : 2;
1452 uint32_t atsrecerr : 1;
1453 uint32_t stall_model : 2;
1454 uint32_t term_model : 1;
1455 uint32_t st_level : 2;
1456 uint32_t reserved_29_31 : 3;
1457 } s;
1458 /* struct ody_smmux_idr0_s cn; */
1459 };
1460 typedef union ody_smmux_idr0 ody_smmux_idr0_t;
1461
1462 static inline uint64_t ODY_SMMUX_IDR0(uint64_t a) __attribute__ ((pure, always_inline));
ODY_SMMUX_IDR0(uint64_t a)1463 static inline uint64_t ODY_SMMUX_IDR0(uint64_t a)
1464 {
1465 if (a <= 3)
1466 return 0x830000000000ll + 0x1000000000ll * ((a) & 0x3);
1467 __ody_csr_fatal("SMMUX_IDR0", 1, a, 0, 0, 0, 0, 0);
1468 }
1469
1470 #define typedef_ODY_SMMUX_IDR0(a) ody_smmux_idr0_t
1471 #define bustype_ODY_SMMUX_IDR0(a) CSR_TYPE_NCB32b
1472 #define basename_ODY_SMMUX_IDR0(a) "SMMUX_IDR0"
1473 #define device_bar_ODY_SMMUX_IDR0(a) 0x0 /* PF_BAR0 */
1474 #define busnum_ODY_SMMUX_IDR0(a) (a)
1475 #define arguments_ODY_SMMUX_IDR0(a) (a), -1, -1, -1
1476
1477 /**
1478 * Register (NCB32b) smmu#_idr1
1479 *
1480 * SMMU Identification 1 Register
1481 */
1482 union ody_smmux_idr1 {
1483 uint32_t u;
1484 struct ody_smmux_idr1_s {
1485 uint32_t sidsize : 6;
1486 uint32_t ssidsize : 5;
1487 uint32_t priqs : 5;
1488 uint32_t eventqs : 5;
1489 uint32_t cmdqs : 5;
1490 uint32_t attr_perms_ovr : 1;
1491 uint32_t attr_types_ovr : 1;
1492 uint32_t rel : 1;
1493 uint32_t queues_preset : 1;
1494 uint32_t tables_preset : 1;
1495 uint32_t ecmdq : 1;
1496 } s;
1497 /* struct ody_smmux_idr1_s cn; */
1498 };
1499 typedef union ody_smmux_idr1 ody_smmux_idr1_t;
1500
1501 static inline uint64_t ODY_SMMUX_IDR1(uint64_t a) __attribute__ ((pure, always_inline));
ODY_SMMUX_IDR1(uint64_t a)1502 static inline uint64_t ODY_SMMUX_IDR1(uint64_t a)
1503 {
1504 if (a <= 3)
1505 return 0x830000000004ll + 0x1000000000ll * ((a) & 0x3);
1506 __ody_csr_fatal("SMMUX_IDR1", 1, a, 0, 0, 0, 0, 0);
1507 }
1508
1509 #define typedef_ODY_SMMUX_IDR1(a) ody_smmux_idr1_t
1510 #define bustype_ODY_SMMUX_IDR1(a) CSR_TYPE_NCB32b
1511 #define basename_ODY_SMMUX_IDR1(a) "SMMUX_IDR1"
1512 #define device_bar_ODY_SMMUX_IDR1(a) 0x0 /* PF_BAR0 */
1513 #define busnum_ODY_SMMUX_IDR1(a) (a)
1514 #define arguments_ODY_SMMUX_IDR1(a) (a), -1, -1, -1
1515
1516 /**
1517 * Register (NCB32b) smmu#_idr2
1518 *
1519 * SMMU Identification 2 Register
1520 */
1521 union ody_smmux_idr2 {
1522 uint32_t u;
1523 struct ody_smmux_idr2_s {
1524 uint32_t ba_vatos : 10;
1525 uint32_t reserved_10_31 : 22;
1526 } s;
1527 /* struct ody_smmux_idr2_s cn; */
1528 };
1529 typedef union ody_smmux_idr2 ody_smmux_idr2_t;
1530
1531 static inline uint64_t ODY_SMMUX_IDR2(uint64_t a) __attribute__ ((pure, always_inline));
ODY_SMMUX_IDR2(uint64_t a)1532 static inline uint64_t ODY_SMMUX_IDR2(uint64_t a)
1533 {
1534 if (a <= 3)
1535 return 0x830000000008ll + 0x1000000000ll * ((a) & 0x3);
1536 __ody_csr_fatal("SMMUX_IDR2", 1, a, 0, 0, 0, 0, 0);
1537 }
1538
1539 #define typedef_ODY_SMMUX_IDR2(a) ody_smmux_idr2_t
1540 #define bustype_ODY_SMMUX_IDR2(a) CSR_TYPE_NCB32b
1541 #define basename_ODY_SMMUX_IDR2(a) "SMMUX_IDR2"
1542 #define device_bar_ODY_SMMUX_IDR2(a) 0x0 /* PF_BAR0 */
1543 #define busnum_ODY_SMMUX_IDR2(a) (a)
1544 #define arguments_ODY_SMMUX_IDR2(a) (a), -1, -1, -1
1545
1546 /**
1547 * Register (NCB32b) smmu#_idr3
1548 *
1549 * SMMU Identification 3 Register
1550 */
1551 union ody_smmux_idr3 {
1552 uint32_t u;
1553 struct ody_smmux_idr3_s {
1554 uint32_t reserved_0_1 : 2;
1555 uint32_t had : 1;
1556 uint32_t pbha : 1;
1557 uint32_t xnx : 1;
1558 uint32_t pps : 1;
1559 uint32_t reserved_6 : 1;
1560 uint32_t mpam : 1;
1561 uint32_t fwb : 1;
1562 uint32_t stt : 1;
1563 uint32_t ril : 1;
1564 uint32_t bbml : 2;
1565 uint32_t e0pd : 1;
1566 uint32_t ptwnnc : 1;
1567 uint32_t reserved_15_31 : 17;
1568 } s;
1569 /* struct ody_smmux_idr3_s cn; */
1570 };
1571 typedef union ody_smmux_idr3 ody_smmux_idr3_t;
1572
1573 static inline uint64_t ODY_SMMUX_IDR3(uint64_t a) __attribute__ ((pure, always_inline));
ODY_SMMUX_IDR3(uint64_t a)1574 static inline uint64_t ODY_SMMUX_IDR3(uint64_t a)
1575 {
1576 if (a <= 3)
1577 return 0x83000000000cll + 0x1000000000ll * ((a) & 0x3);
1578 __ody_csr_fatal("SMMUX_IDR3", 1, a, 0, 0, 0, 0, 0);
1579 }
1580
1581 #define typedef_ODY_SMMUX_IDR3(a) ody_smmux_idr3_t
1582 #define bustype_ODY_SMMUX_IDR3(a) CSR_TYPE_NCB32b
1583 #define basename_ODY_SMMUX_IDR3(a) "SMMUX_IDR3"
1584 #define device_bar_ODY_SMMUX_IDR3(a) 0x0 /* PF_BAR0 */
1585 #define busnum_ODY_SMMUX_IDR3(a) (a)
1586 #define arguments_ODY_SMMUX_IDR3(a) (a), -1, -1, -1
1587
1588 /**
1589 * Register (NCB32b) smmu#_idr4
1590 *
1591 * SMMU Identification 4 Register
1592 * The contents of this register are implementation-defined and can be used to identify
1593 * the presence of other implementation-defined register regions elsewhere in the
1594 * memory map.
1595 */
1596 union ody_smmux_idr4 {
1597 uint32_t u;
1598 struct ody_smmux_idr4_s {
1599 uint32_t reserved_0_31 : 32;
1600 } s;
1601 /* struct ody_smmux_idr4_s cn; */
1602 };
1603 typedef union ody_smmux_idr4 ody_smmux_idr4_t;
1604
1605 static inline uint64_t ODY_SMMUX_IDR4(uint64_t a) __attribute__ ((pure, always_inline));
ODY_SMMUX_IDR4(uint64_t a)1606 static inline uint64_t ODY_SMMUX_IDR4(uint64_t a)
1607 {
1608 if (a <= 3)
1609 return 0x830000000010ll + 0x1000000000ll * ((a) & 0x3);
1610 __ody_csr_fatal("SMMUX_IDR4", 1, a, 0, 0, 0, 0, 0);
1611 }
1612
1613 #define typedef_ODY_SMMUX_IDR4(a) ody_smmux_idr4_t
1614 #define bustype_ODY_SMMUX_IDR4(a) CSR_TYPE_NCB32b
1615 #define basename_ODY_SMMUX_IDR4(a) "SMMUX_IDR4"
1616 #define device_bar_ODY_SMMUX_IDR4(a) 0x0 /* PF_BAR0 */
1617 #define busnum_ODY_SMMUX_IDR4(a) (a)
1618 #define arguments_ODY_SMMUX_IDR4(a) (a), -1, -1, -1
1619
1620 /**
1621 * Register (NCB32b) smmu#_idr5
1622 *
1623 * SMMU Identification 5 Register
1624 */
1625 union ody_smmux_idr5 {
1626 uint32_t u;
1627 struct ody_smmux_idr5_s {
1628 uint32_t oas : 3;
1629 uint32_t reserved_3 : 1;
1630 uint32_t gran4k : 1;
1631 uint32_t gran16k : 1;
1632 uint32_t gran64k : 1;
1633 uint32_t reserved_7_9 : 3;
1634 uint32_t vax : 2;
1635 uint32_t reserved_12_15 : 4;
1636 uint32_t stall_max : 16;
1637 } s;
1638 /* struct ody_smmux_idr5_s cn; */
1639 };
1640 typedef union ody_smmux_idr5 ody_smmux_idr5_t;
1641
1642 static inline uint64_t ODY_SMMUX_IDR5(uint64_t a) __attribute__ ((pure, always_inline));
ODY_SMMUX_IDR5(uint64_t a)1643 static inline uint64_t ODY_SMMUX_IDR5(uint64_t a)
1644 {
1645 if (a <= 3)
1646 return 0x830000000014ll + 0x1000000000ll * ((a) & 0x3);
1647 __ody_csr_fatal("SMMUX_IDR5", 1, a, 0, 0, 0, 0, 0);
1648 }
1649
1650 #define typedef_ODY_SMMUX_IDR5(a) ody_smmux_idr5_t
1651 #define bustype_ODY_SMMUX_IDR5(a) CSR_TYPE_NCB32b
1652 #define basename_ODY_SMMUX_IDR5(a) "SMMUX_IDR5"
1653 #define device_bar_ODY_SMMUX_IDR5(a) 0x0 /* PF_BAR0 */
1654 #define busnum_ODY_SMMUX_IDR5(a) (a)
1655 #define arguments_ODY_SMMUX_IDR5(a) (a), -1, -1, -1
1656
1657 /**
1658 * Register (NCB32b) smmu#_idr6
1659 *
1660 * SMMU Identification 6 Register
1661 */
1662 union ody_smmux_idr6 {
1663 uint32_t u;
1664 struct ody_smmux_idr6_s {
1665 uint32_t reserved_0_15 : 16;
1666 uint32_t cmdq_control_page_log2numq : 4;
1667 uint32_t reserved_20_23 : 4;
1668 uint32_t cmdq_control_page_log2nump : 4;
1669 uint32_t reserved_28_31 : 4;
1670 } s;
1671 /* struct ody_smmux_idr6_s cn; */
1672 };
1673 typedef union ody_smmux_idr6 ody_smmux_idr6_t;
1674
1675 static inline uint64_t ODY_SMMUX_IDR6(uint64_t a) __attribute__ ((pure, always_inline));
ODY_SMMUX_IDR6(uint64_t a)1676 static inline uint64_t ODY_SMMUX_IDR6(uint64_t a)
1677 {
1678 if (a <= 3)
1679 return 0x830000000190ll + 0x1000000000ll * ((a) & 0x3);
1680 __ody_csr_fatal("SMMUX_IDR6", 1, a, 0, 0, 0, 0, 0);
1681 }
1682
1683 #define typedef_ODY_SMMUX_IDR6(a) ody_smmux_idr6_t
1684 #define bustype_ODY_SMMUX_IDR6(a) CSR_TYPE_NCB32b
1685 #define basename_ODY_SMMUX_IDR6(a) "SMMUX_IDR6"
1686 #define device_bar_ODY_SMMUX_IDR6(a) 0x0 /* PF_BAR0 */
1687 #define busnum_ODY_SMMUX_IDR6(a) (a)
1688 #define arguments_ODY_SMMUX_IDR6(a) (a), -1, -1, -1
1689
1690 /**
1691 * Register (NCB32b) smmu#_iidr
1692 *
1693 * SMMU Implementation Identification Register
1694 * Provides information about the implementation/implementer of the SMMU and
1695 * architecture version supported.
1696 */
1697 union ody_smmux_iidr {
1698 uint32_t u;
1699 struct ody_smmux_iidr_s {
1700 uint32_t implementer : 12;
1701 uint32_t revision : 4;
1702 uint32_t variant : 4;
1703 uint32_t productid : 12;
1704 } s;
1705 /* struct ody_smmux_iidr_s cn; */
1706 };
1707 typedef union ody_smmux_iidr ody_smmux_iidr_t;
1708
1709 static inline uint64_t ODY_SMMUX_IIDR(uint64_t a) __attribute__ ((pure, always_inline));
ODY_SMMUX_IIDR(uint64_t a)1710 static inline uint64_t ODY_SMMUX_IIDR(uint64_t a)
1711 {
1712 if (a <= 3)
1713 return 0x830000000018ll + 0x1000000000ll * ((a) & 0x3);
1714 __ody_csr_fatal("SMMUX_IIDR", 1, a, 0, 0, 0, 0, 0);
1715 }
1716
1717 #define typedef_ODY_SMMUX_IIDR(a) ody_smmux_iidr_t
1718 #define bustype_ODY_SMMUX_IIDR(a) CSR_TYPE_NCB32b
1719 #define basename_ODY_SMMUX_IIDR(a) "SMMUX_IIDR"
1720 #define device_bar_ODY_SMMUX_IIDR(a) 0x0 /* PF_BAR0 */
1721 #define busnum_ODY_SMMUX_IIDR(a) (a)
1722 #define arguments_ODY_SMMUX_IIDR(a) (a), -1, -1, -1
1723
1724 /**
1725 * Register (NCB32b) smmu#_imp_actlr
1726 *
1727 * SMMU Auxiliary Control Register
1728 */
1729 union ody_smmux_imp_actlr {
1730 uint32_t u;
1731 struct ody_smmux_imp_actlr_s {
1732 uint32_t qos : 4;
1733 uint32_t reserved_4_31 : 28;
1734 } s;
1735 /* struct ody_smmux_imp_actlr_s cn; */
1736 };
1737 typedef union ody_smmux_imp_actlr ody_smmux_imp_actlr_t;
1738
1739 static inline uint64_t ODY_SMMUX_IMP_ACTLR(uint64_t a) __attribute__ ((pure, always_inline));
ODY_SMMUX_IMP_ACTLR(uint64_t a)1740 static inline uint64_t ODY_SMMUX_IMP_ACTLR(uint64_t a)
1741 {
1742 if (a <= 3)
1743 return 0x830000000e10ll + 0x1000000000ll * ((a) & 0x3);
1744 __ody_csr_fatal("SMMUX_IMP_ACTLR", 1, a, 0, 0, 0, 0, 0);
1745 }
1746
1747 #define typedef_ODY_SMMUX_IMP_ACTLR(a) ody_smmux_imp_actlr_t
1748 #define bustype_ODY_SMMUX_IMP_ACTLR(a) CSR_TYPE_NCB32b
1749 #define basename_ODY_SMMUX_IMP_ACTLR(a) "SMMUX_IMP_ACTLR"
1750 #define device_bar_ODY_SMMUX_IMP_ACTLR(a) 0x0 /* PF_BAR0 */
1751 #define busnum_ODY_SMMUX_IMP_ACTLR(a) (a)
1752 #define arguments_ODY_SMMUX_IMP_ACTLR(a) (a), -1, -1, -1
1753
1754 /**
1755 * Register (NCB) smmu#_imp_const0
1756 *
1757 * SMMU Constant Register
1758 */
1759 union ody_smmux_imp_const0 {
1760 uint64_t u;
1761 struct ody_smmux_imp_const0_s {
1762 uint64_t tlb : 16;
1763 uint64_t reserved_16_47 : 32;
1764 uint64_t cfc : 16;
1765 } s;
1766 /* struct ody_smmux_imp_const0_s cn; */
1767 };
1768 typedef union ody_smmux_imp_const0 ody_smmux_imp_const0_t;
1769
1770 static inline uint64_t ODY_SMMUX_IMP_CONST0(uint64_t a) __attribute__ ((pure, always_inline));
ODY_SMMUX_IMP_CONST0(uint64_t a)1771 static inline uint64_t ODY_SMMUX_IMP_CONST0(uint64_t a)
1772 {
1773 if (a <= 3)
1774 return 0x830000000e08ll + 0x1000000000ll * ((a) & 0x3);
1775 __ody_csr_fatal("SMMUX_IMP_CONST0", 1, a, 0, 0, 0, 0, 0);
1776 }
1777
1778 #define typedef_ODY_SMMUX_IMP_CONST0(a) ody_smmux_imp_const0_t
1779 #define bustype_ODY_SMMUX_IMP_CONST0(a) CSR_TYPE_NCB
1780 #define basename_ODY_SMMUX_IMP_CONST0(a) "SMMUX_IMP_CONST0"
1781 #define device_bar_ODY_SMMUX_IMP_CONST0(a) 0x0 /* PF_BAR0 */
1782 #define busnum_ODY_SMMUX_IMP_CONST0(a) (a)
1783 #define arguments_ODY_SMMUX_IMP_CONST0(a) (a), -1, -1, -1
1784
1785 /**
1786 * Register (NCB32b) smmu#_imp_error_cause
1787 *
1788 * SMMU cause for error event Register
1789 * This register contains debug information.
1790 */
1791 union ody_smmux_imp_error_cause {
1792 uint32_t u;
1793 struct ody_smmux_imp_error_cause_s {
1794 uint32_t ste_valid : 1;
1795 uint32_t ste_sel2 : 1;
1796 uint32_t ste_strw : 1;
1797 uint32_t ste_s1stalld : 1;
1798 uint32_t ste_s1contextptr : 1;
1799 uint32_t ste_s2s : 1;
1800 uint32_t ste_s2tg : 1;
1801 uint32_t ste_aarch : 1;
1802 uint32_t ste_httu : 1;
1803 uint32_t ste_s2ttb : 1;
1804 uint32_t ste_s2t0sz : 1;
1805 uint32_t ste_s2_walk_cfg : 1;
1806 uint32_t cd_valid : 1;
1807 uint32_t cd_s : 1;
1808 uint32_t cd_streamworld : 1;
1809 uint32_t cd_aarch : 1;
1810 uint32_t cd_httu : 1;
1811 uint32_t cd_txsz : 1;
1812 uint32_t cd_ttbx : 1;
1813 uint32_t cd_tgx : 1;
1814 uint32_t reserved_20_23 : 4;
1815 uint32_t ttd_valid : 1;
1816 uint32_t crs_endianness : 1;
1817 uint32_t crs_compr_err_on_httu_upd_resp : 1;
1818 uint32_t crs_unexp_err_on_httu_upd_resp : 1;
1819 uint32_t wlk_crs_miss_dbm_upd_needed : 1;
1820 uint32_t wlk_crs_miss_httu_upd_needed : 1;
1821 uint32_t bus_poison : 1;
1822 uint32_t bus_error : 1;
1823 } s;
1824 /* struct ody_smmux_imp_error_cause_s cn; */
1825 };
1826 typedef union ody_smmux_imp_error_cause ody_smmux_imp_error_cause_t;
1827
1828 static inline uint64_t ODY_SMMUX_IMP_ERROR_CAUSE(uint64_t a) __attribute__ ((pure, always_inline));
ODY_SMMUX_IMP_ERROR_CAUSE(uint64_t a)1829 static inline uint64_t ODY_SMMUX_IMP_ERROR_CAUSE(uint64_t a)
1830 {
1831 if (a <= 3)
1832 return 0x830000000e20ll + 0x1000000000ll * ((a) & 0x3);
1833 __ody_csr_fatal("SMMUX_IMP_ERROR_CAUSE", 1, a, 0, 0, 0, 0, 0);
1834 }
1835
1836 #define typedef_ODY_SMMUX_IMP_ERROR_CAUSE(a) ody_smmux_imp_error_cause_t
1837 #define bustype_ODY_SMMUX_IMP_ERROR_CAUSE(a) CSR_TYPE_NCB32b
1838 #define basename_ODY_SMMUX_IMP_ERROR_CAUSE(a) "SMMUX_IMP_ERROR_CAUSE"
1839 #define device_bar_ODY_SMMUX_IMP_ERROR_CAUSE(a) 0x0 /* PF_BAR0 */
1840 #define busnum_ODY_SMMUX_IMP_ERROR_CAUSE(a) (a)
1841 #define arguments_ODY_SMMUX_IMP_ERROR_CAUSE(a) (a), -1, -1, -1
1842
1843 /**
1844 * Register (NCB32b) smmu#_imp_status
1845 *
1846 * SMMU Debug Registers
1847 * This register contains debug information.
1848 */
1849 union ody_smmux_imp_status {
1850 uint32_t u;
1851 struct ody_smmux_imp_status_s {
1852 uint32_t inflight : 16;
1853 uint32_t walker : 5;
1854 uint32_t cfgwalker : 5;
1855 uint32_t reserved_26_31 : 6;
1856 } s;
1857 /* struct ody_smmux_imp_status_s cn; */
1858 };
1859 typedef union ody_smmux_imp_status ody_smmux_imp_status_t;
1860
1861 static inline uint64_t ODY_SMMUX_IMP_STATUS(uint64_t a) __attribute__ ((pure, always_inline));
ODY_SMMUX_IMP_STATUS(uint64_t a)1862 static inline uint64_t ODY_SMMUX_IMP_STATUS(uint64_t a)
1863 {
1864 if (a <= 3)
1865 return 0x830000000e18ll + 0x1000000000ll * ((a) & 0x3);
1866 __ody_csr_fatal("SMMUX_IMP_STATUS", 1, a, 0, 0, 0, 0, 0);
1867 }
1868
1869 #define typedef_ODY_SMMUX_IMP_STATUS(a) ody_smmux_imp_status_t
1870 #define bustype_ODY_SMMUX_IMP_STATUS(a) CSR_TYPE_NCB32b
1871 #define basename_ODY_SMMUX_IMP_STATUS(a) "SMMUX_IMP_STATUS"
1872 #define device_bar_ODY_SMMUX_IMP_STATUS(a) 0x0 /* PF_BAR0 */
1873 #define busnum_ODY_SMMUX_IMP_STATUS(a) (a)
1874 #define arguments_ODY_SMMUX_IMP_STATUS(a) (a), -1, -1, -1
1875
1876 /**
1877 * Register (NCB32b) smmu#_irq_ctrl
1878 *
1879 * SMMU Interrupt Request Control Register
1880 * Each field in this register has a corresponding field in SMMU()_IRQ_CTRLACK, with
1881 * the same "update" semantic as fields in SMMU()_CR0 versus SMMU()_CR0ACK.
1882 *
1883 * This register contains IRQ enable flags for GERROR/PRIQ/EVENTQ interrupt
1884 * sources. These enables allow/inhibit both edge-triggered wired outputs (if
1885 * implemented) and MSI writes (if implemented).
1886 *
1887 * IRQ enable flags guard the MSI address/payload registers, which must only be changed
1888 * when their respective enable flag is zero. See SMMU()_GERROR_IRQ_CFG0 for details.
1889 *
1890 * Completion of an update of x_IRQEN from zero to one guarantees that the MSI configuration
1891 * in SMMU()_x_IRQ_CFG{0,1,2} will be used for all future MSIs generated from source `x'.
1892 * An update of x_IRQEN from one to zero completes when all prior MSIs have become visible
1893 * to their shareability domain (have completed). Completion of this update guarantees
1894 * that no new MSI writes or wired edge events will later become visible from source
1895 * `x'.
1896 */
1897 union ody_smmux_irq_ctrl {
1898 uint32_t u;
1899 struct ody_smmux_irq_ctrl_s {
1900 uint32_t gerror_irqen : 1;
1901 uint32_t priq_irqen : 1;
1902 uint32_t eventq_irqen : 1;
1903 uint32_t reserved_3_31 : 29;
1904 } s;
1905 /* struct ody_smmux_irq_ctrl_s cn; */
1906 };
1907 typedef union ody_smmux_irq_ctrl ody_smmux_irq_ctrl_t;
1908
1909 static inline uint64_t ODY_SMMUX_IRQ_CTRL(uint64_t a) __attribute__ ((pure, always_inline));
ODY_SMMUX_IRQ_CTRL(uint64_t a)1910 static inline uint64_t ODY_SMMUX_IRQ_CTRL(uint64_t a)
1911 {
1912 if (a <= 3)
1913 return 0x830000000050ll + 0x1000000000ll * ((a) & 0x3);
1914 __ody_csr_fatal("SMMUX_IRQ_CTRL", 1, a, 0, 0, 0, 0, 0);
1915 }
1916
1917 #define typedef_ODY_SMMUX_IRQ_CTRL(a) ody_smmux_irq_ctrl_t
1918 #define bustype_ODY_SMMUX_IRQ_CTRL(a) CSR_TYPE_NCB32b
1919 #define basename_ODY_SMMUX_IRQ_CTRL(a) "SMMUX_IRQ_CTRL"
1920 #define device_bar_ODY_SMMUX_IRQ_CTRL(a) 0x0 /* PF_BAR0 */
1921 #define busnum_ODY_SMMUX_IRQ_CTRL(a) (a)
1922 #define arguments_ODY_SMMUX_IRQ_CTRL(a) (a), -1, -1, -1
1923
1924 /**
1925 * Register (NCB32b) smmu#_irq_ctrlack
1926 *
1927 * SMMU Interrupt Control Acknowledgement Register
1928 * This register is a read-only copy of SMMU()_IRQ_CTRL.
1929 */
1930 union ody_smmux_irq_ctrlack {
1931 uint32_t u;
1932 struct ody_smmux_irq_ctrlack_s {
1933 uint32_t gerror_irqen : 1;
1934 uint32_t priq_irqen : 1;
1935 uint32_t eventq_irqen : 1;
1936 uint32_t reserved_3_31 : 29;
1937 } s;
1938 /* struct ody_smmux_irq_ctrlack_s cn; */
1939 };
1940 typedef union ody_smmux_irq_ctrlack ody_smmux_irq_ctrlack_t;
1941
1942 static inline uint64_t ODY_SMMUX_IRQ_CTRLACK(uint64_t a) __attribute__ ((pure, always_inline));
ODY_SMMUX_IRQ_CTRLACK(uint64_t a)1943 static inline uint64_t ODY_SMMUX_IRQ_CTRLACK(uint64_t a)
1944 {
1945 if (a <= 3)
1946 return 0x830000000054ll + 0x1000000000ll * ((a) & 0x3);
1947 __ody_csr_fatal("SMMUX_IRQ_CTRLACK", 1, a, 0, 0, 0, 0, 0);
1948 }
1949
1950 #define typedef_ODY_SMMUX_IRQ_CTRLACK(a) ody_smmux_irq_ctrlack_t
1951 #define bustype_ODY_SMMUX_IRQ_CTRLACK(a) CSR_TYPE_NCB32b
1952 #define basename_ODY_SMMUX_IRQ_CTRLACK(a) "SMMUX_IRQ_CTRLACK"
1953 #define device_bar_ODY_SMMUX_IRQ_CTRLACK(a) 0x0 /* PF_BAR0 */
1954 #define busnum_ODY_SMMUX_IRQ_CTRLACK(a) (a)
1955 #define arguments_ODY_SMMUX_IRQ_CTRLACK(a) (a), -1, -1, -1
1956
1957 /**
1958 * Register (NCB32b) smmu#_mpamidr
1959 *
1960 * MPAM capability identification for Non-secure state Register
1961 */
1962 union ody_smmux_mpamidr {
1963 uint32_t u;
1964 struct ody_smmux_mpamidr_s {
1965 uint32_t partid_max : 16;
1966 uint32_t pmg_max : 8;
1967 uint32_t reserved_24_31 : 8;
1968 } s;
1969 /* struct ody_smmux_mpamidr_s cn; */
1970 };
1971 typedef union ody_smmux_mpamidr ody_smmux_mpamidr_t;
1972
1973 static inline uint64_t ODY_SMMUX_MPAMIDR(uint64_t a) __attribute__ ((pure, always_inline));
ODY_SMMUX_MPAMIDR(uint64_t a)1974 static inline uint64_t ODY_SMMUX_MPAMIDR(uint64_t a)
1975 {
1976 if (a <= 3)
1977 return 0x830000000130ll + 0x1000000000ll * ((a) & 0x3);
1978 __ody_csr_fatal("SMMUX_MPAMIDR", 1, a, 0, 0, 0, 0, 0);
1979 }
1980
1981 #define typedef_ODY_SMMUX_MPAMIDR(a) ody_smmux_mpamidr_t
1982 #define bustype_ODY_SMMUX_MPAMIDR(a) CSR_TYPE_NCB32b
1983 #define basename_ODY_SMMUX_MPAMIDR(a) "SMMUX_MPAMIDR"
1984 #define device_bar_ODY_SMMUX_MPAMIDR(a) 0x0 /* PF_BAR0 */
1985 #define busnum_ODY_SMMUX_MPAMIDR(a) (a)
1986 #define arguments_ODY_SMMUX_MPAMIDR(a) (a), -1, -1, -1
1987
1988 /**
1989 * Register (NCB32b) smmu#_pidr0
1990 *
1991 * SMMU Peripheral Identification Register 0
1992 */
1993 union ody_smmux_pidr0 {
1994 uint32_t u;
1995 struct ody_smmux_pidr0_s {
1996 uint32_t partnum0 : 8;
1997 uint32_t reserved_8_31 : 24;
1998 } s;
1999 /* struct ody_smmux_pidr0_s cn; */
2000 };
2001 typedef union ody_smmux_pidr0 ody_smmux_pidr0_t;
2002
2003 static inline uint64_t ODY_SMMUX_PIDR0(uint64_t a) __attribute__ ((pure, always_inline));
ODY_SMMUX_PIDR0(uint64_t a)2004 static inline uint64_t ODY_SMMUX_PIDR0(uint64_t a)
2005 {
2006 if (a <= 3)
2007 return 0x830000000fe0ll + 0x1000000000ll * ((a) & 0x3);
2008 __ody_csr_fatal("SMMUX_PIDR0", 1, a, 0, 0, 0, 0, 0);
2009 }
2010
2011 #define typedef_ODY_SMMUX_PIDR0(a) ody_smmux_pidr0_t
2012 #define bustype_ODY_SMMUX_PIDR0(a) CSR_TYPE_NCB32b
2013 #define basename_ODY_SMMUX_PIDR0(a) "SMMUX_PIDR0"
2014 #define device_bar_ODY_SMMUX_PIDR0(a) 0x0 /* PF_BAR0 */
2015 #define busnum_ODY_SMMUX_PIDR0(a) (a)
2016 #define arguments_ODY_SMMUX_PIDR0(a) (a), -1, -1, -1
2017
2018 /**
2019 * Register (NCB32b) smmu#_pidr1
2020 *
2021 * SMMU Peripheral Identification Register 1
2022 */
2023 union ody_smmux_pidr1 {
2024 uint32_t u;
2025 struct ody_smmux_pidr1_s {
2026 uint32_t partnum1 : 4;
2027 uint32_t idcode : 4;
2028 uint32_t reserved_8_31 : 24;
2029 } s;
2030 /* struct ody_smmux_pidr1_s cn; */
2031 };
2032 typedef union ody_smmux_pidr1 ody_smmux_pidr1_t;
2033
2034 static inline uint64_t ODY_SMMUX_PIDR1(uint64_t a) __attribute__ ((pure, always_inline));
ODY_SMMUX_PIDR1(uint64_t a)2035 static inline uint64_t ODY_SMMUX_PIDR1(uint64_t a)
2036 {
2037 if (a <= 3)
2038 return 0x830000000fe4ll + 0x1000000000ll * ((a) & 0x3);
2039 __ody_csr_fatal("SMMUX_PIDR1", 1, a, 0, 0, 0, 0, 0);
2040 }
2041
2042 #define typedef_ODY_SMMUX_PIDR1(a) ody_smmux_pidr1_t
2043 #define bustype_ODY_SMMUX_PIDR1(a) CSR_TYPE_NCB32b
2044 #define basename_ODY_SMMUX_PIDR1(a) "SMMUX_PIDR1"
2045 #define device_bar_ODY_SMMUX_PIDR1(a) 0x0 /* PF_BAR0 */
2046 #define busnum_ODY_SMMUX_PIDR1(a) (a)
2047 #define arguments_ODY_SMMUX_PIDR1(a) (a), -1, -1, -1
2048
2049 /**
2050 * Register (NCB32b) smmu#_pidr2
2051 *
2052 * SMMU Peripheral Identification Register 2
2053 */
2054 union ody_smmux_pidr2 {
2055 uint32_t u;
2056 struct ody_smmux_pidr2_s {
2057 uint32_t idcode : 3;
2058 uint32_t jedec : 1;
2059 uint32_t revision : 4;
2060 uint32_t reserved_8_31 : 24;
2061 } s;
2062 /* struct ody_smmux_pidr2_s cn; */
2063 };
2064 typedef union ody_smmux_pidr2 ody_smmux_pidr2_t;
2065
2066 static inline uint64_t ODY_SMMUX_PIDR2(uint64_t a) __attribute__ ((pure, always_inline));
ODY_SMMUX_PIDR2(uint64_t a)2067 static inline uint64_t ODY_SMMUX_PIDR2(uint64_t a)
2068 {
2069 if (a <= 3)
2070 return 0x830000000fe8ll + 0x1000000000ll * ((a) & 0x3);
2071 __ody_csr_fatal("SMMUX_PIDR2", 1, a, 0, 0, 0, 0, 0);
2072 }
2073
2074 #define typedef_ODY_SMMUX_PIDR2(a) ody_smmux_pidr2_t
2075 #define bustype_ODY_SMMUX_PIDR2(a) CSR_TYPE_NCB32b
2076 #define basename_ODY_SMMUX_PIDR2(a) "SMMUX_PIDR2"
2077 #define device_bar_ODY_SMMUX_PIDR2(a) 0x0 /* PF_BAR0 */
2078 #define busnum_ODY_SMMUX_PIDR2(a) (a)
2079 #define arguments_ODY_SMMUX_PIDR2(a) (a), -1, -1, -1
2080
2081 /**
2082 * Register (NCB32b) smmu#_pidr3
2083 *
2084 * SMMU Peripheral Identification Register 3
2085 */
2086 union ody_smmux_pidr3 {
2087 uint32_t u;
2088 struct ody_smmux_pidr3_s {
2089 uint32_t cust : 4;
2090 uint32_t revand : 4;
2091 uint32_t reserved_8_31 : 24;
2092 } s;
2093 /* struct ody_smmux_pidr3_s cn; */
2094 };
2095 typedef union ody_smmux_pidr3 ody_smmux_pidr3_t;
2096
2097 static inline uint64_t ODY_SMMUX_PIDR3(uint64_t a) __attribute__ ((pure, always_inline));
ODY_SMMUX_PIDR3(uint64_t a)2098 static inline uint64_t ODY_SMMUX_PIDR3(uint64_t a)
2099 {
2100 if (a <= 3)
2101 return 0x830000000fecll + 0x1000000000ll * ((a) & 0x3);
2102 __ody_csr_fatal("SMMUX_PIDR3", 1, a, 0, 0, 0, 0, 0);
2103 }
2104
2105 #define typedef_ODY_SMMUX_PIDR3(a) ody_smmux_pidr3_t
2106 #define bustype_ODY_SMMUX_PIDR3(a) CSR_TYPE_NCB32b
2107 #define basename_ODY_SMMUX_PIDR3(a) "SMMUX_PIDR3"
2108 #define device_bar_ODY_SMMUX_PIDR3(a) 0x0 /* PF_BAR0 */
2109 #define busnum_ODY_SMMUX_PIDR3(a) (a)
2110 #define arguments_ODY_SMMUX_PIDR3(a) (a), -1, -1, -1
2111
2112 /**
2113 * Register (NCB32b) smmu#_pidr4
2114 *
2115 * SMMU Peripheral Identification Register 4
2116 */
2117 union ody_smmux_pidr4 {
2118 uint32_t u;
2119 struct ody_smmux_pidr4_s {
2120 uint32_t jepcont : 4;
2121 uint32_t pagecnt : 4;
2122 uint32_t reserved_8_31 : 24;
2123 } s;
2124 /* struct ody_smmux_pidr4_s cn; */
2125 };
2126 typedef union ody_smmux_pidr4 ody_smmux_pidr4_t;
2127
2128 static inline uint64_t ODY_SMMUX_PIDR4(uint64_t a) __attribute__ ((pure, always_inline));
ODY_SMMUX_PIDR4(uint64_t a)2129 static inline uint64_t ODY_SMMUX_PIDR4(uint64_t a)
2130 {
2131 if (a <= 3)
2132 return 0x830000000fd0ll + 0x1000000000ll * ((a) & 0x3);
2133 __ody_csr_fatal("SMMUX_PIDR4", 1, a, 0, 0, 0, 0, 0);
2134 }
2135
2136 #define typedef_ODY_SMMUX_PIDR4(a) ody_smmux_pidr4_t
2137 #define bustype_ODY_SMMUX_PIDR4(a) CSR_TYPE_NCB32b
2138 #define basename_ODY_SMMUX_PIDR4(a) "SMMUX_PIDR4"
2139 #define device_bar_ODY_SMMUX_PIDR4(a) 0x0 /* PF_BAR0 */
2140 #define busnum_ODY_SMMUX_PIDR4(a) (a)
2141 #define arguments_ODY_SMMUX_PIDR4(a) (a), -1, -1, -1
2142
2143 /**
2144 * Register (NCB32b) smmu#_pidr5
2145 *
2146 * SMMU Peripheral Identification Register 5
2147 */
2148 union ody_smmux_pidr5 {
2149 uint32_t u;
2150 struct ody_smmux_pidr5_s {
2151 uint32_t reserved_0_31 : 32;
2152 } s;
2153 /* struct ody_smmux_pidr5_s cn; */
2154 };
2155 typedef union ody_smmux_pidr5 ody_smmux_pidr5_t;
2156
2157 static inline uint64_t ODY_SMMUX_PIDR5(uint64_t a) __attribute__ ((pure, always_inline));
ODY_SMMUX_PIDR5(uint64_t a)2158 static inline uint64_t ODY_SMMUX_PIDR5(uint64_t a)
2159 {
2160 if (a <= 3)
2161 return 0x830000000fd4ll + 0x1000000000ll * ((a) & 0x3);
2162 __ody_csr_fatal("SMMUX_PIDR5", 1, a, 0, 0, 0, 0, 0);
2163 }
2164
2165 #define typedef_ODY_SMMUX_PIDR5(a) ody_smmux_pidr5_t
2166 #define bustype_ODY_SMMUX_PIDR5(a) CSR_TYPE_NCB32b
2167 #define basename_ODY_SMMUX_PIDR5(a) "SMMUX_PIDR5"
2168 #define device_bar_ODY_SMMUX_PIDR5(a) 0x0 /* PF_BAR0 */
2169 #define busnum_ODY_SMMUX_PIDR5(a) (a)
2170 #define arguments_ODY_SMMUX_PIDR5(a) (a), -1, -1, -1
2171
2172 /**
2173 * Register (NCB32b) smmu#_pidr6
2174 *
2175 * SMMU Peripheral Identification Register 6
2176 */
2177 union ody_smmux_pidr6 {
2178 uint32_t u;
2179 struct ody_smmux_pidr6_s {
2180 uint32_t reserved_0_31 : 32;
2181 } s;
2182 /* struct ody_smmux_pidr6_s cn; */
2183 };
2184 typedef union ody_smmux_pidr6 ody_smmux_pidr6_t;
2185
2186 static inline uint64_t ODY_SMMUX_PIDR6(uint64_t a) __attribute__ ((pure, always_inline));
ODY_SMMUX_PIDR6(uint64_t a)2187 static inline uint64_t ODY_SMMUX_PIDR6(uint64_t a)
2188 {
2189 if (a <= 3)
2190 return 0x830000000fd8ll + 0x1000000000ll * ((a) & 0x3);
2191 __ody_csr_fatal("SMMUX_PIDR6", 1, a, 0, 0, 0, 0, 0);
2192 }
2193
2194 #define typedef_ODY_SMMUX_PIDR6(a) ody_smmux_pidr6_t
2195 #define bustype_ODY_SMMUX_PIDR6(a) CSR_TYPE_NCB32b
2196 #define basename_ODY_SMMUX_PIDR6(a) "SMMUX_PIDR6"
2197 #define device_bar_ODY_SMMUX_PIDR6(a) 0x0 /* PF_BAR0 */
2198 #define busnum_ODY_SMMUX_PIDR6(a) (a)
2199 #define arguments_ODY_SMMUX_PIDR6(a) (a), -1, -1, -1
2200
2201 /**
2202 * Register (NCB32b) smmu#_pidr7
2203 *
2204 * SMMU Peripheral Identification Register 7
2205 */
2206 union ody_smmux_pidr7 {
2207 uint32_t u;
2208 struct ody_smmux_pidr7_s {
2209 uint32_t reserved_0_31 : 32;
2210 } s;
2211 /* struct ody_smmux_pidr7_s cn; */
2212 };
2213 typedef union ody_smmux_pidr7 ody_smmux_pidr7_t;
2214
2215 static inline uint64_t ODY_SMMUX_PIDR7(uint64_t a) __attribute__ ((pure, always_inline));
ODY_SMMUX_PIDR7(uint64_t a)2216 static inline uint64_t ODY_SMMUX_PIDR7(uint64_t a)
2217 {
2218 if (a <= 3)
2219 return 0x830000000fdcll + 0x1000000000ll * ((a) & 0x3);
2220 __ody_csr_fatal("SMMUX_PIDR7", 1, a, 0, 0, 0, 0, 0);
2221 }
2222
2223 #define typedef_ODY_SMMUX_PIDR7(a) ody_smmux_pidr7_t
2224 #define bustype_ODY_SMMUX_PIDR7(a) CSR_TYPE_NCB32b
2225 #define basename_ODY_SMMUX_PIDR7(a) "SMMUX_PIDR7"
2226 #define device_bar_ODY_SMMUX_PIDR7(a) 0x0 /* PF_BAR0 */
2227 #define busnum_ODY_SMMUX_PIDR7(a) (a)
2228 #define arguments_ODY_SMMUX_PIDR7(a) (a), -1, -1, -1
2229
2230 /**
2231 * Register (NCB32b) smmu#_pmcg#_aidr
2232 *
2233 * SMMU PMCG Architecture Identification Register
2234 */
2235 union ody_smmux_pmcgx_aidr {
2236 uint32_t u;
2237 struct ody_smmux_pmcgx_aidr_s {
2238 uint32_t archminorrev : 4;
2239 uint32_t archmajorrev : 4;
2240 uint32_t reserved_8_31 : 24;
2241 } s;
2242 /* struct ody_smmux_pmcgx_aidr_s cn; */
2243 };
2244 typedef union ody_smmux_pmcgx_aidr ody_smmux_pmcgx_aidr_t;
2245
2246 static inline uint64_t ODY_SMMUX_PMCGX_AIDR(uint64_t a, uint64_t b) __attribute__ ((pure, always_inline));
ODY_SMMUX_PMCGX_AIDR(uint64_t a,uint64_t b)2247 static inline uint64_t ODY_SMMUX_PMCGX_AIDR(uint64_t a, uint64_t b)
2248 {
2249 if ((a <= 3) && (b <= 3))
2250 return 0x830000100e70ll + 0x1000000000ll * ((a) & 0x3) + 0x20000ll * ((b) & 0x3);
2251 __ody_csr_fatal("SMMUX_PMCGX_AIDR", 2, a, b, 0, 0, 0, 0);
2252 }
2253
2254 #define typedef_ODY_SMMUX_PMCGX_AIDR(a, b) ody_smmux_pmcgx_aidr_t
2255 #define bustype_ODY_SMMUX_PMCGX_AIDR(a, b) CSR_TYPE_NCB32b
2256 #define basename_ODY_SMMUX_PMCGX_AIDR(a, b) "SMMUX_PMCGX_AIDR"
2257 #define device_bar_ODY_SMMUX_PMCGX_AIDR(a, b) 0x0 /* PF_BAR0 */
2258 #define busnum_ODY_SMMUX_PMCGX_AIDR(a, b) (a)
2259 #define arguments_ODY_SMMUX_PMCGX_AIDR(a, b) (a), (b), -1, -1
2260
2261 /**
2262 * Register (NCB32b) smmu#_pmcg#_capr
2263 *
2264 * SMMU PMCG Counter Shadow Value Register
2265 */
2266 union ody_smmux_pmcgx_capr {
2267 uint32_t u;
2268 struct ody_smmux_pmcgx_capr_s {
2269 uint32_t capture : 1;
2270 uint32_t reserved_1_31 : 31;
2271 } s;
2272 /* struct ody_smmux_pmcgx_capr_s cn; */
2273 };
2274 typedef union ody_smmux_pmcgx_capr ody_smmux_pmcgx_capr_t;
2275
2276 static inline uint64_t ODY_SMMUX_PMCGX_CAPR(uint64_t a, uint64_t b) __attribute__ ((pure, always_inline));
ODY_SMMUX_PMCGX_CAPR(uint64_t a,uint64_t b)2277 static inline uint64_t ODY_SMMUX_PMCGX_CAPR(uint64_t a, uint64_t b)
2278 {
2279 if ((a <= 3) && (b <= 3))
2280 return 0x830000100d88ll + 0x1000000000ll * ((a) & 0x3) + 0x20000ll * ((b) & 0x3);
2281 __ody_csr_fatal("SMMUX_PMCGX_CAPR", 2, a, b, 0, 0, 0, 0);
2282 }
2283
2284 #define typedef_ODY_SMMUX_PMCGX_CAPR(a, b) ody_smmux_pmcgx_capr_t
2285 #define bustype_ODY_SMMUX_PMCGX_CAPR(a, b) CSR_TYPE_NCB32b
2286 #define basename_ODY_SMMUX_PMCGX_CAPR(a, b) "SMMUX_PMCGX_CAPR"
2287 #define device_bar_ODY_SMMUX_PMCGX_CAPR(a, b) 0x0 /* PF_BAR0 */
2288 #define busnum_ODY_SMMUX_PMCGX_CAPR(a, b) (a)
2289 #define arguments_ODY_SMMUX_PMCGX_CAPR(a, b) (a), (b), -1, -1
2290
2291 /**
2292 * Register (NCB) smmu#_pmcg#_ceid0
2293 *
2294 * SMMU PMCG Common Event ID bitmap, Lower Register
2295 */
2296 union ody_smmux_pmcgx_ceid0 {
2297 uint64_t u;
2298 struct ody_smmux_pmcgx_ceid0_s {
2299 uint64_t bitmap : 64;
2300 } s;
2301 /* struct ody_smmux_pmcgx_ceid0_s cn; */
2302 };
2303 typedef union ody_smmux_pmcgx_ceid0 ody_smmux_pmcgx_ceid0_t;
2304
2305 static inline uint64_t ODY_SMMUX_PMCGX_CEID0(uint64_t a, uint64_t b) __attribute__ ((pure, always_inline));
ODY_SMMUX_PMCGX_CEID0(uint64_t a,uint64_t b)2306 static inline uint64_t ODY_SMMUX_PMCGX_CEID0(uint64_t a, uint64_t b)
2307 {
2308 if ((a <= 3) && (b <= 3))
2309 return 0x830000100e20ll + 0x1000000000ll * ((a) & 0x3) + 0x20000ll * ((b) & 0x3);
2310 __ody_csr_fatal("SMMUX_PMCGX_CEID0", 2, a, b, 0, 0, 0, 0);
2311 }
2312
2313 #define typedef_ODY_SMMUX_PMCGX_CEID0(a, b) ody_smmux_pmcgx_ceid0_t
2314 #define bustype_ODY_SMMUX_PMCGX_CEID0(a, b) CSR_TYPE_NCB
2315 #define basename_ODY_SMMUX_PMCGX_CEID0(a, b) "SMMUX_PMCGX_CEID0"
2316 #define device_bar_ODY_SMMUX_PMCGX_CEID0(a, b) 0x0 /* PF_BAR0 */
2317 #define busnum_ODY_SMMUX_PMCGX_CEID0(a, b) (a)
2318 #define arguments_ODY_SMMUX_PMCGX_CEID0(a, b) (a), (b), -1, -1
2319
2320 /**
2321 * Register (NCB) smmu#_pmcg#_ceid1
2322 *
2323 * SMMU PMCG Common Event ID bitmap, Upper Register
2324 */
2325 union ody_smmux_pmcgx_ceid1 {
2326 uint64_t u;
2327 struct ody_smmux_pmcgx_ceid1_s {
2328 uint64_t bitmap : 64;
2329 } s;
2330 /* struct ody_smmux_pmcgx_ceid1_s cn; */
2331 };
2332 typedef union ody_smmux_pmcgx_ceid1 ody_smmux_pmcgx_ceid1_t;
2333
2334 static inline uint64_t ODY_SMMUX_PMCGX_CEID1(uint64_t a, uint64_t b) __attribute__ ((pure, always_inline));
ODY_SMMUX_PMCGX_CEID1(uint64_t a,uint64_t b)2335 static inline uint64_t ODY_SMMUX_PMCGX_CEID1(uint64_t a, uint64_t b)
2336 {
2337 if ((a <= 3) && (b <= 3))
2338 return 0x830000100e28ll + 0x1000000000ll * ((a) & 0x3) + 0x20000ll * ((b) & 0x3);
2339 __ody_csr_fatal("SMMUX_PMCGX_CEID1", 2, a, b, 0, 0, 0, 0);
2340 }
2341
2342 #define typedef_ODY_SMMUX_PMCGX_CEID1(a, b) ody_smmux_pmcgx_ceid1_t
2343 #define bustype_ODY_SMMUX_PMCGX_CEID1(a, b) CSR_TYPE_NCB
2344 #define basename_ODY_SMMUX_PMCGX_CEID1(a, b) "SMMUX_PMCGX_CEID1"
2345 #define device_bar_ODY_SMMUX_PMCGX_CEID1(a, b) 0x0 /* PF_BAR0 */
2346 #define busnum_ODY_SMMUX_PMCGX_CEID1(a, b) (a)
2347 #define arguments_ODY_SMMUX_PMCGX_CEID1(a, b) (a), (b), -1, -1
2348
2349 /**
2350 * Register (NCB32b) smmu#_pmcg#_cfgr
2351 *
2352 * SMMU PMCG Configuration Register
2353 */
2354 union ody_smmux_pmcgx_cfgr {
2355 uint32_t u;
2356 struct ody_smmux_pmcgx_cfgr_s {
2357 uint32_t nctr : 6;
2358 uint32_t reserved_6_7 : 2;
2359 uint32_t size : 6;
2360 uint32_t reserved_14_19 : 6;
2361 uint32_t reloc_ctrs : 1;
2362 uint32_t msi : 1;
2363 uint32_t capture : 1;
2364 uint32_t sid_filter_type : 1;
2365 uint32_t mpam : 1;
2366 uint32_t filter_partid_pmg : 1;
2367 uint32_t reserved_26_31 : 6;
2368 } s;
2369 /* struct ody_smmux_pmcgx_cfgr_s cn; */
2370 };
2371 typedef union ody_smmux_pmcgx_cfgr ody_smmux_pmcgx_cfgr_t;
2372
2373 static inline uint64_t ODY_SMMUX_PMCGX_CFGR(uint64_t a, uint64_t b) __attribute__ ((pure, always_inline));
ODY_SMMUX_PMCGX_CFGR(uint64_t a,uint64_t b)2374 static inline uint64_t ODY_SMMUX_PMCGX_CFGR(uint64_t a, uint64_t b)
2375 {
2376 if ((a <= 3) && (b <= 3))
2377 return 0x830000100e00ll + 0x1000000000ll * ((a) & 0x3) + 0x20000ll * ((b) & 0x3);
2378 __ody_csr_fatal("SMMUX_PMCGX_CFGR", 2, a, b, 0, 0, 0, 0);
2379 }
2380
2381 #define typedef_ODY_SMMUX_PMCGX_CFGR(a, b) ody_smmux_pmcgx_cfgr_t
2382 #define bustype_ODY_SMMUX_PMCGX_CFGR(a, b) CSR_TYPE_NCB32b
2383 #define basename_ODY_SMMUX_PMCGX_CFGR(a, b) "SMMUX_PMCGX_CFGR"
2384 #define device_bar_ODY_SMMUX_PMCGX_CFGR(a, b) 0x0 /* PF_BAR0 */
2385 #define busnum_ODY_SMMUX_PMCGX_CFGR(a, b) (a)
2386 #define arguments_ODY_SMMUX_PMCGX_CFGR(a, b) (a), (b), -1, -1
2387
2388 /**
2389 * Register (NCB32b) smmu#_pmcg#_cidr0
2390 *
2391 * SMMU Component Identification Register 0
2392 */
2393 union ody_smmux_pmcgx_cidr0 {
2394 uint32_t u;
2395 struct ody_smmux_pmcgx_cidr0_s {
2396 uint32_t preamble : 8;
2397 uint32_t reserved_8_31 : 24;
2398 } s;
2399 /* struct ody_smmux_pmcgx_cidr0_s cn; */
2400 };
2401 typedef union ody_smmux_pmcgx_cidr0 ody_smmux_pmcgx_cidr0_t;
2402
2403 static inline uint64_t ODY_SMMUX_PMCGX_CIDR0(uint64_t a, uint64_t b) __attribute__ ((pure, always_inline));
ODY_SMMUX_PMCGX_CIDR0(uint64_t a,uint64_t b)2404 static inline uint64_t ODY_SMMUX_PMCGX_CIDR0(uint64_t a, uint64_t b)
2405 {
2406 if ((a <= 3) && (b <= 3))
2407 return 0x830000100ff0ll + 0x1000000000ll * ((a) & 0x3) + 0x20000ll * ((b) & 0x3);
2408 __ody_csr_fatal("SMMUX_PMCGX_CIDR0", 2, a, b, 0, 0, 0, 0);
2409 }
2410
2411 #define typedef_ODY_SMMUX_PMCGX_CIDR0(a, b) ody_smmux_pmcgx_cidr0_t
2412 #define bustype_ODY_SMMUX_PMCGX_CIDR0(a, b) CSR_TYPE_NCB32b
2413 #define basename_ODY_SMMUX_PMCGX_CIDR0(a, b) "SMMUX_PMCGX_CIDR0"
2414 #define device_bar_ODY_SMMUX_PMCGX_CIDR0(a, b) 0x0 /* PF_BAR0 */
2415 #define busnum_ODY_SMMUX_PMCGX_CIDR0(a, b) (a)
2416 #define arguments_ODY_SMMUX_PMCGX_CIDR0(a, b) (a), (b), -1, -1
2417
2418 /**
2419 * Register (NCB32b) smmu#_pmcg#_cidr1
2420 *
2421 * SMMU PMCG Component Identification Register 1
2422 */
2423 union ody_smmux_pmcgx_cidr1 {
2424 uint32_t u;
2425 struct ody_smmux_pmcgx_cidr1_s {
2426 uint32_t preamble : 4;
2427 uint32_t component_class : 4;
2428 uint32_t reserved_8_31 : 24;
2429 } s;
2430 /* struct ody_smmux_pmcgx_cidr1_s cn; */
2431 };
2432 typedef union ody_smmux_pmcgx_cidr1 ody_smmux_pmcgx_cidr1_t;
2433
2434 static inline uint64_t ODY_SMMUX_PMCGX_CIDR1(uint64_t a, uint64_t b) __attribute__ ((pure, always_inline));
ODY_SMMUX_PMCGX_CIDR1(uint64_t a,uint64_t b)2435 static inline uint64_t ODY_SMMUX_PMCGX_CIDR1(uint64_t a, uint64_t b)
2436 {
2437 if ((a <= 3) && (b <= 3))
2438 return 0x830000100ff4ll + 0x1000000000ll * ((a) & 0x3) + 0x20000ll * ((b) & 0x3);
2439 __ody_csr_fatal("SMMUX_PMCGX_CIDR1", 2, a, b, 0, 0, 0, 0);
2440 }
2441
2442 #define typedef_ODY_SMMUX_PMCGX_CIDR1(a, b) ody_smmux_pmcgx_cidr1_t
2443 #define bustype_ODY_SMMUX_PMCGX_CIDR1(a, b) CSR_TYPE_NCB32b
2444 #define basename_ODY_SMMUX_PMCGX_CIDR1(a, b) "SMMUX_PMCGX_CIDR1"
2445 #define device_bar_ODY_SMMUX_PMCGX_CIDR1(a, b) 0x0 /* PF_BAR0 */
2446 #define busnum_ODY_SMMUX_PMCGX_CIDR1(a, b) (a)
2447 #define arguments_ODY_SMMUX_PMCGX_CIDR1(a, b) (a), (b), -1, -1
2448
2449 /**
2450 * Register (NCB32b) smmu#_pmcg#_cidr2
2451 *
2452 * SMMU PMCG Component Identification Register 2
2453 */
2454 union ody_smmux_pmcgx_cidr2 {
2455 uint32_t u;
2456 struct ody_smmux_pmcgx_cidr2_s {
2457 uint32_t preamble : 8;
2458 uint32_t reserved_8_31 : 24;
2459 } s;
2460 /* struct ody_smmux_pmcgx_cidr2_s cn; */
2461 };
2462 typedef union ody_smmux_pmcgx_cidr2 ody_smmux_pmcgx_cidr2_t;
2463
2464 static inline uint64_t ODY_SMMUX_PMCGX_CIDR2(uint64_t a, uint64_t b) __attribute__ ((pure, always_inline));
ODY_SMMUX_PMCGX_CIDR2(uint64_t a,uint64_t b)2465 static inline uint64_t ODY_SMMUX_PMCGX_CIDR2(uint64_t a, uint64_t b)
2466 {
2467 if ((a <= 3) && (b <= 3))
2468 return 0x830000100ff8ll + 0x1000000000ll * ((a) & 0x3) + 0x20000ll * ((b) & 0x3);
2469 __ody_csr_fatal("SMMUX_PMCGX_CIDR2", 2, a, b, 0, 0, 0, 0);
2470 }
2471
2472 #define typedef_ODY_SMMUX_PMCGX_CIDR2(a, b) ody_smmux_pmcgx_cidr2_t
2473 #define bustype_ODY_SMMUX_PMCGX_CIDR2(a, b) CSR_TYPE_NCB32b
2474 #define basename_ODY_SMMUX_PMCGX_CIDR2(a, b) "SMMUX_PMCGX_CIDR2"
2475 #define device_bar_ODY_SMMUX_PMCGX_CIDR2(a, b) 0x0 /* PF_BAR0 */
2476 #define busnum_ODY_SMMUX_PMCGX_CIDR2(a, b) (a)
2477 #define arguments_ODY_SMMUX_PMCGX_CIDR2(a, b) (a), (b), -1, -1
2478
2479 /**
2480 * Register (NCB32b) smmu#_pmcg#_cidr3
2481 *
2482 * SMMU PMCG Component Identification Register 3
2483 */
2484 union ody_smmux_pmcgx_cidr3 {
2485 uint32_t u;
2486 struct ody_smmux_pmcgx_cidr3_s {
2487 uint32_t preamble : 8;
2488 uint32_t reserved_8_31 : 24;
2489 } s;
2490 /* struct ody_smmux_pmcgx_cidr3_s cn; */
2491 };
2492 typedef union ody_smmux_pmcgx_cidr3 ody_smmux_pmcgx_cidr3_t;
2493
2494 static inline uint64_t ODY_SMMUX_PMCGX_CIDR3(uint64_t a, uint64_t b) __attribute__ ((pure, always_inline));
ODY_SMMUX_PMCGX_CIDR3(uint64_t a,uint64_t b)2495 static inline uint64_t ODY_SMMUX_PMCGX_CIDR3(uint64_t a, uint64_t b)
2496 {
2497 if ((a <= 3) && (b <= 3))
2498 return 0x830000100ffcll + 0x1000000000ll * ((a) & 0x3) + 0x20000ll * ((b) & 0x3);
2499 __ody_csr_fatal("SMMUX_PMCGX_CIDR3", 2, a, b, 0, 0, 0, 0);
2500 }
2501
2502 #define typedef_ODY_SMMUX_PMCGX_CIDR3(a, b) ody_smmux_pmcgx_cidr3_t
2503 #define bustype_ODY_SMMUX_PMCGX_CIDR3(a, b) CSR_TYPE_NCB32b
2504 #define basename_ODY_SMMUX_PMCGX_CIDR3(a, b) "SMMUX_PMCGX_CIDR3"
2505 #define device_bar_ODY_SMMUX_PMCGX_CIDR3(a, b) 0x0 /* PF_BAR0 */
2506 #define busnum_ODY_SMMUX_PMCGX_CIDR3(a, b) (a)
2507 #define arguments_ODY_SMMUX_PMCGX_CIDR3(a, b) (a), (b), -1, -1
2508
2509 /**
2510 * Register (NCB) smmu#_pmcg#_cntenclr0
2511 *
2512 * SMMU PMCG Counter Enable Clear Register
2513 */
2514 union ody_smmux_pmcgx_cntenclr0 {
2515 uint64_t u;
2516 struct ody_smmux_pmcgx_cntenclr0_s {
2517 uint64_t cnten : 4;
2518 uint64_t reserved_4_63 : 60;
2519 } s;
2520 /* struct ody_smmux_pmcgx_cntenclr0_s cn; */
2521 };
2522 typedef union ody_smmux_pmcgx_cntenclr0 ody_smmux_pmcgx_cntenclr0_t;
2523
2524 static inline uint64_t ODY_SMMUX_PMCGX_CNTENCLR0(uint64_t a, uint64_t b) __attribute__ ((pure, always_inline));
ODY_SMMUX_PMCGX_CNTENCLR0(uint64_t a,uint64_t b)2525 static inline uint64_t ODY_SMMUX_PMCGX_CNTENCLR0(uint64_t a, uint64_t b)
2526 {
2527 if ((a <= 3) && (b <= 3))
2528 return 0x830000100c20ll + 0x1000000000ll * ((a) & 0x3) + 0x20000ll * ((b) & 0x3);
2529 __ody_csr_fatal("SMMUX_PMCGX_CNTENCLR0", 2, a, b, 0, 0, 0, 0);
2530 }
2531
2532 #define typedef_ODY_SMMUX_PMCGX_CNTENCLR0(a, b) ody_smmux_pmcgx_cntenclr0_t
2533 #define bustype_ODY_SMMUX_PMCGX_CNTENCLR0(a, b) CSR_TYPE_NCB
2534 #define basename_ODY_SMMUX_PMCGX_CNTENCLR0(a, b) "SMMUX_PMCGX_CNTENCLR0"
2535 #define device_bar_ODY_SMMUX_PMCGX_CNTENCLR0(a, b) 0x0 /* PF_BAR0 */
2536 #define busnum_ODY_SMMUX_PMCGX_CNTENCLR0(a, b) (a)
2537 #define arguments_ODY_SMMUX_PMCGX_CNTENCLR0(a, b) (a), (b), -1, -1
2538
2539 /**
2540 * Register (NCB) smmu#_pmcg#_cntenset0
2541 *
2542 * SMMU PMCG Counter Enable Set Register
2543 */
2544 union ody_smmux_pmcgx_cntenset0 {
2545 uint64_t u;
2546 struct ody_smmux_pmcgx_cntenset0_s {
2547 uint64_t cnten : 4;
2548 uint64_t reserved_4_63 : 60;
2549 } s;
2550 /* struct ody_smmux_pmcgx_cntenset0_s cn; */
2551 };
2552 typedef union ody_smmux_pmcgx_cntenset0 ody_smmux_pmcgx_cntenset0_t;
2553
2554 static inline uint64_t ODY_SMMUX_PMCGX_CNTENSET0(uint64_t a, uint64_t b) __attribute__ ((pure, always_inline));
ODY_SMMUX_PMCGX_CNTENSET0(uint64_t a,uint64_t b)2555 static inline uint64_t ODY_SMMUX_PMCGX_CNTENSET0(uint64_t a, uint64_t b)
2556 {
2557 if ((a <= 3) && (b <= 3))
2558 return 0x830000100c00ll + 0x1000000000ll * ((a) & 0x3) + 0x20000ll * ((b) & 0x3);
2559 __ody_csr_fatal("SMMUX_PMCGX_CNTENSET0", 2, a, b, 0, 0, 0, 0);
2560 }
2561
2562 #define typedef_ODY_SMMUX_PMCGX_CNTENSET0(a, b) ody_smmux_pmcgx_cntenset0_t
2563 #define bustype_ODY_SMMUX_PMCGX_CNTENSET0(a, b) CSR_TYPE_NCB
2564 #define basename_ODY_SMMUX_PMCGX_CNTENSET0(a, b) "SMMUX_PMCGX_CNTENSET0"
2565 #define device_bar_ODY_SMMUX_PMCGX_CNTENSET0(a, b) 0x0 /* PF_BAR0 */
2566 #define busnum_ODY_SMMUX_PMCGX_CNTENSET0(a, b) (a)
2567 #define arguments_ODY_SMMUX_PMCGX_CNTENSET0(a, b) (a), (b), -1, -1
2568
2569 /**
2570 * Register (NCB32b) smmu#_pmcg#_cr
2571 *
2572 * SMMU PMCG Global Counter Enable Register
2573 */
2574 union ody_smmux_pmcgx_cr {
2575 uint32_t u;
2576 struct ody_smmux_pmcgx_cr_s {
2577 uint32_t enable : 1;
2578 uint32_t reserved_1_31 : 31;
2579 } s;
2580 /* struct ody_smmux_pmcgx_cr_s cn; */
2581 };
2582 typedef union ody_smmux_pmcgx_cr ody_smmux_pmcgx_cr_t;
2583
2584 static inline uint64_t ODY_SMMUX_PMCGX_CR(uint64_t a, uint64_t b) __attribute__ ((pure, always_inline));
ODY_SMMUX_PMCGX_CR(uint64_t a,uint64_t b)2585 static inline uint64_t ODY_SMMUX_PMCGX_CR(uint64_t a, uint64_t b)
2586 {
2587 if ((a <= 3) && (b <= 3))
2588 return 0x830000100e04ll + 0x1000000000ll * ((a) & 0x3) + 0x20000ll * ((b) & 0x3);
2589 __ody_csr_fatal("SMMUX_PMCGX_CR", 2, a, b, 0, 0, 0, 0);
2590 }
2591
2592 #define typedef_ODY_SMMUX_PMCGX_CR(a, b) ody_smmux_pmcgx_cr_t
2593 #define bustype_ODY_SMMUX_PMCGX_CR(a, b) CSR_TYPE_NCB32b
2594 #define basename_ODY_SMMUX_PMCGX_CR(a, b) "SMMUX_PMCGX_CR"
2595 #define device_bar_ODY_SMMUX_PMCGX_CR(a, b) 0x0 /* PF_BAR0 */
2596 #define busnum_ODY_SMMUX_PMCGX_CR(a, b) (a)
2597 #define arguments_ODY_SMMUX_PMCGX_CR(a, b) (a), (b), -1, -1
2598
2599 /**
2600 * Register (NCB) smmu#_pmcg#_evcntr#
2601 *
2602 * SMMU PMCG Event Counter Register
2603 */
2604 union ody_smmux_pmcgx_evcntrx {
2605 uint64_t u;
2606 struct ody_smmux_pmcgx_evcntrx_s {
2607 uint64_t count : 64;
2608 } s;
2609 /* struct ody_smmux_pmcgx_evcntrx_s cn; */
2610 };
2611 typedef union ody_smmux_pmcgx_evcntrx ody_smmux_pmcgx_evcntrx_t;
2612
2613 static inline uint64_t ODY_SMMUX_PMCGX_EVCNTRX(uint64_t a, uint64_t b, uint64_t c) __attribute__ ((pure, always_inline));
ODY_SMMUX_PMCGX_EVCNTRX(uint64_t a,uint64_t b,uint64_t c)2614 static inline uint64_t ODY_SMMUX_PMCGX_EVCNTRX(uint64_t a, uint64_t b, uint64_t c)
2615 {
2616 if ((a <= 3) && (b <= 3) && (c <= 3))
2617 return 0x830000110000ll + 0x1000000000ll * ((a) & 0x3) + 0x20000ll * ((b) & 0x3) + 8ll * ((c) & 0x3);
2618 __ody_csr_fatal("SMMUX_PMCGX_EVCNTRX", 3, a, b, c, 0, 0, 0);
2619 }
2620
2621 #define typedef_ODY_SMMUX_PMCGX_EVCNTRX(a, b, c) ody_smmux_pmcgx_evcntrx_t
2622 #define bustype_ODY_SMMUX_PMCGX_EVCNTRX(a, b, c) CSR_TYPE_NCB
2623 #define basename_ODY_SMMUX_PMCGX_EVCNTRX(a, b, c) "SMMUX_PMCGX_EVCNTRX"
2624 #define device_bar_ODY_SMMUX_PMCGX_EVCNTRX(a, b, c) 0x0 /* PF_BAR0 */
2625 #define busnum_ODY_SMMUX_PMCGX_EVCNTRX(a, b, c) (a)
2626 #define arguments_ODY_SMMUX_PMCGX_EVCNTRX(a, b, c) (a), (b), (c), -1
2627
2628 /**
2629 * Register (NCB32b) smmu#_pmcg#_evtyper#
2630 *
2631 * SMMU PMCG Event Type Configuration Register
2632 */
2633 union ody_smmux_pmcgx_evtyperx {
2634 uint32_t u;
2635 struct ody_smmux_pmcgx_evtyperx_s {
2636 uint32_t evnt : 8;
2637 uint32_t reserved_8_28 : 21;
2638 uint32_t filter_sid_span : 1;
2639 uint32_t filter_sec_sid : 1;
2640 uint32_t ovfcap : 1;
2641 } s;
2642 /* struct ody_smmux_pmcgx_evtyperx_s cn; */
2643 };
2644 typedef union ody_smmux_pmcgx_evtyperx ody_smmux_pmcgx_evtyperx_t;
2645
2646 static inline uint64_t ODY_SMMUX_PMCGX_EVTYPERX(uint64_t a, uint64_t b, uint64_t c) __attribute__ ((pure, always_inline));
ODY_SMMUX_PMCGX_EVTYPERX(uint64_t a,uint64_t b,uint64_t c)2647 static inline uint64_t ODY_SMMUX_PMCGX_EVTYPERX(uint64_t a, uint64_t b, uint64_t c)
2648 {
2649 if ((a <= 3) && (b <= 3) && (c <= 3))
2650 return 0x830000100400ll + 0x1000000000ll * ((a) & 0x3) + 0x20000ll * ((b) & 0x3) + 4ll * ((c) & 0x3);
2651 __ody_csr_fatal("SMMUX_PMCGX_EVTYPERX", 3, a, b, c, 0, 0, 0);
2652 }
2653
2654 #define typedef_ODY_SMMUX_PMCGX_EVTYPERX(a, b, c) ody_smmux_pmcgx_evtyperx_t
2655 #define bustype_ODY_SMMUX_PMCGX_EVTYPERX(a, b, c) CSR_TYPE_NCB32b
2656 #define basename_ODY_SMMUX_PMCGX_EVTYPERX(a, b, c) "SMMUX_PMCGX_EVTYPERX"
2657 #define device_bar_ODY_SMMUX_PMCGX_EVTYPERX(a, b, c) 0x0 /* PF_BAR0 */
2658 #define busnum_ODY_SMMUX_PMCGX_EVTYPERX(a, b, c) (a)
2659 #define arguments_ODY_SMMUX_PMCGX_EVTYPERX(a, b, c) (a), (b), (c), -1
2660
2661 /**
2662 * Register (NCB) smmu#_pmcg#_intenclr0
2663 *
2664 * SMMU PMCG Interrupt Enable Clear Register
2665 */
2666 union ody_smmux_pmcgx_intenclr0 {
2667 uint64_t u;
2668 struct ody_smmux_pmcgx_intenclr0_s {
2669 uint64_t inten : 4;
2670 uint64_t reserved_4_63 : 60;
2671 } s;
2672 /* struct ody_smmux_pmcgx_intenclr0_s cn; */
2673 };
2674 typedef union ody_smmux_pmcgx_intenclr0 ody_smmux_pmcgx_intenclr0_t;
2675
2676 static inline uint64_t ODY_SMMUX_PMCGX_INTENCLR0(uint64_t a, uint64_t b) __attribute__ ((pure, always_inline));
ODY_SMMUX_PMCGX_INTENCLR0(uint64_t a,uint64_t b)2677 static inline uint64_t ODY_SMMUX_PMCGX_INTENCLR0(uint64_t a, uint64_t b)
2678 {
2679 if ((a <= 3) && (b <= 3))
2680 return 0x830000100c60ll + 0x1000000000ll * ((a) & 0x3) + 0x20000ll * ((b) & 0x3);
2681 __ody_csr_fatal("SMMUX_PMCGX_INTENCLR0", 2, a, b, 0, 0, 0, 0);
2682 }
2683
2684 #define typedef_ODY_SMMUX_PMCGX_INTENCLR0(a, b) ody_smmux_pmcgx_intenclr0_t
2685 #define bustype_ODY_SMMUX_PMCGX_INTENCLR0(a, b) CSR_TYPE_NCB
2686 #define basename_ODY_SMMUX_PMCGX_INTENCLR0(a, b) "SMMUX_PMCGX_INTENCLR0"
2687 #define device_bar_ODY_SMMUX_PMCGX_INTENCLR0(a, b) 0x0 /* PF_BAR0 */
2688 #define busnum_ODY_SMMUX_PMCGX_INTENCLR0(a, b) (a)
2689 #define arguments_ODY_SMMUX_PMCGX_INTENCLR0(a, b) (a), (b), -1, -1
2690
2691 /**
2692 * Register (NCB) smmu#_pmcg#_intenset0
2693 *
2694 * SMMU PMCG Interrupt Enable Set Register
2695 */
2696 union ody_smmux_pmcgx_intenset0 {
2697 uint64_t u;
2698 struct ody_smmux_pmcgx_intenset0_s {
2699 uint64_t inten : 4;
2700 uint64_t reserved_4_63 : 60;
2701 } s;
2702 /* struct ody_smmux_pmcgx_intenset0_s cn; */
2703 };
2704 typedef union ody_smmux_pmcgx_intenset0 ody_smmux_pmcgx_intenset0_t;
2705
2706 static inline uint64_t ODY_SMMUX_PMCGX_INTENSET0(uint64_t a, uint64_t b) __attribute__ ((pure, always_inline));
ODY_SMMUX_PMCGX_INTENSET0(uint64_t a,uint64_t b)2707 static inline uint64_t ODY_SMMUX_PMCGX_INTENSET0(uint64_t a, uint64_t b)
2708 {
2709 if ((a <= 3) && (b <= 3))
2710 return 0x830000100c40ll + 0x1000000000ll * ((a) & 0x3) + 0x20000ll * ((b) & 0x3);
2711 __ody_csr_fatal("SMMUX_PMCGX_INTENSET0", 2, a, b, 0, 0, 0, 0);
2712 }
2713
2714 #define typedef_ODY_SMMUX_PMCGX_INTENSET0(a, b) ody_smmux_pmcgx_intenset0_t
2715 #define bustype_ODY_SMMUX_PMCGX_INTENSET0(a, b) CSR_TYPE_NCB
2716 #define basename_ODY_SMMUX_PMCGX_INTENSET0(a, b) "SMMUX_PMCGX_INTENSET0"
2717 #define device_bar_ODY_SMMUX_PMCGX_INTENSET0(a, b) 0x0 /* PF_BAR0 */
2718 #define busnum_ODY_SMMUX_PMCGX_INTENSET0(a, b) (a)
2719 #define arguments_ODY_SMMUX_PMCGX_INTENSET0(a, b) (a), (b), -1, -1
2720
2721 /**
2722 * Register (NCB) smmu#_pmcg#_irq_cfg0
2723 *
2724 * SMMU PMCG MSI Configuration Register
2725 */
2726 union ody_smmux_pmcgx_irq_cfg0 {
2727 uint64_t u;
2728 struct ody_smmux_pmcgx_irq_cfg0_s {
2729 uint64_t reserved_0_1 : 2;
2730 uint64_t addr : 50;
2731 uint64_t reserved_52_63 : 12;
2732 } s;
2733 /* struct ody_smmux_pmcgx_irq_cfg0_s cn; */
2734 };
2735 typedef union ody_smmux_pmcgx_irq_cfg0 ody_smmux_pmcgx_irq_cfg0_t;
2736
2737 static inline uint64_t ODY_SMMUX_PMCGX_IRQ_CFG0(uint64_t a, uint64_t b) __attribute__ ((pure, always_inline));
ODY_SMMUX_PMCGX_IRQ_CFG0(uint64_t a,uint64_t b)2738 static inline uint64_t ODY_SMMUX_PMCGX_IRQ_CFG0(uint64_t a, uint64_t b)
2739 {
2740 if ((a <= 3) && (b <= 3))
2741 return 0x830000100e58ll + 0x1000000000ll * ((a) & 0x3) + 0x20000ll * ((b) & 0x3);
2742 __ody_csr_fatal("SMMUX_PMCGX_IRQ_CFG0", 2, a, b, 0, 0, 0, 0);
2743 }
2744
2745 #define typedef_ODY_SMMUX_PMCGX_IRQ_CFG0(a, b) ody_smmux_pmcgx_irq_cfg0_t
2746 #define bustype_ODY_SMMUX_PMCGX_IRQ_CFG0(a, b) CSR_TYPE_NCB
2747 #define basename_ODY_SMMUX_PMCGX_IRQ_CFG0(a, b) "SMMUX_PMCGX_IRQ_CFG0"
2748 #define device_bar_ODY_SMMUX_PMCGX_IRQ_CFG0(a, b) 0x0 /* PF_BAR0 */
2749 #define busnum_ODY_SMMUX_PMCGX_IRQ_CFG0(a, b) (a)
2750 #define arguments_ODY_SMMUX_PMCGX_IRQ_CFG0(a, b) (a), (b), -1, -1
2751
2752 /**
2753 * Register (NCB32b) smmu#_pmcg#_irq_cfg1
2754 *
2755 * SMMU PMCG MSI Configuration Register
2756 */
2757 union ody_smmux_pmcgx_irq_cfg1 {
2758 uint32_t u;
2759 struct ody_smmux_pmcgx_irq_cfg1_s {
2760 uint32_t data : 32;
2761 } s;
2762 /* struct ody_smmux_pmcgx_irq_cfg1_s cn; */
2763 };
2764 typedef union ody_smmux_pmcgx_irq_cfg1 ody_smmux_pmcgx_irq_cfg1_t;
2765
2766 static inline uint64_t ODY_SMMUX_PMCGX_IRQ_CFG1(uint64_t a, uint64_t b) __attribute__ ((pure, always_inline));
ODY_SMMUX_PMCGX_IRQ_CFG1(uint64_t a,uint64_t b)2767 static inline uint64_t ODY_SMMUX_PMCGX_IRQ_CFG1(uint64_t a, uint64_t b)
2768 {
2769 if ((a <= 3) && (b <= 3))
2770 return 0x830000100e60ll + 0x1000000000ll * ((a) & 0x3) + 0x20000ll * ((b) & 0x3);
2771 __ody_csr_fatal("SMMUX_PMCGX_IRQ_CFG1", 2, a, b, 0, 0, 0, 0);
2772 }
2773
2774 #define typedef_ODY_SMMUX_PMCGX_IRQ_CFG1(a, b) ody_smmux_pmcgx_irq_cfg1_t
2775 #define bustype_ODY_SMMUX_PMCGX_IRQ_CFG1(a, b) CSR_TYPE_NCB32b
2776 #define basename_ODY_SMMUX_PMCGX_IRQ_CFG1(a, b) "SMMUX_PMCGX_IRQ_CFG1"
2777 #define device_bar_ODY_SMMUX_PMCGX_IRQ_CFG1(a, b) 0x0 /* PF_BAR0 */
2778 #define busnum_ODY_SMMUX_PMCGX_IRQ_CFG1(a, b) (a)
2779 #define arguments_ODY_SMMUX_PMCGX_IRQ_CFG1(a, b) (a), (b), -1, -1
2780
2781 /**
2782 * Register (NCB32b) smmu#_pmcg#_irq_cfg2
2783 *
2784 * SMMU PMCG MSI Configuration Register
2785 */
2786 union ody_smmux_pmcgx_irq_cfg2 {
2787 uint32_t u;
2788 struct ody_smmux_pmcgx_irq_cfg2_s {
2789 uint32_t memattr : 4;
2790 uint32_t sh : 2;
2791 uint32_t reserved_6_31 : 26;
2792 } s;
2793 /* struct ody_smmux_pmcgx_irq_cfg2_s cn; */
2794 };
2795 typedef union ody_smmux_pmcgx_irq_cfg2 ody_smmux_pmcgx_irq_cfg2_t;
2796
2797 static inline uint64_t ODY_SMMUX_PMCGX_IRQ_CFG2(uint64_t a, uint64_t b) __attribute__ ((pure, always_inline));
ODY_SMMUX_PMCGX_IRQ_CFG2(uint64_t a,uint64_t b)2798 static inline uint64_t ODY_SMMUX_PMCGX_IRQ_CFG2(uint64_t a, uint64_t b)
2799 {
2800 if ((a <= 3) && (b <= 3))
2801 return 0x830000100e64ll + 0x1000000000ll * ((a) & 0x3) + 0x20000ll * ((b) & 0x3);
2802 __ody_csr_fatal("SMMUX_PMCGX_IRQ_CFG2", 2, a, b, 0, 0, 0, 0);
2803 }
2804
2805 #define typedef_ODY_SMMUX_PMCGX_IRQ_CFG2(a, b) ody_smmux_pmcgx_irq_cfg2_t
2806 #define bustype_ODY_SMMUX_PMCGX_IRQ_CFG2(a, b) CSR_TYPE_NCB32b
2807 #define basename_ODY_SMMUX_PMCGX_IRQ_CFG2(a, b) "SMMUX_PMCGX_IRQ_CFG2"
2808 #define device_bar_ODY_SMMUX_PMCGX_IRQ_CFG2(a, b) 0x0 /* PF_BAR0 */
2809 #define busnum_ODY_SMMUX_PMCGX_IRQ_CFG2(a, b) (a)
2810 #define arguments_ODY_SMMUX_PMCGX_IRQ_CFG2(a, b) (a), (b), -1, -1
2811
2812 /**
2813 * Register (NCB32b) smmu#_pmcg#_irq_ctrl
2814 *
2815 * SMMU PMCG IRQ Enable Register
2816 */
2817 union ody_smmux_pmcgx_irq_ctrl {
2818 uint32_t u;
2819 struct ody_smmux_pmcgx_irq_ctrl_s {
2820 uint32_t irqen : 1;
2821 uint32_t reserved_1_31 : 31;
2822 } s;
2823 /* struct ody_smmux_pmcgx_irq_ctrl_s cn; */
2824 };
2825 typedef union ody_smmux_pmcgx_irq_ctrl ody_smmux_pmcgx_irq_ctrl_t;
2826
2827 static inline uint64_t ODY_SMMUX_PMCGX_IRQ_CTRL(uint64_t a, uint64_t b) __attribute__ ((pure, always_inline));
ODY_SMMUX_PMCGX_IRQ_CTRL(uint64_t a,uint64_t b)2828 static inline uint64_t ODY_SMMUX_PMCGX_IRQ_CTRL(uint64_t a, uint64_t b)
2829 {
2830 if ((a <= 3) && (b <= 3))
2831 return 0x830000100e50ll + 0x1000000000ll * ((a) & 0x3) + 0x20000ll * ((b) & 0x3);
2832 __ody_csr_fatal("SMMUX_PMCGX_IRQ_CTRL", 2, a, b, 0, 0, 0, 0);
2833 }
2834
2835 #define typedef_ODY_SMMUX_PMCGX_IRQ_CTRL(a, b) ody_smmux_pmcgx_irq_ctrl_t
2836 #define bustype_ODY_SMMUX_PMCGX_IRQ_CTRL(a, b) CSR_TYPE_NCB32b
2837 #define basename_ODY_SMMUX_PMCGX_IRQ_CTRL(a, b) "SMMUX_PMCGX_IRQ_CTRL"
2838 #define device_bar_ODY_SMMUX_PMCGX_IRQ_CTRL(a, b) 0x0 /* PF_BAR0 */
2839 #define busnum_ODY_SMMUX_PMCGX_IRQ_CTRL(a, b) (a)
2840 #define arguments_ODY_SMMUX_PMCGX_IRQ_CTRL(a, b) (a), (b), -1, -1
2841
2842 /**
2843 * Register (NCB32b) smmu#_pmcg#_irq_ctrlack
2844 *
2845 * SMMU PMCG IRQ Enable Ack Register
2846 * This register is a read-only copy of SMMU()_PMCG()_IRQ_CTRL.
2847 */
2848 union ody_smmux_pmcgx_irq_ctrlack {
2849 uint32_t u;
2850 struct ody_smmux_pmcgx_irq_ctrlack_s {
2851 uint32_t irqen : 1;
2852 uint32_t reserved_1_31 : 31;
2853 } s;
2854 /* struct ody_smmux_pmcgx_irq_ctrlack_s cn; */
2855 };
2856 typedef union ody_smmux_pmcgx_irq_ctrlack ody_smmux_pmcgx_irq_ctrlack_t;
2857
2858 static inline uint64_t ODY_SMMUX_PMCGX_IRQ_CTRLACK(uint64_t a, uint64_t b) __attribute__ ((pure, always_inline));
ODY_SMMUX_PMCGX_IRQ_CTRLACK(uint64_t a,uint64_t b)2859 static inline uint64_t ODY_SMMUX_PMCGX_IRQ_CTRLACK(uint64_t a, uint64_t b)
2860 {
2861 if ((a <= 3) && (b <= 3))
2862 return 0x830000100e54ll + 0x1000000000ll * ((a) & 0x3) + 0x20000ll * ((b) & 0x3);
2863 __ody_csr_fatal("SMMUX_PMCGX_IRQ_CTRLACK", 2, a, b, 0, 0, 0, 0);
2864 }
2865
2866 #define typedef_ODY_SMMUX_PMCGX_IRQ_CTRLACK(a, b) ody_smmux_pmcgx_irq_ctrlack_t
2867 #define bustype_ODY_SMMUX_PMCGX_IRQ_CTRLACK(a, b) CSR_TYPE_NCB32b
2868 #define basename_ODY_SMMUX_PMCGX_IRQ_CTRLACK(a, b) "SMMUX_PMCGX_IRQ_CTRLACK"
2869 #define device_bar_ODY_SMMUX_PMCGX_IRQ_CTRLACK(a, b) 0x0 /* PF_BAR0 */
2870 #define busnum_ODY_SMMUX_PMCGX_IRQ_CTRLACK(a, b) (a)
2871 #define arguments_ODY_SMMUX_PMCGX_IRQ_CTRLACK(a, b) (a), (b), -1, -1
2872
2873 /**
2874 * Register (NCB32b) smmu#_pmcg#_irq_status
2875 *
2876 * SMMU PMCG MSI Status Register
2877 */
2878 union ody_smmux_pmcgx_irq_status {
2879 uint32_t u;
2880 struct ody_smmux_pmcgx_irq_status_s {
2881 uint32_t irq_abt : 1;
2882 uint32_t reserved_1_31 : 31;
2883 } s;
2884 /* struct ody_smmux_pmcgx_irq_status_s cn; */
2885 };
2886 typedef union ody_smmux_pmcgx_irq_status ody_smmux_pmcgx_irq_status_t;
2887
2888 static inline uint64_t ODY_SMMUX_PMCGX_IRQ_STATUS(uint64_t a, uint64_t b) __attribute__ ((pure, always_inline));
ODY_SMMUX_PMCGX_IRQ_STATUS(uint64_t a,uint64_t b)2889 static inline uint64_t ODY_SMMUX_PMCGX_IRQ_STATUS(uint64_t a, uint64_t b)
2890 {
2891 if ((a <= 3) && (b <= 3))
2892 return 0x830000100e68ll + 0x1000000000ll * ((a) & 0x3) + 0x20000ll * ((b) & 0x3);
2893 __ody_csr_fatal("SMMUX_PMCGX_IRQ_STATUS", 2, a, b, 0, 0, 0, 0);
2894 }
2895
2896 #define typedef_ODY_SMMUX_PMCGX_IRQ_STATUS(a, b) ody_smmux_pmcgx_irq_status_t
2897 #define bustype_ODY_SMMUX_PMCGX_IRQ_STATUS(a, b) CSR_TYPE_NCB32b
2898 #define basename_ODY_SMMUX_PMCGX_IRQ_STATUS(a, b) "SMMUX_PMCGX_IRQ_STATUS"
2899 #define device_bar_ODY_SMMUX_PMCGX_IRQ_STATUS(a, b) 0x0 /* PF_BAR0 */
2900 #define busnum_ODY_SMMUX_PMCGX_IRQ_STATUS(a, b) (a)
2901 #define arguments_ODY_SMMUX_PMCGX_IRQ_STATUS(a, b) (a), (b), -1, -1
2902
2903 /**
2904 * Register (NCB32b) smmu#_pmcg#_mpamidr
2905 *
2906 * PMCG MPAM capability identification Register
2907 */
2908 union ody_smmux_pmcgx_mpamidr {
2909 uint32_t u;
2910 struct ody_smmux_pmcgx_mpamidr_s {
2911 uint32_t partid_max : 16;
2912 uint32_t pmg_max : 8;
2913 uint32_t reserved_24_31 : 8;
2914 } s;
2915 /* struct ody_smmux_pmcgx_mpamidr_s cn; */
2916 };
2917 typedef union ody_smmux_pmcgx_mpamidr ody_smmux_pmcgx_mpamidr_t;
2918
2919 static inline uint64_t ODY_SMMUX_PMCGX_MPAMIDR(uint64_t a, uint64_t b) __attribute__ ((pure, always_inline));
ODY_SMMUX_PMCGX_MPAMIDR(uint64_t a,uint64_t b)2920 static inline uint64_t ODY_SMMUX_PMCGX_MPAMIDR(uint64_t a, uint64_t b)
2921 {
2922 if ((a <= 3) && (b <= 3))
2923 return 0x830000100e74ll + 0x1000000000ll * ((a) & 0x3) + 0x20000ll * ((b) & 0x3);
2924 __ody_csr_fatal("SMMUX_PMCGX_MPAMIDR", 2, a, b, 0, 0, 0, 0);
2925 }
2926
2927 #define typedef_ODY_SMMUX_PMCGX_MPAMIDR(a, b) ody_smmux_pmcgx_mpamidr_t
2928 #define bustype_ODY_SMMUX_PMCGX_MPAMIDR(a, b) CSR_TYPE_NCB32b
2929 #define basename_ODY_SMMUX_PMCGX_MPAMIDR(a, b) "SMMUX_PMCGX_MPAMIDR"
2930 #define device_bar_ODY_SMMUX_PMCGX_MPAMIDR(a, b) 0x0 /* PF_BAR0 */
2931 #define busnum_ODY_SMMUX_PMCGX_MPAMIDR(a, b) (a)
2932 #define arguments_ODY_SMMUX_PMCGX_MPAMIDR(a, b) (a), (b), -1, -1
2933
2934 /**
2935 * Register (NCB) smmu#_pmcg#_ovsclr0
2936 *
2937 * SMMU PMCG Overflow Status Clear Register
2938 */
2939 union ody_smmux_pmcgx_ovsclr0 {
2940 uint64_t u;
2941 struct ody_smmux_pmcgx_ovsclr0_s {
2942 uint64_t ovs : 4;
2943 uint64_t reserved_4_63 : 60;
2944 } s;
2945 /* struct ody_smmux_pmcgx_ovsclr0_s cn; */
2946 };
2947 typedef union ody_smmux_pmcgx_ovsclr0 ody_smmux_pmcgx_ovsclr0_t;
2948
2949 static inline uint64_t ODY_SMMUX_PMCGX_OVSCLR0(uint64_t a, uint64_t b) __attribute__ ((pure, always_inline));
ODY_SMMUX_PMCGX_OVSCLR0(uint64_t a,uint64_t b)2950 static inline uint64_t ODY_SMMUX_PMCGX_OVSCLR0(uint64_t a, uint64_t b)
2951 {
2952 if ((a <= 3) && (b <= 3))
2953 return 0x830000110c80ll + 0x1000000000ll * ((a) & 0x3) + 0x20000ll * ((b) & 0x3);
2954 __ody_csr_fatal("SMMUX_PMCGX_OVSCLR0", 2, a, b, 0, 0, 0, 0);
2955 }
2956
2957 #define typedef_ODY_SMMUX_PMCGX_OVSCLR0(a, b) ody_smmux_pmcgx_ovsclr0_t
2958 #define bustype_ODY_SMMUX_PMCGX_OVSCLR0(a, b) CSR_TYPE_NCB
2959 #define basename_ODY_SMMUX_PMCGX_OVSCLR0(a, b) "SMMUX_PMCGX_OVSCLR0"
2960 #define device_bar_ODY_SMMUX_PMCGX_OVSCLR0(a, b) 0x0 /* PF_BAR0 */
2961 #define busnum_ODY_SMMUX_PMCGX_OVSCLR0(a, b) (a)
2962 #define arguments_ODY_SMMUX_PMCGX_OVSCLR0(a, b) (a), (b), -1, -1
2963
2964 /**
2965 * Register (NCB) smmu#_pmcg#_ovsset0
2966 *
2967 * SMMU PMCG Overflow Status Set Register
2968 */
2969 union ody_smmux_pmcgx_ovsset0 {
2970 uint64_t u;
2971 struct ody_smmux_pmcgx_ovsset0_s {
2972 uint64_t ovs : 4;
2973 uint64_t reserved_4_63 : 60;
2974 } s;
2975 /* struct ody_smmux_pmcgx_ovsset0_s cn; */
2976 };
2977 typedef union ody_smmux_pmcgx_ovsset0 ody_smmux_pmcgx_ovsset0_t;
2978
2979 static inline uint64_t ODY_SMMUX_PMCGX_OVSSET0(uint64_t a, uint64_t b) __attribute__ ((pure, always_inline));
ODY_SMMUX_PMCGX_OVSSET0(uint64_t a,uint64_t b)2980 static inline uint64_t ODY_SMMUX_PMCGX_OVSSET0(uint64_t a, uint64_t b)
2981 {
2982 if ((a <= 3) && (b <= 3))
2983 return 0x830000110cc0ll + 0x1000000000ll * ((a) & 0x3) + 0x20000ll * ((b) & 0x3);
2984 __ody_csr_fatal("SMMUX_PMCGX_OVSSET0", 2, a, b, 0, 0, 0, 0);
2985 }
2986
2987 #define typedef_ODY_SMMUX_PMCGX_OVSSET0(a, b) ody_smmux_pmcgx_ovsset0_t
2988 #define bustype_ODY_SMMUX_PMCGX_OVSSET0(a, b) CSR_TYPE_NCB
2989 #define basename_ODY_SMMUX_PMCGX_OVSSET0(a, b) "SMMUX_PMCGX_OVSSET0"
2990 #define device_bar_ODY_SMMUX_PMCGX_OVSSET0(a, b) 0x0 /* PF_BAR0 */
2991 #define busnum_ODY_SMMUX_PMCGX_OVSSET0(a, b) (a)
2992 #define arguments_ODY_SMMUX_PMCGX_OVSSET0(a, b) (a), (b), -1, -1
2993
2994 /**
2995 * Register (NCB32b) smmu#_pmcg#_pidr0
2996 *
2997 * SMMU Peripheral Identification Register 0
2998 */
2999 union ody_smmux_pmcgx_pidr0 {
3000 uint32_t u;
3001 struct ody_smmux_pmcgx_pidr0_s {
3002 uint32_t partnum0 : 8;
3003 uint32_t reserved_8_31 : 24;
3004 } s;
3005 /* struct ody_smmux_pmcgx_pidr0_s cn; */
3006 };
3007 typedef union ody_smmux_pmcgx_pidr0 ody_smmux_pmcgx_pidr0_t;
3008
3009 static inline uint64_t ODY_SMMUX_PMCGX_PIDR0(uint64_t a, uint64_t b) __attribute__ ((pure, always_inline));
ODY_SMMUX_PMCGX_PIDR0(uint64_t a,uint64_t b)3010 static inline uint64_t ODY_SMMUX_PMCGX_PIDR0(uint64_t a, uint64_t b)
3011 {
3012 if ((a <= 3) && (b <= 3))
3013 return 0x830000100fe0ll + 0x1000000000ll * ((a) & 0x3) + 0x20000ll * ((b) & 0x3);
3014 __ody_csr_fatal("SMMUX_PMCGX_PIDR0", 2, a, b, 0, 0, 0, 0);
3015 }
3016
3017 #define typedef_ODY_SMMUX_PMCGX_PIDR0(a, b) ody_smmux_pmcgx_pidr0_t
3018 #define bustype_ODY_SMMUX_PMCGX_PIDR0(a, b) CSR_TYPE_NCB32b
3019 #define basename_ODY_SMMUX_PMCGX_PIDR0(a, b) "SMMUX_PMCGX_PIDR0"
3020 #define device_bar_ODY_SMMUX_PMCGX_PIDR0(a, b) 0x0 /* PF_BAR0 */
3021 #define busnum_ODY_SMMUX_PMCGX_PIDR0(a, b) (a)
3022 #define arguments_ODY_SMMUX_PMCGX_PIDR0(a, b) (a), (b), -1, -1
3023
3024 /**
3025 * Register (NCB32b) smmu#_pmcg#_pidr1
3026 *
3027 * SMMU Peripheral Identification Register 1
3028 */
3029 union ody_smmux_pmcgx_pidr1 {
3030 uint32_t u;
3031 struct ody_smmux_pmcgx_pidr1_s {
3032 uint32_t partnum1 : 4;
3033 uint32_t idcode : 4;
3034 uint32_t reserved_8_31 : 24;
3035 } s;
3036 /* struct ody_smmux_pmcgx_pidr1_s cn; */
3037 };
3038 typedef union ody_smmux_pmcgx_pidr1 ody_smmux_pmcgx_pidr1_t;
3039
3040 static inline uint64_t ODY_SMMUX_PMCGX_PIDR1(uint64_t a, uint64_t b) __attribute__ ((pure, always_inline));
ODY_SMMUX_PMCGX_PIDR1(uint64_t a,uint64_t b)3041 static inline uint64_t ODY_SMMUX_PMCGX_PIDR1(uint64_t a, uint64_t b)
3042 {
3043 if ((a <= 3) && (b <= 3))
3044 return 0x830000100fe4ll + 0x1000000000ll * ((a) & 0x3) + 0x20000ll * ((b) & 0x3);
3045 __ody_csr_fatal("SMMUX_PMCGX_PIDR1", 2, a, b, 0, 0, 0, 0);
3046 }
3047
3048 #define typedef_ODY_SMMUX_PMCGX_PIDR1(a, b) ody_smmux_pmcgx_pidr1_t
3049 #define bustype_ODY_SMMUX_PMCGX_PIDR1(a, b) CSR_TYPE_NCB32b
3050 #define basename_ODY_SMMUX_PMCGX_PIDR1(a, b) "SMMUX_PMCGX_PIDR1"
3051 #define device_bar_ODY_SMMUX_PMCGX_PIDR1(a, b) 0x0 /* PF_BAR0 */
3052 #define busnum_ODY_SMMUX_PMCGX_PIDR1(a, b) (a)
3053 #define arguments_ODY_SMMUX_PMCGX_PIDR1(a, b) (a), (b), -1, -1
3054
3055 /**
3056 * Register (NCB32b) smmu#_pmcg#_pidr2
3057 *
3058 * SMMU Peripheral Identification Register 2
3059 */
3060 union ody_smmux_pmcgx_pidr2 {
3061 uint32_t u;
3062 struct ody_smmux_pmcgx_pidr2_s {
3063 uint32_t idcode : 3;
3064 uint32_t jedec : 1;
3065 uint32_t revision : 4;
3066 uint32_t reserved_8_31 : 24;
3067 } s;
3068 /* struct ody_smmux_pmcgx_pidr2_s cn; */
3069 };
3070 typedef union ody_smmux_pmcgx_pidr2 ody_smmux_pmcgx_pidr2_t;
3071
3072 static inline uint64_t ODY_SMMUX_PMCGX_PIDR2(uint64_t a, uint64_t b) __attribute__ ((pure, always_inline));
ODY_SMMUX_PMCGX_PIDR2(uint64_t a,uint64_t b)3073 static inline uint64_t ODY_SMMUX_PMCGX_PIDR2(uint64_t a, uint64_t b)
3074 {
3075 if ((a <= 3) && (b <= 3))
3076 return 0x830000100fe8ll + 0x1000000000ll * ((a) & 0x3) + 0x20000ll * ((b) & 0x3);
3077 __ody_csr_fatal("SMMUX_PMCGX_PIDR2", 2, a, b, 0, 0, 0, 0);
3078 }
3079
3080 #define typedef_ODY_SMMUX_PMCGX_PIDR2(a, b) ody_smmux_pmcgx_pidr2_t
3081 #define bustype_ODY_SMMUX_PMCGX_PIDR2(a, b) CSR_TYPE_NCB32b
3082 #define basename_ODY_SMMUX_PMCGX_PIDR2(a, b) "SMMUX_PMCGX_PIDR2"
3083 #define device_bar_ODY_SMMUX_PMCGX_PIDR2(a, b) 0x0 /* PF_BAR0 */
3084 #define busnum_ODY_SMMUX_PMCGX_PIDR2(a, b) (a)
3085 #define arguments_ODY_SMMUX_PMCGX_PIDR2(a, b) (a), (b), -1, -1
3086
3087 /**
3088 * Register (NCB32b) smmu#_pmcg#_pidr3
3089 *
3090 * SMMU Peripheral Identification Register 3
3091 */
3092 union ody_smmux_pmcgx_pidr3 {
3093 uint32_t u;
3094 struct ody_smmux_pmcgx_pidr3_s {
3095 uint32_t cust : 4;
3096 uint32_t revand : 4;
3097 uint32_t reserved_8_31 : 24;
3098 } s;
3099 /* struct ody_smmux_pmcgx_pidr3_s cn; */
3100 };
3101 typedef union ody_smmux_pmcgx_pidr3 ody_smmux_pmcgx_pidr3_t;
3102
3103 static inline uint64_t ODY_SMMUX_PMCGX_PIDR3(uint64_t a, uint64_t b) __attribute__ ((pure, always_inline));
ODY_SMMUX_PMCGX_PIDR3(uint64_t a,uint64_t b)3104 static inline uint64_t ODY_SMMUX_PMCGX_PIDR3(uint64_t a, uint64_t b)
3105 {
3106 if ((a <= 3) && (b <= 3))
3107 return 0x830000100fecll + 0x1000000000ll * ((a) & 0x3) + 0x20000ll * ((b) & 0x3);
3108 __ody_csr_fatal("SMMUX_PMCGX_PIDR3", 2, a, b, 0, 0, 0, 0);
3109 }
3110
3111 #define typedef_ODY_SMMUX_PMCGX_PIDR3(a, b) ody_smmux_pmcgx_pidr3_t
3112 #define bustype_ODY_SMMUX_PMCGX_PIDR3(a, b) CSR_TYPE_NCB32b
3113 #define basename_ODY_SMMUX_PMCGX_PIDR3(a, b) "SMMUX_PMCGX_PIDR3"
3114 #define device_bar_ODY_SMMUX_PMCGX_PIDR3(a, b) 0x0 /* PF_BAR0 */
3115 #define busnum_ODY_SMMUX_PMCGX_PIDR3(a, b) (a)
3116 #define arguments_ODY_SMMUX_PMCGX_PIDR3(a, b) (a), (b), -1, -1
3117
3118 /**
3119 * Register (NCB32b) smmu#_pmcg#_pidr4
3120 *
3121 * SMMU Peripheral Identification Register 4
3122 */
3123 union ody_smmux_pmcgx_pidr4 {
3124 uint32_t u;
3125 struct ody_smmux_pmcgx_pidr4_s {
3126 uint32_t jepcont : 4;
3127 uint32_t pagecnt : 4;
3128 uint32_t reserved_8_31 : 24;
3129 } s;
3130 /* struct ody_smmux_pmcgx_pidr4_s cn; */
3131 };
3132 typedef union ody_smmux_pmcgx_pidr4 ody_smmux_pmcgx_pidr4_t;
3133
3134 static inline uint64_t ODY_SMMUX_PMCGX_PIDR4(uint64_t a, uint64_t b) __attribute__ ((pure, always_inline));
ODY_SMMUX_PMCGX_PIDR4(uint64_t a,uint64_t b)3135 static inline uint64_t ODY_SMMUX_PMCGX_PIDR4(uint64_t a, uint64_t b)
3136 {
3137 if ((a <= 3) && (b <= 3))
3138 return 0x830000100fd0ll + 0x1000000000ll * ((a) & 0x3) + 0x20000ll * ((b) & 0x3);
3139 __ody_csr_fatal("SMMUX_PMCGX_PIDR4", 2, a, b, 0, 0, 0, 0);
3140 }
3141
3142 #define typedef_ODY_SMMUX_PMCGX_PIDR4(a, b) ody_smmux_pmcgx_pidr4_t
3143 #define bustype_ODY_SMMUX_PMCGX_PIDR4(a, b) CSR_TYPE_NCB32b
3144 #define basename_ODY_SMMUX_PMCGX_PIDR4(a, b) "SMMUX_PMCGX_PIDR4"
3145 #define device_bar_ODY_SMMUX_PMCGX_PIDR4(a, b) 0x0 /* PF_BAR0 */
3146 #define busnum_ODY_SMMUX_PMCGX_PIDR4(a, b) (a)
3147 #define arguments_ODY_SMMUX_PMCGX_PIDR4(a, b) (a), (b), -1, -1
3148
3149 /**
3150 * Register (NCB32b) smmu#_pmcg#_pidr5
3151 *
3152 * SMMU Peripheral Identification Register 5
3153 */
3154 union ody_smmux_pmcgx_pidr5 {
3155 uint32_t u;
3156 struct ody_smmux_pmcgx_pidr5_s {
3157 uint32_t reserved_0_31 : 32;
3158 } s;
3159 /* struct ody_smmux_pmcgx_pidr5_s cn; */
3160 };
3161 typedef union ody_smmux_pmcgx_pidr5 ody_smmux_pmcgx_pidr5_t;
3162
3163 static inline uint64_t ODY_SMMUX_PMCGX_PIDR5(uint64_t a, uint64_t b) __attribute__ ((pure, always_inline));
ODY_SMMUX_PMCGX_PIDR5(uint64_t a,uint64_t b)3164 static inline uint64_t ODY_SMMUX_PMCGX_PIDR5(uint64_t a, uint64_t b)
3165 {
3166 if ((a <= 3) && (b <= 3))
3167 return 0x830000100fd4ll + 0x1000000000ll * ((a) & 0x3) + 0x20000ll * ((b) & 0x3);
3168 __ody_csr_fatal("SMMUX_PMCGX_PIDR5", 2, a, b, 0, 0, 0, 0);
3169 }
3170
3171 #define typedef_ODY_SMMUX_PMCGX_PIDR5(a, b) ody_smmux_pmcgx_pidr5_t
3172 #define bustype_ODY_SMMUX_PMCGX_PIDR5(a, b) CSR_TYPE_NCB32b
3173 #define basename_ODY_SMMUX_PMCGX_PIDR5(a, b) "SMMUX_PMCGX_PIDR5"
3174 #define device_bar_ODY_SMMUX_PMCGX_PIDR5(a, b) 0x0 /* PF_BAR0 */
3175 #define busnum_ODY_SMMUX_PMCGX_PIDR5(a, b) (a)
3176 #define arguments_ODY_SMMUX_PMCGX_PIDR5(a, b) (a), (b), -1, -1
3177
3178 /**
3179 * Register (NCB32b) smmu#_pmcg#_pidr6
3180 *
3181 * SMMU Peripheral Identification Register 6
3182 */
3183 union ody_smmux_pmcgx_pidr6 {
3184 uint32_t u;
3185 struct ody_smmux_pmcgx_pidr6_s {
3186 uint32_t reserved_0_31 : 32;
3187 } s;
3188 /* struct ody_smmux_pmcgx_pidr6_s cn; */
3189 };
3190 typedef union ody_smmux_pmcgx_pidr6 ody_smmux_pmcgx_pidr6_t;
3191
3192 static inline uint64_t ODY_SMMUX_PMCGX_PIDR6(uint64_t a, uint64_t b) __attribute__ ((pure, always_inline));
ODY_SMMUX_PMCGX_PIDR6(uint64_t a,uint64_t b)3193 static inline uint64_t ODY_SMMUX_PMCGX_PIDR6(uint64_t a, uint64_t b)
3194 {
3195 if ((a <= 3) && (b <= 3))
3196 return 0x830000100fd8ll + 0x1000000000ll * ((a) & 0x3) + 0x20000ll * ((b) & 0x3);
3197 __ody_csr_fatal("SMMUX_PMCGX_PIDR6", 2, a, b, 0, 0, 0, 0);
3198 }
3199
3200 #define typedef_ODY_SMMUX_PMCGX_PIDR6(a, b) ody_smmux_pmcgx_pidr6_t
3201 #define bustype_ODY_SMMUX_PMCGX_PIDR6(a, b) CSR_TYPE_NCB32b
3202 #define basename_ODY_SMMUX_PMCGX_PIDR6(a, b) "SMMUX_PMCGX_PIDR6"
3203 #define device_bar_ODY_SMMUX_PMCGX_PIDR6(a, b) 0x0 /* PF_BAR0 */
3204 #define busnum_ODY_SMMUX_PMCGX_PIDR6(a, b) (a)
3205 #define arguments_ODY_SMMUX_PMCGX_PIDR6(a, b) (a), (b), -1, -1
3206
3207 /**
3208 * Register (NCB32b) smmu#_pmcg#_pidr7
3209 *
3210 * SMMU Peripheral Identification Register 7
3211 */
3212 union ody_smmux_pmcgx_pidr7 {
3213 uint32_t u;
3214 struct ody_smmux_pmcgx_pidr7_s {
3215 uint32_t reserved_0_31 : 32;
3216 } s;
3217 /* struct ody_smmux_pmcgx_pidr7_s cn; */
3218 };
3219 typedef union ody_smmux_pmcgx_pidr7 ody_smmux_pmcgx_pidr7_t;
3220
3221 static inline uint64_t ODY_SMMUX_PMCGX_PIDR7(uint64_t a, uint64_t b) __attribute__ ((pure, always_inline));
ODY_SMMUX_PMCGX_PIDR7(uint64_t a,uint64_t b)3222 static inline uint64_t ODY_SMMUX_PMCGX_PIDR7(uint64_t a, uint64_t b)
3223 {
3224 if ((a <= 3) && (b <= 3))
3225 return 0x830000100fdcll + 0x1000000000ll * ((a) & 0x3) + 0x20000ll * ((b) & 0x3);
3226 __ody_csr_fatal("SMMUX_PMCGX_PIDR7", 2, a, b, 0, 0, 0, 0);
3227 }
3228
3229 #define typedef_ODY_SMMUX_PMCGX_PIDR7(a, b) ody_smmux_pmcgx_pidr7_t
3230 #define bustype_ODY_SMMUX_PMCGX_PIDR7(a, b) CSR_TYPE_NCB32b
3231 #define basename_ODY_SMMUX_PMCGX_PIDR7(a, b) "SMMUX_PMCGX_PIDR7"
3232 #define device_bar_ODY_SMMUX_PMCGX_PIDR7(a, b) 0x0 /* PF_BAR0 */
3233 #define busnum_ODY_SMMUX_PMCGX_PIDR7(a, b) (a)
3234 #define arguments_ODY_SMMUX_PMCGX_PIDR7(a, b) (a), (b), -1, -1
3235
3236 /**
3237 * Register (NCB32b) smmu#_pmcg#_pmauthstatus
3238 *
3239 * Performance Monitor Authentication Status Register
3240 */
3241 union ody_smmux_pmcgx_pmauthstatus {
3242 uint32_t u;
3243 struct ody_smmux_pmcgx_pmauthstatus_s {
3244 uint32_t reserved_0_31 : 32;
3245 } s;
3246 /* struct ody_smmux_pmcgx_pmauthstatus_s cn; */
3247 };
3248 typedef union ody_smmux_pmcgx_pmauthstatus ody_smmux_pmcgx_pmauthstatus_t;
3249
3250 static inline uint64_t ODY_SMMUX_PMCGX_PMAUTHSTATUS(uint64_t a, uint64_t b) __attribute__ ((pure, always_inline));
ODY_SMMUX_PMCGX_PMAUTHSTATUS(uint64_t a,uint64_t b)3251 static inline uint64_t ODY_SMMUX_PMCGX_PMAUTHSTATUS(uint64_t a, uint64_t b)
3252 {
3253 if ((a <= 3) && (b <= 3))
3254 return 0x830000100fb8ll + 0x1000000000ll * ((a) & 0x3) + 0x20000ll * ((b) & 0x3);
3255 __ody_csr_fatal("SMMUX_PMCGX_PMAUTHSTATUS", 2, a, b, 0, 0, 0, 0);
3256 }
3257
3258 #define typedef_ODY_SMMUX_PMCGX_PMAUTHSTATUS(a, b) ody_smmux_pmcgx_pmauthstatus_t
3259 #define bustype_ODY_SMMUX_PMCGX_PMAUTHSTATUS(a, b) CSR_TYPE_NCB32b
3260 #define basename_ODY_SMMUX_PMCGX_PMAUTHSTATUS(a, b) "SMMUX_PMCGX_PMAUTHSTATUS"
3261 #define device_bar_ODY_SMMUX_PMCGX_PMAUTHSTATUS(a, b) 0x0 /* PF_BAR0 */
3262 #define busnum_ODY_SMMUX_PMCGX_PMAUTHSTATUS(a, b) (a)
3263 #define arguments_ODY_SMMUX_PMCGX_PMAUTHSTATUS(a, b) (a), (b), -1, -1
3264
3265 /**
3266 * Register (NCB32b) smmu#_pmcg#_pmdevarch
3267 *
3268 * Performance Monitor Device Architecture Register
3269 */
3270 union ody_smmux_pmcgx_pmdevarch {
3271 uint32_t u;
3272 struct ody_smmux_pmcgx_pmdevarch_s {
3273 uint32_t archid : 16;
3274 uint32_t revision : 4;
3275 uint32_t present : 1;
3276 uint32_t architect : 11;
3277 } s;
3278 /* struct ody_smmux_pmcgx_pmdevarch_s cn; */
3279 };
3280 typedef union ody_smmux_pmcgx_pmdevarch ody_smmux_pmcgx_pmdevarch_t;
3281
3282 static inline uint64_t ODY_SMMUX_PMCGX_PMDEVARCH(uint64_t a, uint64_t b) __attribute__ ((pure, always_inline));
ODY_SMMUX_PMCGX_PMDEVARCH(uint64_t a,uint64_t b)3283 static inline uint64_t ODY_SMMUX_PMCGX_PMDEVARCH(uint64_t a, uint64_t b)
3284 {
3285 if ((a <= 3) && (b <= 3))
3286 return 0x830000100fbcll + 0x1000000000ll * ((a) & 0x3) + 0x20000ll * ((b) & 0x3);
3287 __ody_csr_fatal("SMMUX_PMCGX_PMDEVARCH", 2, a, b, 0, 0, 0, 0);
3288 }
3289
3290 #define typedef_ODY_SMMUX_PMCGX_PMDEVARCH(a, b) ody_smmux_pmcgx_pmdevarch_t
3291 #define bustype_ODY_SMMUX_PMCGX_PMDEVARCH(a, b) CSR_TYPE_NCB32b
3292 #define basename_ODY_SMMUX_PMCGX_PMDEVARCH(a, b) "SMMUX_PMCGX_PMDEVARCH"
3293 #define device_bar_ODY_SMMUX_PMCGX_PMDEVARCH(a, b) 0x0 /* PF_BAR0 */
3294 #define busnum_ODY_SMMUX_PMCGX_PMDEVARCH(a, b) (a)
3295 #define arguments_ODY_SMMUX_PMCGX_PMDEVARCH(a, b) (a), (b), -1, -1
3296
3297 /**
3298 * Register (NCB32b) smmu#_pmcg#_pmdevtype
3299 *
3300 * Performance Monitor Device Type Register
3301 */
3302 union ody_smmux_pmcgx_pmdevtype {
3303 uint32_t u;
3304 struct ody_smmux_pmcgx_pmdevtype_s {
3305 uint32_t device_class : 4;
3306 uint32_t subtype : 4;
3307 uint32_t reserved_8_31 : 24;
3308 } s;
3309 /* struct ody_smmux_pmcgx_pmdevtype_s cn; */
3310 };
3311 typedef union ody_smmux_pmcgx_pmdevtype ody_smmux_pmcgx_pmdevtype_t;
3312
3313 static inline uint64_t ODY_SMMUX_PMCGX_PMDEVTYPE(uint64_t a, uint64_t b) __attribute__ ((pure, always_inline));
ODY_SMMUX_PMCGX_PMDEVTYPE(uint64_t a,uint64_t b)3314 static inline uint64_t ODY_SMMUX_PMCGX_PMDEVTYPE(uint64_t a, uint64_t b)
3315 {
3316 if ((a <= 3) && (b <= 3))
3317 return 0x830000100fccll + 0x1000000000ll * ((a) & 0x3) + 0x20000ll * ((b) & 0x3);
3318 __ody_csr_fatal("SMMUX_PMCGX_PMDEVTYPE", 2, a, b, 0, 0, 0, 0);
3319 }
3320
3321 #define typedef_ODY_SMMUX_PMCGX_PMDEVTYPE(a, b) ody_smmux_pmcgx_pmdevtype_t
3322 #define bustype_ODY_SMMUX_PMCGX_PMDEVTYPE(a, b) CSR_TYPE_NCB32b
3323 #define basename_ODY_SMMUX_PMCGX_PMDEVTYPE(a, b) "SMMUX_PMCGX_PMDEVTYPE"
3324 #define device_bar_ODY_SMMUX_PMCGX_PMDEVTYPE(a, b) 0x0 /* PF_BAR0 */
3325 #define busnum_ODY_SMMUX_PMCGX_PMDEVTYPE(a, b) (a)
3326 #define arguments_ODY_SMMUX_PMCGX_PMDEVTYPE(a, b) (a), (b), -1, -1
3327
3328 /**
3329 * Register (NCB32b) smmu#_pmcg#_scr
3330 *
3331 * SMMU PMCG Secure Control Register
3332 */
3333 union ody_smmux_pmcgx_scr {
3334 uint32_t u;
3335 struct ody_smmux_pmcgx_scr_s {
3336 uint32_t so : 1;
3337 uint32_t nsra : 1;
3338 uint32_t nsmsi : 1;
3339 uint32_t msi_mpam_ns : 1;
3340 uint32_t reserved_4_30 : 27;
3341 uint32_t valid : 1;
3342 } s;
3343 /* struct ody_smmux_pmcgx_scr_s cn; */
3344 };
3345 typedef union ody_smmux_pmcgx_scr ody_smmux_pmcgx_scr_t;
3346
3347 static inline uint64_t ODY_SMMUX_PMCGX_SCR(uint64_t a, uint64_t b) __attribute__ ((pure, always_inline));
ODY_SMMUX_PMCGX_SCR(uint64_t a,uint64_t b)3348 static inline uint64_t ODY_SMMUX_PMCGX_SCR(uint64_t a, uint64_t b)
3349 {
3350 if ((a <= 3) && (b <= 3))
3351 return 0x830000100df8ll + 0x1000000000ll * ((a) & 0x3) + 0x20000ll * ((b) & 0x3);
3352 __ody_csr_fatal("SMMUX_PMCGX_SCR", 2, a, b, 0, 0, 0, 0);
3353 }
3354
3355 #define typedef_ODY_SMMUX_PMCGX_SCR(a, b) ody_smmux_pmcgx_scr_t
3356 #define bustype_ODY_SMMUX_PMCGX_SCR(a, b) CSR_TYPE_NCB32b
3357 #define basename_ODY_SMMUX_PMCGX_SCR(a, b) "SMMUX_PMCGX_SCR"
3358 #define device_bar_ODY_SMMUX_PMCGX_SCR(a, b) 0x0 /* PF_BAR0 */
3359 #define busnum_ODY_SMMUX_PMCGX_SCR(a, b) (a)
3360 #define arguments_ODY_SMMUX_PMCGX_SCR(a, b) (a), (b), -1, -1
3361
3362 /**
3363 * Register (NCB32b) smmu#_pmcg#_smr#
3364 *
3365 * SMMU PMCG Counter Stream Match Filter Register
3366 */
3367 union ody_smmux_pmcgx_smrx {
3368 uint32_t u;
3369 struct ody_smmux_pmcgx_smrx_s {
3370 uint32_t streamid : 22;
3371 uint32_t reserved_22_31 : 10;
3372 } s;
3373 /* struct ody_smmux_pmcgx_smrx_s cn; */
3374 };
3375 typedef union ody_smmux_pmcgx_smrx ody_smmux_pmcgx_smrx_t;
3376
3377 static inline uint64_t ODY_SMMUX_PMCGX_SMRX(uint64_t a, uint64_t b, uint64_t c) __attribute__ ((pure, always_inline));
ODY_SMMUX_PMCGX_SMRX(uint64_t a,uint64_t b,uint64_t c)3378 static inline uint64_t ODY_SMMUX_PMCGX_SMRX(uint64_t a, uint64_t b, uint64_t c)
3379 {
3380 if ((a <= 3) && (b <= 3) && (c == 0))
3381 return 0x830000100a00ll + 0x1000000000ll * ((a) & 0x3) + 0x20000ll * ((b) & 0x3);
3382 __ody_csr_fatal("SMMUX_PMCGX_SMRX", 3, a, b, c, 0, 0, 0);
3383 }
3384
3385 #define typedef_ODY_SMMUX_PMCGX_SMRX(a, b, c) ody_smmux_pmcgx_smrx_t
3386 #define bustype_ODY_SMMUX_PMCGX_SMRX(a, b, c) CSR_TYPE_NCB32b
3387 #define basename_ODY_SMMUX_PMCGX_SMRX(a, b, c) "SMMUX_PMCGX_SMRX"
3388 #define device_bar_ODY_SMMUX_PMCGX_SMRX(a, b, c) 0x0 /* PF_BAR0 */
3389 #define busnum_ODY_SMMUX_PMCGX_SMRX(a, b, c) (a)
3390 #define arguments_ODY_SMMUX_PMCGX_SMRX(a, b, c) (a), (b), (c), -1
3391
3392 /**
3393 * Register (NCB) smmu#_pmcg#_svr#
3394 *
3395 * SMMU PMCG Counter Shadow Value Register
3396 */
3397 union ody_smmux_pmcgx_svrx {
3398 uint64_t u;
3399 struct ody_smmux_pmcgx_svrx_s {
3400 uint64_t reserved_0_63 : 64;
3401 } s;
3402 /* struct ody_smmux_pmcgx_svrx_s cn; */
3403 };
3404 typedef union ody_smmux_pmcgx_svrx ody_smmux_pmcgx_svrx_t;
3405
3406 static inline uint64_t ODY_SMMUX_PMCGX_SVRX(uint64_t a, uint64_t b, uint64_t c) __attribute__ ((pure, always_inline));
ODY_SMMUX_PMCGX_SVRX(uint64_t a,uint64_t b,uint64_t c)3407 static inline uint64_t ODY_SMMUX_PMCGX_SVRX(uint64_t a, uint64_t b, uint64_t c)
3408 {
3409 if ((a <= 3) && (b <= 3) && (c == 0))
3410 return 0x830000100600ll + 0x1000000000ll * ((a) & 0x3) + 0x20000ll * ((b) & 0x3);
3411 __ody_csr_fatal("SMMUX_PMCGX_SVRX", 3, a, b, c, 0, 0, 0);
3412 }
3413
3414 #define typedef_ODY_SMMUX_PMCGX_SVRX(a, b, c) ody_smmux_pmcgx_svrx_t
3415 #define bustype_ODY_SMMUX_PMCGX_SVRX(a, b, c) CSR_TYPE_NCB
3416 #define basename_ODY_SMMUX_PMCGX_SVRX(a, b, c) "SMMUX_PMCGX_SVRX"
3417 #define device_bar_ODY_SMMUX_PMCGX_SVRX(a, b, c) 0x0 /* PF_BAR0 */
3418 #define busnum_ODY_SMMUX_PMCGX_SVRX(a, b, c) (a)
3419 #define arguments_ODY_SMMUX_PMCGX_SVRX(a, b, c) (a), (b), (c), -1
3420
3421 /**
3422 * Register (NCB) smmu#_priq_base
3423 *
3424 * SMMU PRI Queue Base Register
3425 */
3426 union ody_smmux_priq_base {
3427 uint64_t u;
3428 struct ody_smmux_priq_base_s {
3429 uint64_t log2size : 5;
3430 uint64_t addr : 47;
3431 uint64_t reserved_52_61 : 10;
3432 uint64_t wa : 1;
3433 uint64_t reserved_63 : 1;
3434 } s;
3435 /* struct ody_smmux_priq_base_s cn; */
3436 };
3437 typedef union ody_smmux_priq_base ody_smmux_priq_base_t;
3438
3439 static inline uint64_t ODY_SMMUX_PRIQ_BASE(uint64_t a) __attribute__ ((pure, always_inline));
ODY_SMMUX_PRIQ_BASE(uint64_t a)3440 static inline uint64_t ODY_SMMUX_PRIQ_BASE(uint64_t a)
3441 {
3442 if (a <= 3)
3443 return 0x8300000000c0ll + 0x1000000000ll * ((a) & 0x3);
3444 __ody_csr_fatal("SMMUX_PRIQ_BASE", 1, a, 0, 0, 0, 0, 0);
3445 }
3446
3447 #define typedef_ODY_SMMUX_PRIQ_BASE(a) ody_smmux_priq_base_t
3448 #define bustype_ODY_SMMUX_PRIQ_BASE(a) CSR_TYPE_NCB
3449 #define basename_ODY_SMMUX_PRIQ_BASE(a) "SMMUX_PRIQ_BASE"
3450 #define device_bar_ODY_SMMUX_PRIQ_BASE(a) 0x0 /* PF_BAR0 */
3451 #define busnum_ODY_SMMUX_PRIQ_BASE(a) (a)
3452 #define arguments_ODY_SMMUX_PRIQ_BASE(a) (a), -1, -1, -1
3453
3454 /**
3455 * Register (NCB32b) smmu#_priq_cons
3456 *
3457 * SMMU PRI Queue Consumer Register
3458 */
3459 union ody_smmux_priq_cons {
3460 uint32_t u;
3461 struct ody_smmux_priq_cons_s {
3462 uint32_t rd : 20;
3463 uint32_t reserved_20_30 : 11;
3464 uint32_t ovackflg : 1;
3465 } s;
3466 /* struct ody_smmux_priq_cons_s cn; */
3467 };
3468 typedef union ody_smmux_priq_cons ody_smmux_priq_cons_t;
3469
3470 static inline uint64_t ODY_SMMUX_PRIQ_CONS(uint64_t a) __attribute__ ((pure, always_inline));
ODY_SMMUX_PRIQ_CONS(uint64_t a)3471 static inline uint64_t ODY_SMMUX_PRIQ_CONS(uint64_t a)
3472 {
3473 if (a <= 3)
3474 return 0x8300000100ccll + 0x1000000000ll * ((a) & 0x3);
3475 __ody_csr_fatal("SMMUX_PRIQ_CONS", 1, a, 0, 0, 0, 0, 0);
3476 }
3477
3478 #define typedef_ODY_SMMUX_PRIQ_CONS(a) ody_smmux_priq_cons_t
3479 #define bustype_ODY_SMMUX_PRIQ_CONS(a) CSR_TYPE_NCB32b
3480 #define basename_ODY_SMMUX_PRIQ_CONS(a) "SMMUX_PRIQ_CONS"
3481 #define device_bar_ODY_SMMUX_PRIQ_CONS(a) 0x0 /* PF_BAR0 */
3482 #define busnum_ODY_SMMUX_PRIQ_CONS(a) (a)
3483 #define arguments_ODY_SMMUX_PRIQ_CONS(a) (a), -1, -1, -1
3484
3485 /**
3486 * Register (NCB) smmu#_priq_irq_cfg0
3487 *
3488 * SMMU PRI Queue Interrupt Configuration 0 Register
3489 */
3490 union ody_smmux_priq_irq_cfg0 {
3491 uint64_t u;
3492 struct ody_smmux_priq_irq_cfg0_s {
3493 uint64_t reserved_0_1 : 2;
3494 uint64_t addr : 50;
3495 uint64_t reserved_52_63 : 12;
3496 } s;
3497 /* struct ody_smmux_priq_irq_cfg0_s cn; */
3498 };
3499 typedef union ody_smmux_priq_irq_cfg0 ody_smmux_priq_irq_cfg0_t;
3500
3501 static inline uint64_t ODY_SMMUX_PRIQ_IRQ_CFG0(uint64_t a) __attribute__ ((pure, always_inline));
ODY_SMMUX_PRIQ_IRQ_CFG0(uint64_t a)3502 static inline uint64_t ODY_SMMUX_PRIQ_IRQ_CFG0(uint64_t a)
3503 {
3504 if (a <= 3)
3505 return 0x8300000000d0ll + 0x1000000000ll * ((a) & 0x3);
3506 __ody_csr_fatal("SMMUX_PRIQ_IRQ_CFG0", 1, a, 0, 0, 0, 0, 0);
3507 }
3508
3509 #define typedef_ODY_SMMUX_PRIQ_IRQ_CFG0(a) ody_smmux_priq_irq_cfg0_t
3510 #define bustype_ODY_SMMUX_PRIQ_IRQ_CFG0(a) CSR_TYPE_NCB
3511 #define basename_ODY_SMMUX_PRIQ_IRQ_CFG0(a) "SMMUX_PRIQ_IRQ_CFG0"
3512 #define device_bar_ODY_SMMUX_PRIQ_IRQ_CFG0(a) 0x0 /* PF_BAR0 */
3513 #define busnum_ODY_SMMUX_PRIQ_IRQ_CFG0(a) (a)
3514 #define arguments_ODY_SMMUX_PRIQ_IRQ_CFG0(a) (a), -1, -1, -1
3515
3516 /**
3517 * Register (NCB32b) smmu#_priq_irq_cfg1
3518 *
3519 * SMMU PRI Queue Interrupt Configuration 1 Register
3520 */
3521 union ody_smmux_priq_irq_cfg1 {
3522 uint32_t u;
3523 struct ody_smmux_priq_irq_cfg1_s {
3524 uint32_t data : 32;
3525 } s;
3526 /* struct ody_smmux_priq_irq_cfg1_s cn; */
3527 };
3528 typedef union ody_smmux_priq_irq_cfg1 ody_smmux_priq_irq_cfg1_t;
3529
3530 static inline uint64_t ODY_SMMUX_PRIQ_IRQ_CFG1(uint64_t a) __attribute__ ((pure, always_inline));
ODY_SMMUX_PRIQ_IRQ_CFG1(uint64_t a)3531 static inline uint64_t ODY_SMMUX_PRIQ_IRQ_CFG1(uint64_t a)
3532 {
3533 if (a <= 3)
3534 return 0x8300000000d8ll + 0x1000000000ll * ((a) & 0x3);
3535 __ody_csr_fatal("SMMUX_PRIQ_IRQ_CFG1", 1, a, 0, 0, 0, 0, 0);
3536 }
3537
3538 #define typedef_ODY_SMMUX_PRIQ_IRQ_CFG1(a) ody_smmux_priq_irq_cfg1_t
3539 #define bustype_ODY_SMMUX_PRIQ_IRQ_CFG1(a) CSR_TYPE_NCB32b
3540 #define basename_ODY_SMMUX_PRIQ_IRQ_CFG1(a) "SMMUX_PRIQ_IRQ_CFG1"
3541 #define device_bar_ODY_SMMUX_PRIQ_IRQ_CFG1(a) 0x0 /* PF_BAR0 */
3542 #define busnum_ODY_SMMUX_PRIQ_IRQ_CFG1(a) (a)
3543 #define arguments_ODY_SMMUX_PRIQ_IRQ_CFG1(a) (a), -1, -1, -1
3544
3545 /**
3546 * Register (NCB32b) smmu#_priq_irq_cfg2
3547 *
3548 * SMMU PRI Queue Interrupt Configuration 2 Register
3549 */
3550 union ody_smmux_priq_irq_cfg2 {
3551 uint32_t u;
3552 struct ody_smmux_priq_irq_cfg2_s {
3553 uint32_t memattr : 4;
3554 uint32_t sh : 2;
3555 uint32_t reserved_6_30 : 25;
3556 uint32_t lo : 1;
3557 } s;
3558 /* struct ody_smmux_priq_irq_cfg2_s cn; */
3559 };
3560 typedef union ody_smmux_priq_irq_cfg2 ody_smmux_priq_irq_cfg2_t;
3561
3562 static inline uint64_t ODY_SMMUX_PRIQ_IRQ_CFG2(uint64_t a) __attribute__ ((pure, always_inline));
ODY_SMMUX_PRIQ_IRQ_CFG2(uint64_t a)3563 static inline uint64_t ODY_SMMUX_PRIQ_IRQ_CFG2(uint64_t a)
3564 {
3565 if (a <= 3)
3566 return 0x8300000000dcll + 0x1000000000ll * ((a) & 0x3);
3567 __ody_csr_fatal("SMMUX_PRIQ_IRQ_CFG2", 1, a, 0, 0, 0, 0, 0);
3568 }
3569
3570 #define typedef_ODY_SMMUX_PRIQ_IRQ_CFG2(a) ody_smmux_priq_irq_cfg2_t
3571 #define bustype_ODY_SMMUX_PRIQ_IRQ_CFG2(a) CSR_TYPE_NCB32b
3572 #define basename_ODY_SMMUX_PRIQ_IRQ_CFG2(a) "SMMUX_PRIQ_IRQ_CFG2"
3573 #define device_bar_ODY_SMMUX_PRIQ_IRQ_CFG2(a) 0x0 /* PF_BAR0 */
3574 #define busnum_ODY_SMMUX_PRIQ_IRQ_CFG2(a) (a)
3575 #define arguments_ODY_SMMUX_PRIQ_IRQ_CFG2(a) (a), -1, -1, -1
3576
3577 /**
3578 * Register (NCB32b) smmu#_priq_prod
3579 *
3580 * SMMU PRI Queue Producer Register
3581 */
3582 union ody_smmux_priq_prod {
3583 uint32_t u;
3584 struct ody_smmux_priq_prod_s {
3585 uint32_t wr : 20;
3586 uint32_t reserved_20_30 : 11;
3587 uint32_t ovflg : 1;
3588 } s;
3589 /* struct ody_smmux_priq_prod_s cn; */
3590 };
3591 typedef union ody_smmux_priq_prod ody_smmux_priq_prod_t;
3592
3593 static inline uint64_t ODY_SMMUX_PRIQ_PROD(uint64_t a) __attribute__ ((pure, always_inline));
ODY_SMMUX_PRIQ_PROD(uint64_t a)3594 static inline uint64_t ODY_SMMUX_PRIQ_PROD(uint64_t a)
3595 {
3596 if (a <= 3)
3597 return 0x8300000100c8ll + 0x1000000000ll * ((a) & 0x3);
3598 __ody_csr_fatal("SMMUX_PRIQ_PROD", 1, a, 0, 0, 0, 0, 0);
3599 }
3600
3601 #define typedef_ODY_SMMUX_PRIQ_PROD(a) ody_smmux_priq_prod_t
3602 #define bustype_ODY_SMMUX_PRIQ_PROD(a) CSR_TYPE_NCB32b
3603 #define basename_ODY_SMMUX_PRIQ_PROD(a) "SMMUX_PRIQ_PROD"
3604 #define device_bar_ODY_SMMUX_PRIQ_PROD(a) 0x0 /* PF_BAR0 */
3605 #define busnum_ODY_SMMUX_PRIQ_PROD(a) (a)
3606 #define arguments_ODY_SMMUX_PRIQ_PROD(a) (a), -1, -1, -1
3607
3608 /**
3609 * Register (NCB32b) smmu#_s_agbpa
3610 *
3611 * SMMU Secure Alternate Global Bypass Attribute Register
3612 * This register is intended to allow an implementation to apply an additional non
3613 * architected attributes or tag to bypassing transactions, for example a traffic
3614 * routing identifier.
3615 *
3616 * If this field is unsupported by an implementation, it is RES0. It is not
3617 * intended for this register to be used to further modify existing architected
3618 * bypass attributes which are controlled using GPBA.
3619 */
3620 union ody_smmux_s_agbpa {
3621 uint32_t u;
3622 struct ody_smmux_s_agbpa_s {
3623 uint32_t qos : 4;
3624 uint32_t reserved_4_31 : 28;
3625 } s;
3626 /* struct ody_smmux_s_agbpa_s cn; */
3627 };
3628 typedef union ody_smmux_s_agbpa ody_smmux_s_agbpa_t;
3629
3630 static inline uint64_t ODY_SMMUX_S_AGBPA(uint64_t a) __attribute__ ((pure, always_inline));
ODY_SMMUX_S_AGBPA(uint64_t a)3631 static inline uint64_t ODY_SMMUX_S_AGBPA(uint64_t a)
3632 {
3633 if (a <= 3)
3634 return 0x830000008048ll + 0x1000000000ll * ((a) & 0x3);
3635 __ody_csr_fatal("SMMUX_S_AGBPA", 1, a, 0, 0, 0, 0, 0);
3636 }
3637
3638 #define typedef_ODY_SMMUX_S_AGBPA(a) ody_smmux_s_agbpa_t
3639 #define bustype_ODY_SMMUX_S_AGBPA(a) CSR_TYPE_NCB32b
3640 #define basename_ODY_SMMUX_S_AGBPA(a) "SMMUX_S_AGBPA"
3641 #define device_bar_ODY_SMMUX_S_AGBPA(a) 0x0 /* PF_BAR0 */
3642 #define busnum_ODY_SMMUX_S_AGBPA(a) (a)
3643 #define arguments_ODY_SMMUX_S_AGBPA(a) (a), -1, -1, -1
3644
3645 /**
3646 * Register (NCB) smmu#_s_cmdq_base
3647 *
3648 * SMMU Secure Command Queue Base Register
3649 */
3650 union ody_smmux_s_cmdq_base {
3651 uint64_t u;
3652 struct ody_smmux_s_cmdq_base_s {
3653 uint64_t log2size : 5;
3654 uint64_t addr : 47;
3655 uint64_t reserved_52_61 : 10;
3656 uint64_t ra : 1;
3657 uint64_t reserved_63 : 1;
3658 } s;
3659 /* struct ody_smmux_s_cmdq_base_s cn; */
3660 };
3661 typedef union ody_smmux_s_cmdq_base ody_smmux_s_cmdq_base_t;
3662
3663 static inline uint64_t ODY_SMMUX_S_CMDQ_BASE(uint64_t a) __attribute__ ((pure, always_inline));
ODY_SMMUX_S_CMDQ_BASE(uint64_t a)3664 static inline uint64_t ODY_SMMUX_S_CMDQ_BASE(uint64_t a)
3665 {
3666 if (a <= 3)
3667 return 0x830000008090ll + 0x1000000000ll * ((a) & 0x3);
3668 __ody_csr_fatal("SMMUX_S_CMDQ_BASE", 1, a, 0, 0, 0, 0, 0);
3669 }
3670
3671 #define typedef_ODY_SMMUX_S_CMDQ_BASE(a) ody_smmux_s_cmdq_base_t
3672 #define bustype_ODY_SMMUX_S_CMDQ_BASE(a) CSR_TYPE_NCB
3673 #define basename_ODY_SMMUX_S_CMDQ_BASE(a) "SMMUX_S_CMDQ_BASE"
3674 #define device_bar_ODY_SMMUX_S_CMDQ_BASE(a) 0x0 /* PF_BAR0 */
3675 #define busnum_ODY_SMMUX_S_CMDQ_BASE(a) (a)
3676 #define arguments_ODY_SMMUX_S_CMDQ_BASE(a) (a), -1, -1, -1
3677
3678 /**
3679 * Register (NCB32b) smmu#_s_cmdq_cons
3680 *
3681 * SMMU Secure Command Queue Consumer Register
3682 */
3683 union ody_smmux_s_cmdq_cons {
3684 uint32_t u;
3685 struct ody_smmux_s_cmdq_cons_s {
3686 uint32_t rd : 20;
3687 uint32_t reserved_20_23 : 4;
3688 uint32_t errx : 7;
3689 uint32_t reserved_31 : 1;
3690 } s;
3691 /* struct ody_smmux_s_cmdq_cons_s cn; */
3692 };
3693 typedef union ody_smmux_s_cmdq_cons ody_smmux_s_cmdq_cons_t;
3694
3695 static inline uint64_t ODY_SMMUX_S_CMDQ_CONS(uint64_t a) __attribute__ ((pure, always_inline));
ODY_SMMUX_S_CMDQ_CONS(uint64_t a)3696 static inline uint64_t ODY_SMMUX_S_CMDQ_CONS(uint64_t a)
3697 {
3698 if (a <= 3)
3699 return 0x83000000809cll + 0x1000000000ll * ((a) & 0x3);
3700 __ody_csr_fatal("SMMUX_S_CMDQ_CONS", 1, a, 0, 0, 0, 0, 0);
3701 }
3702
3703 #define typedef_ODY_SMMUX_S_CMDQ_CONS(a) ody_smmux_s_cmdq_cons_t
3704 #define bustype_ODY_SMMUX_S_CMDQ_CONS(a) CSR_TYPE_NCB32b
3705 #define basename_ODY_SMMUX_S_CMDQ_CONS(a) "SMMUX_S_CMDQ_CONS"
3706 #define device_bar_ODY_SMMUX_S_CMDQ_CONS(a) 0x0 /* PF_BAR0 */
3707 #define busnum_ODY_SMMUX_S_CMDQ_CONS(a) (a)
3708 #define arguments_ODY_SMMUX_S_CMDQ_CONS(a) (a), -1, -1, -1
3709
3710 /**
3711 * Register (NCB32b) smmu#_s_cmdq_prod
3712 *
3713 * SMMU Secure Command Queue Producer Register
3714 */
3715 union ody_smmux_s_cmdq_prod {
3716 uint32_t u;
3717 struct ody_smmux_s_cmdq_prod_s {
3718 uint32_t wr : 20;
3719 uint32_t reserved_20_31 : 12;
3720 } s;
3721 /* struct ody_smmux_s_cmdq_prod_s cn; */
3722 };
3723 typedef union ody_smmux_s_cmdq_prod ody_smmux_s_cmdq_prod_t;
3724
3725 static inline uint64_t ODY_SMMUX_S_CMDQ_PROD(uint64_t a) __attribute__ ((pure, always_inline));
ODY_SMMUX_S_CMDQ_PROD(uint64_t a)3726 static inline uint64_t ODY_SMMUX_S_CMDQ_PROD(uint64_t a)
3727 {
3728 if (a <= 3)
3729 return 0x830000008098ll + 0x1000000000ll * ((a) & 0x3);
3730 __ody_csr_fatal("SMMUX_S_CMDQ_PROD", 1, a, 0, 0, 0, 0, 0);
3731 }
3732
3733 #define typedef_ODY_SMMUX_S_CMDQ_PROD(a) ody_smmux_s_cmdq_prod_t
3734 #define bustype_ODY_SMMUX_S_CMDQ_PROD(a) CSR_TYPE_NCB32b
3735 #define basename_ODY_SMMUX_S_CMDQ_PROD(a) "SMMUX_S_CMDQ_PROD"
3736 #define device_bar_ODY_SMMUX_S_CMDQ_PROD(a) 0x0 /* PF_BAR0 */
3737 #define busnum_ODY_SMMUX_S_CMDQ_PROD(a) (a)
3738 #define arguments_ODY_SMMUX_S_CMDQ_PROD(a) (a), -1, -1, -1
3739
3740 /**
3741 * Register (NCB32b) smmu#_s_cr0
3742 *
3743 * SMMU Secure Control 0 Register
3744 * An update to a field in SMMU()_S_CR0 is not considered complete, along with any
3745 * side effects, until the respective field in SMMU()_S_CR0ACK is observed to take the
3746 * new value.
3747 */
3748 union ody_smmux_s_cr0 {
3749 uint32_t u;
3750 struct ody_smmux_s_cr0_s {
3751 uint32_t smmuen : 1;
3752 uint32_t reserved_1 : 1;
3753 uint32_t eventqen : 1;
3754 uint32_t cmdqen : 1;
3755 uint32_t reserved_4 : 1;
3756 uint32_t sif : 1;
3757 uint32_t vmw : 3;
3758 uint32_t nsstalld : 1;
3759 uint32_t reserved_10_31 : 22;
3760 } s;
3761 /* struct ody_smmux_s_cr0_s cn; */
3762 };
3763 typedef union ody_smmux_s_cr0 ody_smmux_s_cr0_t;
3764
3765 static inline uint64_t ODY_SMMUX_S_CR0(uint64_t a) __attribute__ ((pure, always_inline));
ODY_SMMUX_S_CR0(uint64_t a)3766 static inline uint64_t ODY_SMMUX_S_CR0(uint64_t a)
3767 {
3768 if (a <= 3)
3769 return 0x830000008020ll + 0x1000000000ll * ((a) & 0x3);
3770 __ody_csr_fatal("SMMUX_S_CR0", 1, a, 0, 0, 0, 0, 0);
3771 }
3772
3773 #define typedef_ODY_SMMUX_S_CR0(a) ody_smmux_s_cr0_t
3774 #define bustype_ODY_SMMUX_S_CR0(a) CSR_TYPE_NCB32b
3775 #define basename_ODY_SMMUX_S_CR0(a) "SMMUX_S_CR0"
3776 #define device_bar_ODY_SMMUX_S_CR0(a) 0x0 /* PF_BAR0 */
3777 #define busnum_ODY_SMMUX_S_CR0(a) (a)
3778 #define arguments_ODY_SMMUX_S_CR0(a) (a), -1, -1, -1
3779
3780 /**
3781 * Register (NCB32b) smmu#_s_cr0ack
3782 *
3783 * SMMU Secure Control 0 Acknowledgement Register
3784 * This register is a read-only copy of SMMU()_S_CR0.
3785 */
3786 union ody_smmux_s_cr0ack {
3787 uint32_t u;
3788 struct ody_smmux_s_cr0ack_s {
3789 uint32_t smmuen : 1;
3790 uint32_t reserved_1 : 1;
3791 uint32_t eventqen : 1;
3792 uint32_t cmdqen : 1;
3793 uint32_t reserved_4 : 1;
3794 uint32_t sif : 1;
3795 uint32_t vmw : 3;
3796 uint32_t nsstalld : 1;
3797 uint32_t reserved_10_31 : 22;
3798 } s;
3799 /* struct ody_smmux_s_cr0ack_s cn; */
3800 };
3801 typedef union ody_smmux_s_cr0ack ody_smmux_s_cr0ack_t;
3802
3803 static inline uint64_t ODY_SMMUX_S_CR0ACK(uint64_t a) __attribute__ ((pure, always_inline));
ODY_SMMUX_S_CR0ACK(uint64_t a)3804 static inline uint64_t ODY_SMMUX_S_CR0ACK(uint64_t a)
3805 {
3806 if (a <= 3)
3807 return 0x830000008024ll + 0x1000000000ll * ((a) & 0x3);
3808 __ody_csr_fatal("SMMUX_S_CR0ACK", 1, a, 0, 0, 0, 0, 0);
3809 }
3810
3811 #define typedef_ODY_SMMUX_S_CR0ACK(a) ody_smmux_s_cr0ack_t
3812 #define bustype_ODY_SMMUX_S_CR0ACK(a) CSR_TYPE_NCB32b
3813 #define basename_ODY_SMMUX_S_CR0ACK(a) "SMMUX_S_CR0ACK"
3814 #define device_bar_ODY_SMMUX_S_CR0ACK(a) 0x0 /* PF_BAR0 */
3815 #define busnum_ODY_SMMUX_S_CR0ACK(a) (a)
3816 #define arguments_ODY_SMMUX_S_CR0ACK(a) (a), -1, -1, -1
3817
3818 /**
3819 * Register (NCB32b) smmu#_s_cr1
3820 *
3821 * SMMU Secure Control 1 Register
3822 */
3823 union ody_smmux_s_cr1 {
3824 uint32_t u;
3825 struct ody_smmux_s_cr1_s {
3826 uint32_t queue_ic : 2;
3827 uint32_t queue_oc : 2;
3828 uint32_t queue_sh : 2;
3829 uint32_t table_ic : 2;
3830 uint32_t table_oc : 2;
3831 uint32_t table_sh : 2;
3832 uint32_t reserved_12_31 : 20;
3833 } s;
3834 /* struct ody_smmux_s_cr1_s cn; */
3835 };
3836 typedef union ody_smmux_s_cr1 ody_smmux_s_cr1_t;
3837
3838 static inline uint64_t ODY_SMMUX_S_CR1(uint64_t a) __attribute__ ((pure, always_inline));
ODY_SMMUX_S_CR1(uint64_t a)3839 static inline uint64_t ODY_SMMUX_S_CR1(uint64_t a)
3840 {
3841 if (a <= 3)
3842 return 0x830000008028ll + 0x1000000000ll * ((a) & 0x3);
3843 __ody_csr_fatal("SMMUX_S_CR1", 1, a, 0, 0, 0, 0, 0);
3844 }
3845
3846 #define typedef_ODY_SMMUX_S_CR1(a) ody_smmux_s_cr1_t
3847 #define bustype_ODY_SMMUX_S_CR1(a) CSR_TYPE_NCB32b
3848 #define basename_ODY_SMMUX_S_CR1(a) "SMMUX_S_CR1"
3849 #define device_bar_ODY_SMMUX_S_CR1(a) 0x0 /* PF_BAR0 */
3850 #define busnum_ODY_SMMUX_S_CR1(a) (a)
3851 #define arguments_ODY_SMMUX_S_CR1(a) (a), -1, -1, -1
3852
3853 /**
3854 * Register (NCB32b) smmu#_s_cr2
3855 *
3856 * SMMU Secure Control 2 Register
3857 */
3858 union ody_smmux_s_cr2 {
3859 uint32_t u;
3860 struct ody_smmux_s_cr2_s {
3861 uint32_t e2h : 1;
3862 uint32_t recinvsid : 1;
3863 uint32_t ptm : 1;
3864 uint32_t reserved_3_31 : 29;
3865 } s;
3866 /* struct ody_smmux_s_cr2_s cn; */
3867 };
3868 typedef union ody_smmux_s_cr2 ody_smmux_s_cr2_t;
3869
3870 static inline uint64_t ODY_SMMUX_S_CR2(uint64_t a) __attribute__ ((pure, always_inline));
ODY_SMMUX_S_CR2(uint64_t a)3871 static inline uint64_t ODY_SMMUX_S_CR2(uint64_t a)
3872 {
3873 if (a <= 3)
3874 return 0x83000000802cll + 0x1000000000ll * ((a) & 0x3);
3875 __ody_csr_fatal("SMMUX_S_CR2", 1, a, 0, 0, 0, 0, 0);
3876 }
3877
3878 #define typedef_ODY_SMMUX_S_CR2(a) ody_smmux_s_cr2_t
3879 #define bustype_ODY_SMMUX_S_CR2(a) CSR_TYPE_NCB32b
3880 #define basename_ODY_SMMUX_S_CR2(a) "SMMUX_S_CR2"
3881 #define device_bar_ODY_SMMUX_S_CR2(a) 0x0 /* PF_BAR0 */
3882 #define busnum_ODY_SMMUX_S_CR2(a) (a)
3883 #define arguments_ODY_SMMUX_S_CR2(a) (a), -1, -1, -1
3884
3885 /**
3886 * Register (NCB) smmu#_s_eventq_base
3887 *
3888 * SMMU Secure Event Queue Base Register
3889 */
3890 union ody_smmux_s_eventq_base {
3891 uint64_t u;
3892 struct ody_smmux_s_eventq_base_s {
3893 uint64_t log2size : 5;
3894 uint64_t addr : 47;
3895 uint64_t reserved_52_61 : 10;
3896 uint64_t wa : 1;
3897 uint64_t reserved_63 : 1;
3898 } s;
3899 /* struct ody_smmux_s_eventq_base_s cn; */
3900 };
3901 typedef union ody_smmux_s_eventq_base ody_smmux_s_eventq_base_t;
3902
3903 static inline uint64_t ODY_SMMUX_S_EVENTQ_BASE(uint64_t a) __attribute__ ((pure, always_inline));
ODY_SMMUX_S_EVENTQ_BASE(uint64_t a)3904 static inline uint64_t ODY_SMMUX_S_EVENTQ_BASE(uint64_t a)
3905 {
3906 if (a <= 3)
3907 return 0x8300000080a0ll + 0x1000000000ll * ((a) & 0x3);
3908 __ody_csr_fatal("SMMUX_S_EVENTQ_BASE", 1, a, 0, 0, 0, 0, 0);
3909 }
3910
3911 #define typedef_ODY_SMMUX_S_EVENTQ_BASE(a) ody_smmux_s_eventq_base_t
3912 #define bustype_ODY_SMMUX_S_EVENTQ_BASE(a) CSR_TYPE_NCB
3913 #define basename_ODY_SMMUX_S_EVENTQ_BASE(a) "SMMUX_S_EVENTQ_BASE"
3914 #define device_bar_ODY_SMMUX_S_EVENTQ_BASE(a) 0x0 /* PF_BAR0 */
3915 #define busnum_ODY_SMMUX_S_EVENTQ_BASE(a) (a)
3916 #define arguments_ODY_SMMUX_S_EVENTQ_BASE(a) (a), -1, -1, -1
3917
3918 /**
3919 * Register (NCB32b) smmu#_s_eventq_cons
3920 *
3921 * SMMU Secure Event Queue Consumer Register
3922 */
3923 union ody_smmux_s_eventq_cons {
3924 uint32_t u;
3925 struct ody_smmux_s_eventq_cons_s {
3926 uint32_t rd : 20;
3927 uint32_t reserved_20_30 : 11;
3928 uint32_t ovackflg : 1;
3929 } s;
3930 /* struct ody_smmux_s_eventq_cons_s cn; */
3931 };
3932 typedef union ody_smmux_s_eventq_cons ody_smmux_s_eventq_cons_t;
3933
3934 static inline uint64_t ODY_SMMUX_S_EVENTQ_CONS(uint64_t a) __attribute__ ((pure, always_inline));
ODY_SMMUX_S_EVENTQ_CONS(uint64_t a)3935 static inline uint64_t ODY_SMMUX_S_EVENTQ_CONS(uint64_t a)
3936 {
3937 if (a <= 3)
3938 return 0x8300000080acll + 0x1000000000ll * ((a) & 0x3);
3939 __ody_csr_fatal("SMMUX_S_EVENTQ_CONS", 1, a, 0, 0, 0, 0, 0);
3940 }
3941
3942 #define typedef_ODY_SMMUX_S_EVENTQ_CONS(a) ody_smmux_s_eventq_cons_t
3943 #define bustype_ODY_SMMUX_S_EVENTQ_CONS(a) CSR_TYPE_NCB32b
3944 #define basename_ODY_SMMUX_S_EVENTQ_CONS(a) "SMMUX_S_EVENTQ_CONS"
3945 #define device_bar_ODY_SMMUX_S_EVENTQ_CONS(a) 0x0 /* PF_BAR0 */
3946 #define busnum_ODY_SMMUX_S_EVENTQ_CONS(a) (a)
3947 #define arguments_ODY_SMMUX_S_EVENTQ_CONS(a) (a), -1, -1, -1
3948
3949 /**
3950 * Register (NCB) smmu#_s_eventq_irq_cfg0
3951 *
3952 * SMMU Secure Event Queue IRQ Configuration 0 Register
3953 */
3954 union ody_smmux_s_eventq_irq_cfg0 {
3955 uint64_t u;
3956 struct ody_smmux_s_eventq_irq_cfg0_s {
3957 uint64_t reserved_0_1 : 2;
3958 uint64_t addr : 50;
3959 uint64_t reserved_52_63 : 12;
3960 } s;
3961 /* struct ody_smmux_s_eventq_irq_cfg0_s cn; */
3962 };
3963 typedef union ody_smmux_s_eventq_irq_cfg0 ody_smmux_s_eventq_irq_cfg0_t;
3964
3965 static inline uint64_t ODY_SMMUX_S_EVENTQ_IRQ_CFG0(uint64_t a) __attribute__ ((pure, always_inline));
ODY_SMMUX_S_EVENTQ_IRQ_CFG0(uint64_t a)3966 static inline uint64_t ODY_SMMUX_S_EVENTQ_IRQ_CFG0(uint64_t a)
3967 {
3968 if (a <= 3)
3969 return 0x8300000080b0ll + 0x1000000000ll * ((a) & 0x3);
3970 __ody_csr_fatal("SMMUX_S_EVENTQ_IRQ_CFG0", 1, a, 0, 0, 0, 0, 0);
3971 }
3972
3973 #define typedef_ODY_SMMUX_S_EVENTQ_IRQ_CFG0(a) ody_smmux_s_eventq_irq_cfg0_t
3974 #define bustype_ODY_SMMUX_S_EVENTQ_IRQ_CFG0(a) CSR_TYPE_NCB
3975 #define basename_ODY_SMMUX_S_EVENTQ_IRQ_CFG0(a) "SMMUX_S_EVENTQ_IRQ_CFG0"
3976 #define device_bar_ODY_SMMUX_S_EVENTQ_IRQ_CFG0(a) 0x0 /* PF_BAR0 */
3977 #define busnum_ODY_SMMUX_S_EVENTQ_IRQ_CFG0(a) (a)
3978 #define arguments_ODY_SMMUX_S_EVENTQ_IRQ_CFG0(a) (a), -1, -1, -1
3979
3980 /**
3981 * Register (NCB32b) smmu#_s_eventq_irq_cfg1
3982 *
3983 * SMMU Secure Event Queue IRQ Configuration 1 Register
3984 */
3985 union ody_smmux_s_eventq_irq_cfg1 {
3986 uint32_t u;
3987 struct ody_smmux_s_eventq_irq_cfg1_s {
3988 uint32_t data : 32;
3989 } s;
3990 /* struct ody_smmux_s_eventq_irq_cfg1_s cn; */
3991 };
3992 typedef union ody_smmux_s_eventq_irq_cfg1 ody_smmux_s_eventq_irq_cfg1_t;
3993
3994 static inline uint64_t ODY_SMMUX_S_EVENTQ_IRQ_CFG1(uint64_t a) __attribute__ ((pure, always_inline));
ODY_SMMUX_S_EVENTQ_IRQ_CFG1(uint64_t a)3995 static inline uint64_t ODY_SMMUX_S_EVENTQ_IRQ_CFG1(uint64_t a)
3996 {
3997 if (a <= 3)
3998 return 0x8300000080b8ll + 0x1000000000ll * ((a) & 0x3);
3999 __ody_csr_fatal("SMMUX_S_EVENTQ_IRQ_CFG1", 1, a, 0, 0, 0, 0, 0);
4000 }
4001
4002 #define typedef_ODY_SMMUX_S_EVENTQ_IRQ_CFG1(a) ody_smmux_s_eventq_irq_cfg1_t
4003 #define bustype_ODY_SMMUX_S_EVENTQ_IRQ_CFG1(a) CSR_TYPE_NCB32b
4004 #define basename_ODY_SMMUX_S_EVENTQ_IRQ_CFG1(a) "SMMUX_S_EVENTQ_IRQ_CFG1"
4005 #define device_bar_ODY_SMMUX_S_EVENTQ_IRQ_CFG1(a) 0x0 /* PF_BAR0 */
4006 #define busnum_ODY_SMMUX_S_EVENTQ_IRQ_CFG1(a) (a)
4007 #define arguments_ODY_SMMUX_S_EVENTQ_IRQ_CFG1(a) (a), -1, -1, -1
4008
4009 /**
4010 * Register (NCB32b) smmu#_s_eventq_irq_cfg2
4011 *
4012 * SMMU Secure Event Queue IRQ Configuration 2 Register
4013 */
4014 union ody_smmux_s_eventq_irq_cfg2 {
4015 uint32_t u;
4016 struct ody_smmux_s_eventq_irq_cfg2_s {
4017 uint32_t memattr : 4;
4018 uint32_t sh : 2;
4019 uint32_t reserved_6_31 : 26;
4020 } s;
4021 /* struct ody_smmux_s_eventq_irq_cfg2_s cn; */
4022 };
4023 typedef union ody_smmux_s_eventq_irq_cfg2 ody_smmux_s_eventq_irq_cfg2_t;
4024
4025 static inline uint64_t ODY_SMMUX_S_EVENTQ_IRQ_CFG2(uint64_t a) __attribute__ ((pure, always_inline));
ODY_SMMUX_S_EVENTQ_IRQ_CFG2(uint64_t a)4026 static inline uint64_t ODY_SMMUX_S_EVENTQ_IRQ_CFG2(uint64_t a)
4027 {
4028 if (a <= 3)
4029 return 0x8300000080bcll + 0x1000000000ll * ((a) & 0x3);
4030 __ody_csr_fatal("SMMUX_S_EVENTQ_IRQ_CFG2", 1, a, 0, 0, 0, 0, 0);
4031 }
4032
4033 #define typedef_ODY_SMMUX_S_EVENTQ_IRQ_CFG2(a) ody_smmux_s_eventq_irq_cfg2_t
4034 #define bustype_ODY_SMMUX_S_EVENTQ_IRQ_CFG2(a) CSR_TYPE_NCB32b
4035 #define basename_ODY_SMMUX_S_EVENTQ_IRQ_CFG2(a) "SMMUX_S_EVENTQ_IRQ_CFG2"
4036 #define device_bar_ODY_SMMUX_S_EVENTQ_IRQ_CFG2(a) 0x0 /* PF_BAR0 */
4037 #define busnum_ODY_SMMUX_S_EVENTQ_IRQ_CFG2(a) (a)
4038 #define arguments_ODY_SMMUX_S_EVENTQ_IRQ_CFG2(a) (a), -1, -1, -1
4039
4040 /**
4041 * Register (NCB32b) smmu#_s_eventq_prod
4042 *
4043 * SMMU Secure Event Queue Producer Register
4044 */
4045 union ody_smmux_s_eventq_prod {
4046 uint32_t u;
4047 struct ody_smmux_s_eventq_prod_s {
4048 uint32_t wr : 20;
4049 uint32_t reserved_20_30 : 11;
4050 uint32_t ovflg : 1;
4051 } s;
4052 /* struct ody_smmux_s_eventq_prod_s cn; */
4053 };
4054 typedef union ody_smmux_s_eventq_prod ody_smmux_s_eventq_prod_t;
4055
4056 static inline uint64_t ODY_SMMUX_S_EVENTQ_PROD(uint64_t a) __attribute__ ((pure, always_inline));
ODY_SMMUX_S_EVENTQ_PROD(uint64_t a)4057 static inline uint64_t ODY_SMMUX_S_EVENTQ_PROD(uint64_t a)
4058 {
4059 if (a <= 3)
4060 return 0x8300000080a8ll + 0x1000000000ll * ((a) & 0x3);
4061 __ody_csr_fatal("SMMUX_S_EVENTQ_PROD", 1, a, 0, 0, 0, 0, 0);
4062 }
4063
4064 #define typedef_ODY_SMMUX_S_EVENTQ_PROD(a) ody_smmux_s_eventq_prod_t
4065 #define bustype_ODY_SMMUX_S_EVENTQ_PROD(a) CSR_TYPE_NCB32b
4066 #define basename_ODY_SMMUX_S_EVENTQ_PROD(a) "SMMUX_S_EVENTQ_PROD"
4067 #define device_bar_ODY_SMMUX_S_EVENTQ_PROD(a) 0x0 /* PF_BAR0 */
4068 #define busnum_ODY_SMMUX_S_EVENTQ_PROD(a) (a)
4069 #define arguments_ODY_SMMUX_S_EVENTQ_PROD(a) (a), -1, -1, -1
4070
4071 /**
4072 * Register (NCB) smmu#_s_gatos_addr
4073 *
4074 * SMMU GATOS Address Register
4075 */
4076 union ody_smmux_s_gatos_addr {
4077 uint64_t u;
4078 struct ody_smmux_s_gatos_addr_s {
4079 uint64_t reserved_0_3 : 4;
4080 uint64_t ns_ind : 1;
4081 uint64_t reserved_5 : 1;
4082 uint64_t httui : 1;
4083 uint64_t ind : 1;
4084 uint64_t rnw : 1;
4085 uint64_t pnu : 1;
4086 uint64_t rtype : 2;
4087 uint64_t addr : 52;
4088 } s;
4089 /* struct ody_smmux_s_gatos_addr_s cn; */
4090 };
4091 typedef union ody_smmux_s_gatos_addr ody_smmux_s_gatos_addr_t;
4092
4093 static inline uint64_t ODY_SMMUX_S_GATOS_ADDR(uint64_t a) __attribute__ ((pure, always_inline));
ODY_SMMUX_S_GATOS_ADDR(uint64_t a)4094 static inline uint64_t ODY_SMMUX_S_GATOS_ADDR(uint64_t a)
4095 {
4096 if (a <= 3)
4097 return 0x830000008110ll + 0x1000000000ll * ((a) & 0x3);
4098 __ody_csr_fatal("SMMUX_S_GATOS_ADDR", 1, a, 0, 0, 0, 0, 0);
4099 }
4100
4101 #define typedef_ODY_SMMUX_S_GATOS_ADDR(a) ody_smmux_s_gatos_addr_t
4102 #define bustype_ODY_SMMUX_S_GATOS_ADDR(a) CSR_TYPE_NCB
4103 #define basename_ODY_SMMUX_S_GATOS_ADDR(a) "SMMUX_S_GATOS_ADDR"
4104 #define device_bar_ODY_SMMUX_S_GATOS_ADDR(a) 0x0 /* PF_BAR0 */
4105 #define busnum_ODY_SMMUX_S_GATOS_ADDR(a) (a)
4106 #define arguments_ODY_SMMUX_S_GATOS_ADDR(a) (a), -1, -1, -1
4107
4108 /**
4109 * Register (NCB32b) smmu#_s_gatos_ctrl
4110 *
4111 * SMMU Secure GATOS Control Register
4112 */
4113 union ody_smmux_s_gatos_ctrl {
4114 uint32_t u;
4115 struct ody_smmux_s_gatos_ctrl_s {
4116 uint32_t run : 1;
4117 uint32_t reserved_1_31 : 31;
4118 } s;
4119 /* struct ody_smmux_s_gatos_ctrl_s cn; */
4120 };
4121 typedef union ody_smmux_s_gatos_ctrl ody_smmux_s_gatos_ctrl_t;
4122
4123 static inline uint64_t ODY_SMMUX_S_GATOS_CTRL(uint64_t a) __attribute__ ((pure, always_inline));
ODY_SMMUX_S_GATOS_CTRL(uint64_t a)4124 static inline uint64_t ODY_SMMUX_S_GATOS_CTRL(uint64_t a)
4125 {
4126 if (a <= 3)
4127 return 0x830000008100ll + 0x1000000000ll * ((a) & 0x3);
4128 __ody_csr_fatal("SMMUX_S_GATOS_CTRL", 1, a, 0, 0, 0, 0, 0);
4129 }
4130
4131 #define typedef_ODY_SMMUX_S_GATOS_CTRL(a) ody_smmux_s_gatos_ctrl_t
4132 #define bustype_ODY_SMMUX_S_GATOS_CTRL(a) CSR_TYPE_NCB32b
4133 #define basename_ODY_SMMUX_S_GATOS_CTRL(a) "SMMUX_S_GATOS_CTRL"
4134 #define device_bar_ODY_SMMUX_S_GATOS_CTRL(a) 0x0 /* PF_BAR0 */
4135 #define busnum_ODY_SMMUX_S_GATOS_CTRL(a) (a)
4136 #define arguments_ODY_SMMUX_S_GATOS_CTRL(a) (a), -1, -1, -1
4137
4138 /**
4139 * Register (NCB) smmu#_s_gatos_par
4140 *
4141 * SMMU GATOS Address Register
4142 */
4143 union ody_smmux_s_gatos_par {
4144 uint64_t u;
4145 struct ody_smmux_s_gatos_par_s {
4146 uint64_t par : 64;
4147 } s;
4148 /* struct ody_smmux_s_gatos_par_s cn; */
4149 };
4150 typedef union ody_smmux_s_gatos_par ody_smmux_s_gatos_par_t;
4151
4152 static inline uint64_t ODY_SMMUX_S_GATOS_PAR(uint64_t a) __attribute__ ((pure, always_inline));
ODY_SMMUX_S_GATOS_PAR(uint64_t a)4153 static inline uint64_t ODY_SMMUX_S_GATOS_PAR(uint64_t a)
4154 {
4155 if (a <= 3)
4156 return 0x830000008118ll + 0x1000000000ll * ((a) & 0x3);
4157 __ody_csr_fatal("SMMUX_S_GATOS_PAR", 1, a, 0, 0, 0, 0, 0);
4158 }
4159
4160 #define typedef_ODY_SMMUX_S_GATOS_PAR(a) ody_smmux_s_gatos_par_t
4161 #define bustype_ODY_SMMUX_S_GATOS_PAR(a) CSR_TYPE_NCB
4162 #define basename_ODY_SMMUX_S_GATOS_PAR(a) "SMMUX_S_GATOS_PAR"
4163 #define device_bar_ODY_SMMUX_S_GATOS_PAR(a) 0x0 /* PF_BAR0 */
4164 #define busnum_ODY_SMMUX_S_GATOS_PAR(a) (a)
4165 #define arguments_ODY_SMMUX_S_GATOS_PAR(a) (a), -1, -1, -1
4166
4167 /**
4168 * Register (NCB) smmu#_s_gatos_sid
4169 *
4170 * SMMU GATOS SID Register
4171 */
4172 union ody_smmux_s_gatos_sid {
4173 uint64_t u;
4174 struct ody_smmux_s_gatos_sid_s {
4175 uint64_t streamid : 22;
4176 uint64_t reserved_22_31 : 10;
4177 uint64_t substreamid : 20;
4178 uint64_t ssid_valid : 1;
4179 uint64_t ssec : 1;
4180 uint64_t reserved_54_63 : 10;
4181 } s;
4182 /* struct ody_smmux_s_gatos_sid_s cn; */
4183 };
4184 typedef union ody_smmux_s_gatos_sid ody_smmux_s_gatos_sid_t;
4185
4186 static inline uint64_t ODY_SMMUX_S_GATOS_SID(uint64_t a) __attribute__ ((pure, always_inline));
ODY_SMMUX_S_GATOS_SID(uint64_t a)4187 static inline uint64_t ODY_SMMUX_S_GATOS_SID(uint64_t a)
4188 {
4189 if (a <= 3)
4190 return 0x830000008108ll + 0x1000000000ll * ((a) & 0x3);
4191 __ody_csr_fatal("SMMUX_S_GATOS_SID", 1, a, 0, 0, 0, 0, 0);
4192 }
4193
4194 #define typedef_ODY_SMMUX_S_GATOS_SID(a) ody_smmux_s_gatos_sid_t
4195 #define bustype_ODY_SMMUX_S_GATOS_SID(a) CSR_TYPE_NCB
4196 #define basename_ODY_SMMUX_S_GATOS_SID(a) "SMMUX_S_GATOS_SID"
4197 #define device_bar_ODY_SMMUX_S_GATOS_SID(a) 0x0 /* PF_BAR0 */
4198 #define busnum_ODY_SMMUX_S_GATOS_SID(a) (a)
4199 #define arguments_ODY_SMMUX_S_GATOS_SID(a) (a), -1, -1, -1
4200
4201 /**
4202 * Register (NCB32b) smmu#_s_gbpa
4203 *
4204 * SMMU Secure Global Bypass Attribute Register
4205 */
4206 union ody_smmux_s_gbpa {
4207 uint32_t u;
4208 struct ody_smmux_s_gbpa_s {
4209 uint32_t memattr : 4;
4210 uint32_t mtcfg : 1;
4211 uint32_t reserved_5_7 : 3;
4212 uint32_t alloccfg : 4;
4213 uint32_t shcfg : 2;
4214 uint32_t nscfg : 2;
4215 uint32_t privcfg : 2;
4216 uint32_t instcfg : 2;
4217 uint32_t abrt : 1;
4218 uint32_t reserved_21_30 : 10;
4219 uint32_t update : 1;
4220 } s;
4221 /* struct ody_smmux_s_gbpa_s cn; */
4222 };
4223 typedef union ody_smmux_s_gbpa ody_smmux_s_gbpa_t;
4224
4225 static inline uint64_t ODY_SMMUX_S_GBPA(uint64_t a) __attribute__ ((pure, always_inline));
ODY_SMMUX_S_GBPA(uint64_t a)4226 static inline uint64_t ODY_SMMUX_S_GBPA(uint64_t a)
4227 {
4228 if (a <= 3)
4229 return 0x830000008044ll + 0x1000000000ll * ((a) & 0x3);
4230 __ody_csr_fatal("SMMUX_S_GBPA", 1, a, 0, 0, 0, 0, 0);
4231 }
4232
4233 #define typedef_ODY_SMMUX_S_GBPA(a) ody_smmux_s_gbpa_t
4234 #define bustype_ODY_SMMUX_S_GBPA(a) CSR_TYPE_NCB32b
4235 #define basename_ODY_SMMUX_S_GBPA(a) "SMMUX_S_GBPA"
4236 #define device_bar_ODY_SMMUX_S_GBPA(a) 0x0 /* PF_BAR0 */
4237 #define busnum_ODY_SMMUX_S_GBPA(a) (a)
4238 #define arguments_ODY_SMMUX_S_GBPA(a) (a), -1, -1, -1
4239
4240 /**
4241 * Register (NCB32b) smmu#_s_gbpmpam
4242 *
4243 * SMMU Global Bypass MPAM Configuration for secure state Register
4244 */
4245 union ody_smmux_s_gbpmpam {
4246 uint32_t u;
4247 struct ody_smmux_s_gbpmpam_s {
4248 uint32_t gbp_partid : 9;
4249 uint32_t reserved_9_15 : 7;
4250 uint32_t gbp_pmg : 1;
4251 uint32_t reserved_17_23 : 7;
4252 uint32_t mpam_ns : 1;
4253 uint32_t reserved_25_30 : 6;
4254 uint32_t update : 1;
4255 } s;
4256 /* struct ody_smmux_s_gbpmpam_s cn; */
4257 };
4258 typedef union ody_smmux_s_gbpmpam ody_smmux_s_gbpmpam_t;
4259
4260 static inline uint64_t ODY_SMMUX_S_GBPMPAM(uint64_t a) __attribute__ ((pure, always_inline));
ODY_SMMUX_S_GBPMPAM(uint64_t a)4261 static inline uint64_t ODY_SMMUX_S_GBPMPAM(uint64_t a)
4262 {
4263 if (a <= 3)
4264 return 0x83000000813cll + 0x1000000000ll * ((a) & 0x3);
4265 __ody_csr_fatal("SMMUX_S_GBPMPAM", 1, a, 0, 0, 0, 0, 0);
4266 }
4267
4268 #define typedef_ODY_SMMUX_S_GBPMPAM(a) ody_smmux_s_gbpmpam_t
4269 #define bustype_ODY_SMMUX_S_GBPMPAM(a) CSR_TYPE_NCB32b
4270 #define basename_ODY_SMMUX_S_GBPMPAM(a) "SMMUX_S_GBPMPAM"
4271 #define device_bar_ODY_SMMUX_S_GBPMPAM(a) 0x0 /* PF_BAR0 */
4272 #define busnum_ODY_SMMUX_S_GBPMPAM(a) (a)
4273 #define arguments_ODY_SMMUX_S_GBPMPAM(a) (a), -1, -1, -1
4274
4275 /**
4276 * Register (NCB32b) smmu#_s_gerror
4277 *
4278 * SMMU Secure GERROR Register
4279 */
4280 union ody_smmux_s_gerror {
4281 uint32_t u;
4282 struct ody_smmux_s_gerror_s {
4283 uint32_t cmdq_err : 1;
4284 uint32_t reserved_1 : 1;
4285 uint32_t eventq_abt_err : 1;
4286 uint32_t reserved_3 : 1;
4287 uint32_t msi_cmdq_abt_err : 1;
4288 uint32_t msi_eventq_abt_err : 1;
4289 uint32_t reserved_6 : 1;
4290 uint32_t msi_gerror_abt_err : 1;
4291 uint32_t sfm_err : 1;
4292 uint32_t reserved_9_31 : 23;
4293 } s;
4294 /* struct ody_smmux_s_gerror_s cn; */
4295 };
4296 typedef union ody_smmux_s_gerror ody_smmux_s_gerror_t;
4297
4298 static inline uint64_t ODY_SMMUX_S_GERROR(uint64_t a) __attribute__ ((pure, always_inline));
ODY_SMMUX_S_GERROR(uint64_t a)4299 static inline uint64_t ODY_SMMUX_S_GERROR(uint64_t a)
4300 {
4301 if (a <= 3)
4302 return 0x830000008060ll + 0x1000000000ll * ((a) & 0x3);
4303 __ody_csr_fatal("SMMUX_S_GERROR", 1, a, 0, 0, 0, 0, 0);
4304 }
4305
4306 #define typedef_ODY_SMMUX_S_GERROR(a) ody_smmux_s_gerror_t
4307 #define bustype_ODY_SMMUX_S_GERROR(a) CSR_TYPE_NCB32b
4308 #define basename_ODY_SMMUX_S_GERROR(a) "SMMUX_S_GERROR"
4309 #define device_bar_ODY_SMMUX_S_GERROR(a) 0x0 /* PF_BAR0 */
4310 #define busnum_ODY_SMMUX_S_GERROR(a) (a)
4311 #define arguments_ODY_SMMUX_S_GERROR(a) (a), -1, -1, -1
4312
4313 /**
4314 * Register (NCB) smmu#_s_gerror_irq_cfg0
4315 *
4316 * SMMU Secure GERROR IRQ Configuration 0 Register
4317 * Registers SMMU()_S_GERROR_IRQ_CFG0/1/2 are guarded by the respective
4318 * SMMU()_S_IRQ_CTRL[GERROR_IRQEN] and must only be modified when
4319 * SMMU()_S_IRQ_CTRL[GERROR_IRQEN]=0.
4320 */
4321 union ody_smmux_s_gerror_irq_cfg0 {
4322 uint64_t u;
4323 struct ody_smmux_s_gerror_irq_cfg0_s {
4324 uint64_t reserved_0_1 : 2;
4325 uint64_t addr : 50;
4326 uint64_t reserved_52_63 : 12;
4327 } s;
4328 /* struct ody_smmux_s_gerror_irq_cfg0_s cn; */
4329 };
4330 typedef union ody_smmux_s_gerror_irq_cfg0 ody_smmux_s_gerror_irq_cfg0_t;
4331
4332 static inline uint64_t ODY_SMMUX_S_GERROR_IRQ_CFG0(uint64_t a) __attribute__ ((pure, always_inline));
ODY_SMMUX_S_GERROR_IRQ_CFG0(uint64_t a)4333 static inline uint64_t ODY_SMMUX_S_GERROR_IRQ_CFG0(uint64_t a)
4334 {
4335 if (a <= 3)
4336 return 0x830000008068ll + 0x1000000000ll * ((a) & 0x3);
4337 __ody_csr_fatal("SMMUX_S_GERROR_IRQ_CFG0", 1, a, 0, 0, 0, 0, 0);
4338 }
4339
4340 #define typedef_ODY_SMMUX_S_GERROR_IRQ_CFG0(a) ody_smmux_s_gerror_irq_cfg0_t
4341 #define bustype_ODY_SMMUX_S_GERROR_IRQ_CFG0(a) CSR_TYPE_NCB
4342 #define basename_ODY_SMMUX_S_GERROR_IRQ_CFG0(a) "SMMUX_S_GERROR_IRQ_CFG0"
4343 #define device_bar_ODY_SMMUX_S_GERROR_IRQ_CFG0(a) 0x0 /* PF_BAR0 */
4344 #define busnum_ODY_SMMUX_S_GERROR_IRQ_CFG0(a) (a)
4345 #define arguments_ODY_SMMUX_S_GERROR_IRQ_CFG0(a) (a), -1, -1, -1
4346
4347 /**
4348 * Register (NCB32b) smmu#_s_gerror_irq_cfg1
4349 *
4350 * SMMU Secure GERROR IRQ Configuration 1 Register
4351 */
4352 union ody_smmux_s_gerror_irq_cfg1 {
4353 uint32_t u;
4354 struct ody_smmux_s_gerror_irq_cfg1_s {
4355 uint32_t data : 32;
4356 } s;
4357 /* struct ody_smmux_s_gerror_irq_cfg1_s cn; */
4358 };
4359 typedef union ody_smmux_s_gerror_irq_cfg1 ody_smmux_s_gerror_irq_cfg1_t;
4360
4361 static inline uint64_t ODY_SMMUX_S_GERROR_IRQ_CFG1(uint64_t a) __attribute__ ((pure, always_inline));
ODY_SMMUX_S_GERROR_IRQ_CFG1(uint64_t a)4362 static inline uint64_t ODY_SMMUX_S_GERROR_IRQ_CFG1(uint64_t a)
4363 {
4364 if (a <= 3)
4365 return 0x830000008070ll + 0x1000000000ll * ((a) & 0x3);
4366 __ody_csr_fatal("SMMUX_S_GERROR_IRQ_CFG1", 1, a, 0, 0, 0, 0, 0);
4367 }
4368
4369 #define typedef_ODY_SMMUX_S_GERROR_IRQ_CFG1(a) ody_smmux_s_gerror_irq_cfg1_t
4370 #define bustype_ODY_SMMUX_S_GERROR_IRQ_CFG1(a) CSR_TYPE_NCB32b
4371 #define basename_ODY_SMMUX_S_GERROR_IRQ_CFG1(a) "SMMUX_S_GERROR_IRQ_CFG1"
4372 #define device_bar_ODY_SMMUX_S_GERROR_IRQ_CFG1(a) 0x0 /* PF_BAR0 */
4373 #define busnum_ODY_SMMUX_S_GERROR_IRQ_CFG1(a) (a)
4374 #define arguments_ODY_SMMUX_S_GERROR_IRQ_CFG1(a) (a), -1, -1, -1
4375
4376 /**
4377 * Register (NCB32b) smmu#_s_gerror_irq_cfg2
4378 *
4379 * SMMU Secure GERROR IRQ Configuration 2 Register
4380 */
4381 union ody_smmux_s_gerror_irq_cfg2 {
4382 uint32_t u;
4383 struct ody_smmux_s_gerror_irq_cfg2_s {
4384 uint32_t memattr : 4;
4385 uint32_t sh : 2;
4386 uint32_t reserved_6_31 : 26;
4387 } s;
4388 /* struct ody_smmux_s_gerror_irq_cfg2_s cn; */
4389 };
4390 typedef union ody_smmux_s_gerror_irq_cfg2 ody_smmux_s_gerror_irq_cfg2_t;
4391
4392 static inline uint64_t ODY_SMMUX_S_GERROR_IRQ_CFG2(uint64_t a) __attribute__ ((pure, always_inline));
ODY_SMMUX_S_GERROR_IRQ_CFG2(uint64_t a)4393 static inline uint64_t ODY_SMMUX_S_GERROR_IRQ_CFG2(uint64_t a)
4394 {
4395 if (a <= 3)
4396 return 0x830000008074ll + 0x1000000000ll * ((a) & 0x3);
4397 __ody_csr_fatal("SMMUX_S_GERROR_IRQ_CFG2", 1, a, 0, 0, 0, 0, 0);
4398 }
4399
4400 #define typedef_ODY_SMMUX_S_GERROR_IRQ_CFG2(a) ody_smmux_s_gerror_irq_cfg2_t
4401 #define bustype_ODY_SMMUX_S_GERROR_IRQ_CFG2(a) CSR_TYPE_NCB32b
4402 #define basename_ODY_SMMUX_S_GERROR_IRQ_CFG2(a) "SMMUX_S_GERROR_IRQ_CFG2"
4403 #define device_bar_ODY_SMMUX_S_GERROR_IRQ_CFG2(a) 0x0 /* PF_BAR0 */
4404 #define busnum_ODY_SMMUX_S_GERROR_IRQ_CFG2(a) (a)
4405 #define arguments_ODY_SMMUX_S_GERROR_IRQ_CFG2(a) (a), -1, -1, -1
4406
4407 /**
4408 * Register (NCB32b) smmu#_s_gerrorn
4409 *
4410 * SMMU Secure GERRORN Register
4411 */
4412 union ody_smmux_s_gerrorn {
4413 uint32_t u;
4414 struct ody_smmux_s_gerrorn_s {
4415 uint32_t cmdq_err : 1;
4416 uint32_t reserved_1 : 1;
4417 uint32_t eventq_abt_err : 1;
4418 uint32_t reserved_3 : 1;
4419 uint32_t msi_cmdq_abt_err : 1;
4420 uint32_t msi_eventq_abt_err : 1;
4421 uint32_t reserved_6 : 1;
4422 uint32_t msi_gerror_abt_err : 1;
4423 uint32_t sfm_err : 1;
4424 uint32_t reserved_9_31 : 23;
4425 } s;
4426 /* struct ody_smmux_s_gerrorn_s cn; */
4427 };
4428 typedef union ody_smmux_s_gerrorn ody_smmux_s_gerrorn_t;
4429
4430 static inline uint64_t ODY_SMMUX_S_GERRORN(uint64_t a) __attribute__ ((pure, always_inline));
ODY_SMMUX_S_GERRORN(uint64_t a)4431 static inline uint64_t ODY_SMMUX_S_GERRORN(uint64_t a)
4432 {
4433 if (a <= 3)
4434 return 0x830000008064ll + 0x1000000000ll * ((a) & 0x3);
4435 __ody_csr_fatal("SMMUX_S_GERRORN", 1, a, 0, 0, 0, 0, 0);
4436 }
4437
4438 #define typedef_ODY_SMMUX_S_GERRORN(a) ody_smmux_s_gerrorn_t
4439 #define bustype_ODY_SMMUX_S_GERRORN(a) CSR_TYPE_NCB32b
4440 #define basename_ODY_SMMUX_S_GERRORN(a) "SMMUX_S_GERRORN"
4441 #define device_bar_ODY_SMMUX_S_GERRORN(a) 0x0 /* PF_BAR0 */
4442 #define busnum_ODY_SMMUX_S_GERRORN(a) (a)
4443 #define arguments_ODY_SMMUX_S_GERRORN(a) (a), -1, -1, -1
4444
4445 /**
4446 * Register (NCB32b) smmu#_s_gmpam
4447 *
4448 * SMMU Global MPAM Configuration for secure state Register
4449 */
4450 union ody_smmux_s_gmpam {
4451 uint32_t u;
4452 struct ody_smmux_s_gmpam_s {
4453 uint32_t so_partid : 9;
4454 uint32_t reserved_9_15 : 7;
4455 uint32_t so_pmg : 1;
4456 uint32_t reserved_17_23 : 7;
4457 uint32_t mpam_ns : 1;
4458 uint32_t reserved_25_30 : 6;
4459 uint32_t update : 1;
4460 } s;
4461 /* struct ody_smmux_s_gmpam_s cn; */
4462 };
4463 typedef union ody_smmux_s_gmpam ody_smmux_s_gmpam_t;
4464
4465 static inline uint64_t ODY_SMMUX_S_GMPAM(uint64_t a) __attribute__ ((pure, always_inline));
ODY_SMMUX_S_GMPAM(uint64_t a)4466 static inline uint64_t ODY_SMMUX_S_GMPAM(uint64_t a)
4467 {
4468 if (a <= 3)
4469 return 0x830000008138ll + 0x1000000000ll * ((a) & 0x3);
4470 __ody_csr_fatal("SMMUX_S_GMPAM", 1, a, 0, 0, 0, 0, 0);
4471 }
4472
4473 #define typedef_ODY_SMMUX_S_GMPAM(a) ody_smmux_s_gmpam_t
4474 #define bustype_ODY_SMMUX_S_GMPAM(a) CSR_TYPE_NCB32b
4475 #define basename_ODY_SMMUX_S_GMPAM(a) "SMMUX_S_GMPAM"
4476 #define device_bar_ODY_SMMUX_S_GMPAM(a) 0x0 /* PF_BAR0 */
4477 #define busnum_ODY_SMMUX_S_GMPAM(a) (a)
4478 #define arguments_ODY_SMMUX_S_GMPAM(a) (a), -1, -1, -1
4479
4480 /**
4481 * Register (NCB32b) smmu#_s_idr0
4482 *
4483 * SMMU Secure IDR0 Register
4484 */
4485 union ody_smmux_s_idr0 {
4486 uint32_t u;
4487 struct ody_smmux_s_idr0_s {
4488 uint32_t reserved_0_12 : 13;
4489 uint32_t msi : 1;
4490 uint32_t reserved_14_23 : 10;
4491 uint32_t stall_model : 2;
4492 uint32_t reserved_26_30 : 5;
4493 uint32_t ecmdq : 1;
4494 } s;
4495 /* struct ody_smmux_s_idr0_s cn; */
4496 };
4497 typedef union ody_smmux_s_idr0 ody_smmux_s_idr0_t;
4498
4499 static inline uint64_t ODY_SMMUX_S_IDR0(uint64_t a) __attribute__ ((pure, always_inline));
ODY_SMMUX_S_IDR0(uint64_t a)4500 static inline uint64_t ODY_SMMUX_S_IDR0(uint64_t a)
4501 {
4502 if (a <= 3)
4503 return 0x830000008000ll + 0x1000000000ll * ((a) & 0x3);
4504 __ody_csr_fatal("SMMUX_S_IDR0", 1, a, 0, 0, 0, 0, 0);
4505 }
4506
4507 #define typedef_ODY_SMMUX_S_IDR0(a) ody_smmux_s_idr0_t
4508 #define bustype_ODY_SMMUX_S_IDR0(a) CSR_TYPE_NCB32b
4509 #define basename_ODY_SMMUX_S_IDR0(a) "SMMUX_S_IDR0"
4510 #define device_bar_ODY_SMMUX_S_IDR0(a) 0x0 /* PF_BAR0 */
4511 #define busnum_ODY_SMMUX_S_IDR0(a) (a)
4512 #define arguments_ODY_SMMUX_S_IDR0(a) (a), -1, -1, -1
4513
4514 /**
4515 * Register (NCB32b) smmu#_s_idr1
4516 *
4517 * SMMU Secure IDR1 Register
4518 */
4519 union ody_smmux_s_idr1 {
4520 uint32_t u;
4521 struct ody_smmux_s_idr1_s {
4522 uint32_t s_sidsize : 6;
4523 uint32_t reserved_6_28 : 23;
4524 uint32_t sel2 : 1;
4525 uint32_t reserved_30 : 1;
4526 uint32_t secure_impl : 1;
4527 } s;
4528 /* struct ody_smmux_s_idr1_s cn; */
4529 };
4530 typedef union ody_smmux_s_idr1 ody_smmux_s_idr1_t;
4531
4532 static inline uint64_t ODY_SMMUX_S_IDR1(uint64_t a) __attribute__ ((pure, always_inline));
ODY_SMMUX_S_IDR1(uint64_t a)4533 static inline uint64_t ODY_SMMUX_S_IDR1(uint64_t a)
4534 {
4535 if (a <= 3)
4536 return 0x830000008004ll + 0x1000000000ll * ((a) & 0x3);
4537 __ody_csr_fatal("SMMUX_S_IDR1", 1, a, 0, 0, 0, 0, 0);
4538 }
4539
4540 #define typedef_ODY_SMMUX_S_IDR1(a) ody_smmux_s_idr1_t
4541 #define bustype_ODY_SMMUX_S_IDR1(a) CSR_TYPE_NCB32b
4542 #define basename_ODY_SMMUX_S_IDR1(a) "SMMUX_S_IDR1"
4543 #define device_bar_ODY_SMMUX_S_IDR1(a) 0x0 /* PF_BAR0 */
4544 #define busnum_ODY_SMMUX_S_IDR1(a) (a)
4545 #define arguments_ODY_SMMUX_S_IDR1(a) (a), -1, -1, -1
4546
4547 /**
4548 * Register (NCB32b) smmu#_s_idr2
4549 *
4550 * SMMU Secure IDR2 Register
4551 */
4552 union ody_smmux_s_idr2 {
4553 uint32_t u;
4554 struct ody_smmux_s_idr2_s {
4555 uint32_t ba_s_vatos : 10;
4556 uint32_t reserved_10_31 : 22;
4557 } s;
4558 /* struct ody_smmux_s_idr2_s cn; */
4559 };
4560 typedef union ody_smmux_s_idr2 ody_smmux_s_idr2_t;
4561
4562 static inline uint64_t ODY_SMMUX_S_IDR2(uint64_t a) __attribute__ ((pure, always_inline));
ODY_SMMUX_S_IDR2(uint64_t a)4563 static inline uint64_t ODY_SMMUX_S_IDR2(uint64_t a)
4564 {
4565 if (a <= 3)
4566 return 0x830000008008ll + 0x1000000000ll * ((a) & 0x3);
4567 __ody_csr_fatal("SMMUX_S_IDR2", 1, a, 0, 0, 0, 0, 0);
4568 }
4569
4570 #define typedef_ODY_SMMUX_S_IDR2(a) ody_smmux_s_idr2_t
4571 #define bustype_ODY_SMMUX_S_IDR2(a) CSR_TYPE_NCB32b
4572 #define basename_ODY_SMMUX_S_IDR2(a) "SMMUX_S_IDR2"
4573 #define device_bar_ODY_SMMUX_S_IDR2(a) 0x0 /* PF_BAR0 */
4574 #define busnum_ODY_SMMUX_S_IDR2(a) (a)
4575 #define arguments_ODY_SMMUX_S_IDR2(a) (a), -1, -1, -1
4576
4577 /**
4578 * Register (NCB32b) smmu#_s_idr3
4579 *
4580 * SMMU Secure IDR3 Register
4581 */
4582 union ody_smmux_s_idr3 {
4583 uint32_t u;
4584 struct ody_smmux_s_idr3_s {
4585 uint32_t reserved_0_5 : 6;
4586 uint32_t sams : 1;
4587 uint32_t reserved_7_31 : 25;
4588 } s;
4589 /* struct ody_smmux_s_idr3_s cn; */
4590 };
4591 typedef union ody_smmux_s_idr3 ody_smmux_s_idr3_t;
4592
4593 static inline uint64_t ODY_SMMUX_S_IDR3(uint64_t a) __attribute__ ((pure, always_inline));
ODY_SMMUX_S_IDR3(uint64_t a)4594 static inline uint64_t ODY_SMMUX_S_IDR3(uint64_t a)
4595 {
4596 if (a <= 3)
4597 return 0x83000000800cll + 0x1000000000ll * ((a) & 0x3);
4598 __ody_csr_fatal("SMMUX_S_IDR3", 1, a, 0, 0, 0, 0, 0);
4599 }
4600
4601 #define typedef_ODY_SMMUX_S_IDR3(a) ody_smmux_s_idr3_t
4602 #define bustype_ODY_SMMUX_S_IDR3(a) CSR_TYPE_NCB32b
4603 #define basename_ODY_SMMUX_S_IDR3(a) "SMMUX_S_IDR3"
4604 #define device_bar_ODY_SMMUX_S_IDR3(a) 0x0 /* PF_BAR0 */
4605 #define busnum_ODY_SMMUX_S_IDR3(a) (a)
4606 #define arguments_ODY_SMMUX_S_IDR3(a) (a), -1, -1, -1
4607
4608 /**
4609 * Register (NCB32b) smmu#_s_idr4
4610 *
4611 * SMMU Secure IDR4 Register
4612 */
4613 union ody_smmux_s_idr4 {
4614 uint32_t u;
4615 struct ody_smmux_s_idr4_s {
4616 uint32_t reserved_0_31 : 32;
4617 } s;
4618 /* struct ody_smmux_s_idr4_s cn; */
4619 };
4620 typedef union ody_smmux_s_idr4 ody_smmux_s_idr4_t;
4621
4622 static inline uint64_t ODY_SMMUX_S_IDR4(uint64_t a) __attribute__ ((pure, always_inline));
ODY_SMMUX_S_IDR4(uint64_t a)4623 static inline uint64_t ODY_SMMUX_S_IDR4(uint64_t a)
4624 {
4625 if (a <= 3)
4626 return 0x830000008010ll + 0x1000000000ll * ((a) & 0x3);
4627 __ody_csr_fatal("SMMUX_S_IDR4", 1, a, 0, 0, 0, 0, 0);
4628 }
4629
4630 #define typedef_ODY_SMMUX_S_IDR4(a) ody_smmux_s_idr4_t
4631 #define bustype_ODY_SMMUX_S_IDR4(a) CSR_TYPE_NCB32b
4632 #define basename_ODY_SMMUX_S_IDR4(a) "SMMUX_S_IDR4"
4633 #define device_bar_ODY_SMMUX_S_IDR4(a) 0x0 /* PF_BAR0 */
4634 #define busnum_ODY_SMMUX_S_IDR4(a) (a)
4635 #define arguments_ODY_SMMUX_S_IDR4(a) (a), -1, -1, -1
4636
4637 /**
4638 * Register (NCB32b) smmu#_s_imp_actlr
4639 *
4640 * SMMU Auxiliary Control Register
4641 */
4642 union ody_smmux_s_imp_actlr {
4643 uint32_t u;
4644 struct ody_smmux_s_imp_actlr_s {
4645 uint32_t qos : 4;
4646 uint32_t reserved_4_31 : 28;
4647 } s;
4648 /* struct ody_smmux_s_imp_actlr_s cn; */
4649 };
4650 typedef union ody_smmux_s_imp_actlr ody_smmux_s_imp_actlr_t;
4651
4652 static inline uint64_t ODY_SMMUX_S_IMP_ACTLR(uint64_t a) __attribute__ ((pure, always_inline));
ODY_SMMUX_S_IMP_ACTLR(uint64_t a)4653 static inline uint64_t ODY_SMMUX_S_IMP_ACTLR(uint64_t a)
4654 {
4655 if (a <= 3)
4656 return 0x830000008e10ll + 0x1000000000ll * ((a) & 0x3);
4657 __ody_csr_fatal("SMMUX_S_IMP_ACTLR", 1, a, 0, 0, 0, 0, 0);
4658 }
4659
4660 #define typedef_ODY_SMMUX_S_IMP_ACTLR(a) ody_smmux_s_imp_actlr_t
4661 #define bustype_ODY_SMMUX_S_IMP_ACTLR(a) CSR_TYPE_NCB32b
4662 #define basename_ODY_SMMUX_S_IMP_ACTLR(a) "SMMUX_S_IMP_ACTLR"
4663 #define device_bar_ODY_SMMUX_S_IMP_ACTLR(a) 0x0 /* PF_BAR0 */
4664 #define busnum_ODY_SMMUX_S_IMP_ACTLR(a) (a)
4665 #define arguments_ODY_SMMUX_S_IMP_ACTLR(a) (a), -1, -1, -1
4666
4667 /**
4668 * Register (NCB32b) smmu#_s_imp_chicken_bits
4669 *
4670 * SMMU chicken bits Register
4671 */
4672 union ody_smmux_s_imp_chicken_bits {
4673 uint32_t u;
4674 struct ody_smmux_s_imp_chicken_bits_s {
4675 uint32_t httu_chicken_bits : 2;
4676 uint32_t wlk_dup_dis : 1;
4677 uint32_t dwb_all : 1;
4678 uint32_t ind_pnu_zero_enable : 1;
4679 uint32_t reserved_5_7 : 3;
4680 uint32_t pem_enable : 4;
4681 uint32_t reserved_12_31 : 20;
4682 } s;
4683 struct ody_smmux_s_imp_chicken_bits_cn {
4684 uint32_t httu_chicken_bits : 2;
4685 uint32_t wlk_dup_dis : 1;
4686 uint32_t dwb_all : 1;
4687 uint32_t ind_pnu_zero_enable : 1;
4688 uint32_t reserved_5_7 : 3;
4689 uint32_t pem_enable : 4;
4690 uint32_t reserved_12_15 : 4;
4691 uint32_t reserved_16_31 : 16;
4692 } cn;
4693 };
4694 typedef union ody_smmux_s_imp_chicken_bits ody_smmux_s_imp_chicken_bits_t;
4695
4696 static inline uint64_t ODY_SMMUX_S_IMP_CHICKEN_BITS(uint64_t a) __attribute__ ((pure, always_inline));
ODY_SMMUX_S_IMP_CHICKEN_BITS(uint64_t a)4697 static inline uint64_t ODY_SMMUX_S_IMP_CHICKEN_BITS(uint64_t a)
4698 {
4699 if (a <= 3)
4700 return 0x830000008e78ll + 0x1000000000ll * ((a) & 0x3);
4701 __ody_csr_fatal("SMMUX_S_IMP_CHICKEN_BITS", 1, a, 0, 0, 0, 0, 0);
4702 }
4703
4704 #define typedef_ODY_SMMUX_S_IMP_CHICKEN_BITS(a) ody_smmux_s_imp_chicken_bits_t
4705 #define bustype_ODY_SMMUX_S_IMP_CHICKEN_BITS(a) CSR_TYPE_NCB32b
4706 #define basename_ODY_SMMUX_S_IMP_CHICKEN_BITS(a) "SMMUX_S_IMP_CHICKEN_BITS"
4707 #define device_bar_ODY_SMMUX_S_IMP_CHICKEN_BITS(a) 0x0 /* PF_BAR0 */
4708 #define busnum_ODY_SMMUX_S_IMP_CHICKEN_BITS(a) (a)
4709 #define arguments_ODY_SMMUX_S_IMP_CHICKEN_BITS(a) (a), -1, -1, -1
4710
4711 /**
4712 * Register (NCB32b) smmu#_s_imp_diag_ctl
4713 *
4714 * SMMU Secure Diagnostic Control Register
4715 */
4716 union ody_smmux_s_imp_diag_ctl {
4717 uint32_t u;
4718 struct ody_smmux_s_imp_diag_ctl_s {
4719 uint32_t walkers : 6;
4720 uint32_t dis_wcs2 : 2;
4721 uint32_t dis_wcs1 : 2;
4722 uint32_t dis_tlb : 1;
4723 uint32_t dis_cfc : 1;
4724 uint32_t force_clks_active : 1;
4725 uint32_t force_tlb_clk_active : 1;
4726 uint32_t force_wlk_clk_active : 1;
4727 uint32_t force_out_clk_active : 1;
4728 uint32_t force_cmd_clk_active : 1;
4729 uint32_t force_crs_clk_active : 1;
4730 uint32_t force_csr_clk_active : 1;
4731 uint32_t force_cra_clk_active : 1;
4732 uint32_t force_inp_clk_active : 1;
4733 uint32_t force_fxl_clk_active : 1;
4734 uint32_t force_pri_clk_active : 1;
4735 uint32_t force_atc_clk_active : 1;
4736 uint32_t reserved_24_31 : 8;
4737 } s;
4738 /* struct ody_smmux_s_imp_diag_ctl_s cn; */
4739 };
4740 typedef union ody_smmux_s_imp_diag_ctl ody_smmux_s_imp_diag_ctl_t;
4741
4742 static inline uint64_t ODY_SMMUX_S_IMP_DIAG_CTL(uint64_t a) __attribute__ ((pure, always_inline));
ODY_SMMUX_S_IMP_DIAG_CTL(uint64_t a)4743 static inline uint64_t ODY_SMMUX_S_IMP_DIAG_CTL(uint64_t a)
4744 {
4745 if (a <= 3)
4746 return 0x830000008e14ll + 0x1000000000ll * ((a) & 0x3);
4747 __ody_csr_fatal("SMMUX_S_IMP_DIAG_CTL", 1, a, 0, 0, 0, 0, 0);
4748 }
4749
4750 #define typedef_ODY_SMMUX_S_IMP_DIAG_CTL(a) ody_smmux_s_imp_diag_ctl_t
4751 #define bustype_ODY_SMMUX_S_IMP_DIAG_CTL(a) CSR_TYPE_NCB32b
4752 #define basename_ODY_SMMUX_S_IMP_DIAG_CTL(a) "SMMUX_S_IMP_DIAG_CTL"
4753 #define device_bar_ODY_SMMUX_S_IMP_DIAG_CTL(a) 0x0 /* PF_BAR0 */
4754 #define busnum_ODY_SMMUX_S_IMP_DIAG_CTL(a) (a)
4755 #define arguments_ODY_SMMUX_S_IMP_DIAG_CTL(a) (a), -1, -1, -1
4756
4757 /**
4758 * Register (NCB32b) smmu#_s_imp_fifo_threshold
4759 *
4760 * SMMU FIFO Threshold Register
4761 */
4762 union ody_smmux_s_imp_fifo_threshold {
4763 uint32_t u;
4764 struct ody_smmux_s_imp_fifo_threshold_s {
4765 uint32_t rpb_safety_threshold : 7;
4766 uint32_t reserved_7_31 : 25;
4767 } s;
4768 /* struct ody_smmux_s_imp_fifo_threshold_s cn; */
4769 };
4770 typedef union ody_smmux_s_imp_fifo_threshold ody_smmux_s_imp_fifo_threshold_t;
4771
4772 static inline uint64_t ODY_SMMUX_S_IMP_FIFO_THRESHOLD(uint64_t a) __attribute__ ((pure, always_inline));
ODY_SMMUX_S_IMP_FIFO_THRESHOLD(uint64_t a)4773 static inline uint64_t ODY_SMMUX_S_IMP_FIFO_THRESHOLD(uint64_t a)
4774 {
4775 if (a <= 3)
4776 return 0x830000008e60ll + 0x1000000000ll * ((a) & 0x3);
4777 __ody_csr_fatal("SMMUX_S_IMP_FIFO_THRESHOLD", 1, a, 0, 0, 0, 0, 0);
4778 }
4779
4780 #define typedef_ODY_SMMUX_S_IMP_FIFO_THRESHOLD(a) ody_smmux_s_imp_fifo_threshold_t
4781 #define bustype_ODY_SMMUX_S_IMP_FIFO_THRESHOLD(a) CSR_TYPE_NCB32b
4782 #define basename_ODY_SMMUX_S_IMP_FIFO_THRESHOLD(a) "SMMUX_S_IMP_FIFO_THRESHOLD"
4783 #define device_bar_ODY_SMMUX_S_IMP_FIFO_THRESHOLD(a) 0x0 /* PF_BAR0 */
4784 #define busnum_ODY_SMMUX_S_IMP_FIFO_THRESHOLD(a) (a)
4785 #define arguments_ODY_SMMUX_S_IMP_FIFO_THRESHOLD(a) (a), -1, -1, -1
4786
4787 /**
4788 * Register (NCB32b) smmu#_s_imp_long_rbi
4789 *
4790 * SMMU Range-based TLBI To Slow TLBI Conversion Register
4791 * This register controls conversion of a range-based TLBI into a slow TLBI.
4792 */
4793 union ody_smmux_s_imp_long_rbi {
4794 uint32_t u;
4795 struct ody_smmux_s_imp_long_rbi_s {
4796 uint32_t cmd_long_rbi_log2limit : 5;
4797 uint32_t cmd_long_rbi_force_dis : 1;
4798 uint32_t cmd_long_rbi_force_en : 1;
4799 uint32_t reserved_7_15 : 9;
4800 uint32_t dvm_long_rbi_log2limit : 5;
4801 uint32_t dvm_long_rbi_force_dis : 1;
4802 uint32_t dvm_long_rbi_force_en : 1;
4803 uint32_t reserved_23_31 : 9;
4804 } s;
4805 /* struct ody_smmux_s_imp_long_rbi_s cn; */
4806 };
4807 typedef union ody_smmux_s_imp_long_rbi ody_smmux_s_imp_long_rbi_t;
4808
4809 static inline uint64_t ODY_SMMUX_S_IMP_LONG_RBI(uint64_t a) __attribute__ ((pure, always_inline));
ODY_SMMUX_S_IMP_LONG_RBI(uint64_t a)4810 static inline uint64_t ODY_SMMUX_S_IMP_LONG_RBI(uint64_t a)
4811 {
4812 if (a <= 3)
4813 return 0x830000008e70ll + 0x1000000000ll * ((a) & 0x3);
4814 __ody_csr_fatal("SMMUX_S_IMP_LONG_RBI", 1, a, 0, 0, 0, 0, 0);
4815 }
4816
4817 #define typedef_ODY_SMMUX_S_IMP_LONG_RBI(a) ody_smmux_s_imp_long_rbi_t
4818 #define bustype_ODY_SMMUX_S_IMP_LONG_RBI(a) CSR_TYPE_NCB32b
4819 #define basename_ODY_SMMUX_S_IMP_LONG_RBI(a) "SMMUX_S_IMP_LONG_RBI"
4820 #define device_bar_ODY_SMMUX_S_IMP_LONG_RBI(a) 0x0 /* PF_BAR0 */
4821 #define busnum_ODY_SMMUX_S_IMP_LONG_RBI(a) (a)
4822 #define arguments_ODY_SMMUX_S_IMP_LONG_RBI(a) (a), -1, -1, -1
4823
4824 /**
4825 * Register (NCB32b) smmu#_s_imp_prefetch_addr_cap
4826 *
4827 * SMMU Prepeftc Addr Cap Register
4828 */
4829 union ody_smmux_s_imp_prefetch_addr_cap {
4830 uint32_t u;
4831 struct ody_smmux_s_imp_prefetch_addr_cap_s {
4832 uint32_t prefetch_addr_cap : 5;
4833 uint32_t prefetch_addr_cap_valid : 1;
4834 uint32_t fxl_prefetch_dis : 1;
4835 uint32_t reserved_7_31 : 25;
4836 } s;
4837 /* struct ody_smmux_s_imp_prefetch_addr_cap_s cn; */
4838 };
4839 typedef union ody_smmux_s_imp_prefetch_addr_cap ody_smmux_s_imp_prefetch_addr_cap_t;
4840
4841 static inline uint64_t ODY_SMMUX_S_IMP_PREFETCH_ADDR_CAP(uint64_t a) __attribute__ ((pure, always_inline));
ODY_SMMUX_S_IMP_PREFETCH_ADDR_CAP(uint64_t a)4842 static inline uint64_t ODY_SMMUX_S_IMP_PREFETCH_ADDR_CAP(uint64_t a)
4843 {
4844 if (a <= 3)
4845 return 0x830000008e88ll + 0x1000000000ll * ((a) & 0x3);
4846 __ody_csr_fatal("SMMUX_S_IMP_PREFETCH_ADDR_CAP", 1, a, 0, 0, 0, 0, 0);
4847 }
4848
4849 #define typedef_ODY_SMMUX_S_IMP_PREFETCH_ADDR_CAP(a) ody_smmux_s_imp_prefetch_addr_cap_t
4850 #define bustype_ODY_SMMUX_S_IMP_PREFETCH_ADDR_CAP(a) CSR_TYPE_NCB32b
4851 #define basename_ODY_SMMUX_S_IMP_PREFETCH_ADDR_CAP(a) "SMMUX_S_IMP_PREFETCH_ADDR_CAP"
4852 #define device_bar_ODY_SMMUX_S_IMP_PREFETCH_ADDR_CAP(a) 0x0 /* PF_BAR0 */
4853 #define busnum_ODY_SMMUX_S_IMP_PREFETCH_ADDR_CAP(a) (a)
4854 #define arguments_ODY_SMMUX_S_IMP_PREFETCH_ADDR_CAP(a) (a), -1, -1, -1
4855
4856 /**
4857 * Register (NCB) smmu#_s_imp_ras_ctl
4858 *
4859 * SMMU RAS Control Register
4860 */
4861 union ody_smmux_s_imp_ras_ctl {
4862 uint64_t u;
4863 struct ody_smmux_s_imp_ras_ctl_s {
4864 uint64_t rd_psn_ign : 1;
4865 uint64_t reserved_1_63 : 63;
4866 } s;
4867 /* struct ody_smmux_s_imp_ras_ctl_s cn; */
4868 };
4869 typedef union ody_smmux_s_imp_ras_ctl ody_smmux_s_imp_ras_ctl_t;
4870
4871 static inline uint64_t ODY_SMMUX_S_IMP_RAS_CTL(uint64_t a) __attribute__ ((pure, always_inline));
ODY_SMMUX_S_IMP_RAS_CTL(uint64_t a)4872 static inline uint64_t ODY_SMMUX_S_IMP_RAS_CTL(uint64_t a)
4873 {
4874 if (a <= 3)
4875 return 0x830000008e50ll + 0x1000000000ll * ((a) & 0x3);
4876 __ody_csr_fatal("SMMUX_S_IMP_RAS_CTL", 1, a, 0, 0, 0, 0, 0);
4877 }
4878
4879 #define typedef_ODY_SMMUX_S_IMP_RAS_CTL(a) ody_smmux_s_imp_ras_ctl_t
4880 #define bustype_ODY_SMMUX_S_IMP_RAS_CTL(a) CSR_TYPE_NCB
4881 #define basename_ODY_SMMUX_S_IMP_RAS_CTL(a) "SMMUX_S_IMP_RAS_CTL"
4882 #define device_bar_ODY_SMMUX_S_IMP_RAS_CTL(a) 0x0 /* PF_BAR0 */
4883 #define busnum_ODY_SMMUX_S_IMP_RAS_CTL(a) (a)
4884 #define arguments_ODY_SMMUX_S_IMP_RAS_CTL(a) (a), -1, -1, -1
4885
4886 /**
4887 * Register (NCB32b) smmu#_s_imp_ras_int
4888 *
4889 * SMMU RAS Interrupt Register
4890 */
4891 union ody_smmux_s_imp_ras_int {
4892 uint32_t u;
4893 struct ody_smmux_s_imp_ras_int_s {
4894 uint32_t ns_cmdq_psn : 1;
4895 uint32_t s_cmdq_psn : 1;
4896 uint32_t fetch_psn : 1;
4897 uint32_t reserved_3_31 : 29;
4898 } s;
4899 /* struct ody_smmux_s_imp_ras_int_s cn; */
4900 };
4901 typedef union ody_smmux_s_imp_ras_int ody_smmux_s_imp_ras_int_t;
4902
4903 static inline uint64_t ODY_SMMUX_S_IMP_RAS_INT(uint64_t a) __attribute__ ((pure, always_inline));
ODY_SMMUX_S_IMP_RAS_INT(uint64_t a)4904 static inline uint64_t ODY_SMMUX_S_IMP_RAS_INT(uint64_t a)
4905 {
4906 if (a <= 3)
4907 return 0x830000008e20ll + 0x1000000000ll * ((a) & 0x3);
4908 __ody_csr_fatal("SMMUX_S_IMP_RAS_INT", 1, a, 0, 0, 0, 0, 0);
4909 }
4910
4911 #define typedef_ODY_SMMUX_S_IMP_RAS_INT(a) ody_smmux_s_imp_ras_int_t
4912 #define bustype_ODY_SMMUX_S_IMP_RAS_INT(a) CSR_TYPE_NCB32b
4913 #define basename_ODY_SMMUX_S_IMP_RAS_INT(a) "SMMUX_S_IMP_RAS_INT"
4914 #define device_bar_ODY_SMMUX_S_IMP_RAS_INT(a) 0x0 /* PF_BAR0 */
4915 #define busnum_ODY_SMMUX_S_IMP_RAS_INT(a) (a)
4916 #define arguments_ODY_SMMUX_S_IMP_RAS_INT(a) (a), -1, -1, -1
4917
4918 /**
4919 * Register (NCB32b) smmu#_s_imp_ras_int_ena_w1c
4920 *
4921 * SMMU RAS Interrupt Enable Set Register
4922 * This register clears interrupt enable bits.
4923 */
4924 union ody_smmux_s_imp_ras_int_ena_w1c {
4925 uint32_t u;
4926 struct ody_smmux_s_imp_ras_int_ena_w1c_s {
4927 uint32_t ns_cmdq_psn : 1;
4928 uint32_t s_cmdq_psn : 1;
4929 uint32_t fetch_psn : 1;
4930 uint32_t reserved_3_31 : 29;
4931 } s;
4932 /* struct ody_smmux_s_imp_ras_int_ena_w1c_s cn; */
4933 };
4934 typedef union ody_smmux_s_imp_ras_int_ena_w1c ody_smmux_s_imp_ras_int_ena_w1c_t;
4935
4936 static inline uint64_t ODY_SMMUX_S_IMP_RAS_INT_ENA_W1C(uint64_t a) __attribute__ ((pure, always_inline));
ODY_SMMUX_S_IMP_RAS_INT_ENA_W1C(uint64_t a)4937 static inline uint64_t ODY_SMMUX_S_IMP_RAS_INT_ENA_W1C(uint64_t a)
4938 {
4939 if (a <= 3)
4940 return 0x830000008e38ll + 0x1000000000ll * ((a) & 0x3);
4941 __ody_csr_fatal("SMMUX_S_IMP_RAS_INT_ENA_W1C", 1, a, 0, 0, 0, 0, 0);
4942 }
4943
4944 #define typedef_ODY_SMMUX_S_IMP_RAS_INT_ENA_W1C(a) ody_smmux_s_imp_ras_int_ena_w1c_t
4945 #define bustype_ODY_SMMUX_S_IMP_RAS_INT_ENA_W1C(a) CSR_TYPE_NCB32b
4946 #define basename_ODY_SMMUX_S_IMP_RAS_INT_ENA_W1C(a) "SMMUX_S_IMP_RAS_INT_ENA_W1C"
4947 #define device_bar_ODY_SMMUX_S_IMP_RAS_INT_ENA_W1C(a) 0x0 /* PF_BAR0 */
4948 #define busnum_ODY_SMMUX_S_IMP_RAS_INT_ENA_W1C(a) (a)
4949 #define arguments_ODY_SMMUX_S_IMP_RAS_INT_ENA_W1C(a) (a), -1, -1, -1
4950
4951 /**
4952 * Register (NCB32b) smmu#_s_imp_ras_int_ena_w1s
4953 *
4954 * SMMU RAS Interrupt Enable Set Register
4955 * This register sets interrupt enable bits.
4956 */
4957 union ody_smmux_s_imp_ras_int_ena_w1s {
4958 uint32_t u;
4959 struct ody_smmux_s_imp_ras_int_ena_w1s_s {
4960 uint32_t ns_cmdq_psn : 1;
4961 uint32_t s_cmdq_psn : 1;
4962 uint32_t fetch_psn : 1;
4963 uint32_t reserved_3_31 : 29;
4964 } s;
4965 /* struct ody_smmux_s_imp_ras_int_ena_w1s_s cn; */
4966 };
4967 typedef union ody_smmux_s_imp_ras_int_ena_w1s ody_smmux_s_imp_ras_int_ena_w1s_t;
4968
4969 static inline uint64_t ODY_SMMUX_S_IMP_RAS_INT_ENA_W1S(uint64_t a) __attribute__ ((pure, always_inline));
ODY_SMMUX_S_IMP_RAS_INT_ENA_W1S(uint64_t a)4970 static inline uint64_t ODY_SMMUX_S_IMP_RAS_INT_ENA_W1S(uint64_t a)
4971 {
4972 if (a <= 3)
4973 return 0x830000008e30ll + 0x1000000000ll * ((a) & 0x3);
4974 __ody_csr_fatal("SMMUX_S_IMP_RAS_INT_ENA_W1S", 1, a, 0, 0, 0, 0, 0);
4975 }
4976
4977 #define typedef_ODY_SMMUX_S_IMP_RAS_INT_ENA_W1S(a) ody_smmux_s_imp_ras_int_ena_w1s_t
4978 #define bustype_ODY_SMMUX_S_IMP_RAS_INT_ENA_W1S(a) CSR_TYPE_NCB32b
4979 #define basename_ODY_SMMUX_S_IMP_RAS_INT_ENA_W1S(a) "SMMUX_S_IMP_RAS_INT_ENA_W1S"
4980 #define device_bar_ODY_SMMUX_S_IMP_RAS_INT_ENA_W1S(a) 0x0 /* PF_BAR0 */
4981 #define busnum_ODY_SMMUX_S_IMP_RAS_INT_ENA_W1S(a) (a)
4982 #define arguments_ODY_SMMUX_S_IMP_RAS_INT_ENA_W1S(a) (a), -1, -1, -1
4983
4984 /**
4985 * Register (NCB32b) smmu#_s_imp_ras_int_w1s
4986 *
4987 * SMMU RAS Interrupt Set Register
4988 * This register sets interrupt bits.
4989 */
4990 union ody_smmux_s_imp_ras_int_w1s {
4991 uint32_t u;
4992 struct ody_smmux_s_imp_ras_int_w1s_s {
4993 uint32_t ns_cmdq_psn : 1;
4994 uint32_t s_cmdq_psn : 1;
4995 uint32_t fetch_psn : 1;
4996 uint32_t reserved_3_31 : 29;
4997 } s;
4998 /* struct ody_smmux_s_imp_ras_int_w1s_s cn; */
4999 };
5000 typedef union ody_smmux_s_imp_ras_int_w1s ody_smmux_s_imp_ras_int_w1s_t;
5001
5002 static inline uint64_t ODY_SMMUX_S_IMP_RAS_INT_W1S(uint64_t a) __attribute__ ((pure, always_inline));
ODY_SMMUX_S_IMP_RAS_INT_W1S(uint64_t a)5003 static inline uint64_t ODY_SMMUX_S_IMP_RAS_INT_W1S(uint64_t a)
5004 {
5005 if (a <= 3)
5006 return 0x830000008e28ll + 0x1000000000ll * ((a) & 0x3);
5007 __ody_csr_fatal("SMMUX_S_IMP_RAS_INT_W1S", 1, a, 0, 0, 0, 0, 0);
5008 }
5009
5010 #define typedef_ODY_SMMUX_S_IMP_RAS_INT_W1S(a) ody_smmux_s_imp_ras_int_w1s_t
5011 #define bustype_ODY_SMMUX_S_IMP_RAS_INT_W1S(a) CSR_TYPE_NCB32b
5012 #define basename_ODY_SMMUX_S_IMP_RAS_INT_W1S(a) "SMMUX_S_IMP_RAS_INT_W1S"
5013 #define device_bar_ODY_SMMUX_S_IMP_RAS_INT_W1S(a) 0x0 /* PF_BAR0 */
5014 #define busnum_ODY_SMMUX_S_IMP_RAS_INT_W1S(a) (a)
5015 #define arguments_ODY_SMMUX_S_IMP_RAS_INT_W1S(a) (a), -1, -1, -1
5016
5017 /**
5018 * Register (NCB) smmu#_s_imp_ras_irq_cfg0
5019 *
5020 * SMMU RAS Interrupt 0 Register
5021 */
5022 union ody_smmux_s_imp_ras_irq_cfg0 {
5023 uint64_t u;
5024 struct ody_smmux_s_imp_ras_irq_cfg0_s {
5025 uint64_t reserved_0_1 : 2;
5026 uint64_t addr : 50;
5027 uint64_t reserved_52_63 : 12;
5028 } s;
5029 /* struct ody_smmux_s_imp_ras_irq_cfg0_s cn; */
5030 };
5031 typedef union ody_smmux_s_imp_ras_irq_cfg0 ody_smmux_s_imp_ras_irq_cfg0_t;
5032
5033 static inline uint64_t ODY_SMMUX_S_IMP_RAS_IRQ_CFG0(uint64_t a) __attribute__ ((pure, always_inline));
ODY_SMMUX_S_IMP_RAS_IRQ_CFG0(uint64_t a)5034 static inline uint64_t ODY_SMMUX_S_IMP_RAS_IRQ_CFG0(uint64_t a)
5035 {
5036 if (a <= 3)
5037 return 0x830000008e40ll + 0x1000000000ll * ((a) & 0x3);
5038 __ody_csr_fatal("SMMUX_S_IMP_RAS_IRQ_CFG0", 1, a, 0, 0, 0, 0, 0);
5039 }
5040
5041 #define typedef_ODY_SMMUX_S_IMP_RAS_IRQ_CFG0(a) ody_smmux_s_imp_ras_irq_cfg0_t
5042 #define bustype_ODY_SMMUX_S_IMP_RAS_IRQ_CFG0(a) CSR_TYPE_NCB
5043 #define basename_ODY_SMMUX_S_IMP_RAS_IRQ_CFG0(a) "SMMUX_S_IMP_RAS_IRQ_CFG0"
5044 #define device_bar_ODY_SMMUX_S_IMP_RAS_IRQ_CFG0(a) 0x0 /* PF_BAR0 */
5045 #define busnum_ODY_SMMUX_S_IMP_RAS_IRQ_CFG0(a) (a)
5046 #define arguments_ODY_SMMUX_S_IMP_RAS_IRQ_CFG0(a) (a), -1, -1, -1
5047
5048 /**
5049 * Register (NCB32b) smmu#_s_imp_ras_irq_cfg1
5050 *
5051 * SMMU RAS Interrupt 1 Register
5052 */
5053 union ody_smmux_s_imp_ras_irq_cfg1 {
5054 uint32_t u;
5055 struct ody_smmux_s_imp_ras_irq_cfg1_s {
5056 uint32_t data : 32;
5057 } s;
5058 /* struct ody_smmux_s_imp_ras_irq_cfg1_s cn; */
5059 };
5060 typedef union ody_smmux_s_imp_ras_irq_cfg1 ody_smmux_s_imp_ras_irq_cfg1_t;
5061
5062 static inline uint64_t ODY_SMMUX_S_IMP_RAS_IRQ_CFG1(uint64_t a) __attribute__ ((pure, always_inline));
ODY_SMMUX_S_IMP_RAS_IRQ_CFG1(uint64_t a)5063 static inline uint64_t ODY_SMMUX_S_IMP_RAS_IRQ_CFG1(uint64_t a)
5064 {
5065 if (a <= 3)
5066 return 0x830000008e48ll + 0x1000000000ll * ((a) & 0x3);
5067 __ody_csr_fatal("SMMUX_S_IMP_RAS_IRQ_CFG1", 1, a, 0, 0, 0, 0, 0);
5068 }
5069
5070 #define typedef_ODY_SMMUX_S_IMP_RAS_IRQ_CFG1(a) ody_smmux_s_imp_ras_irq_cfg1_t
5071 #define bustype_ODY_SMMUX_S_IMP_RAS_IRQ_CFG1(a) CSR_TYPE_NCB32b
5072 #define basename_ODY_SMMUX_S_IMP_RAS_IRQ_CFG1(a) "SMMUX_S_IMP_RAS_IRQ_CFG1"
5073 #define device_bar_ODY_SMMUX_S_IMP_RAS_IRQ_CFG1(a) 0x0 /* PF_BAR0 */
5074 #define busnum_ODY_SMMUX_S_IMP_RAS_IRQ_CFG1(a) (a)
5075 #define arguments_ODY_SMMUX_S_IMP_RAS_IRQ_CFG1(a) (a), -1, -1, -1
5076
5077 /**
5078 * Register (NCB32b) smmu#_s_imp_txn_arb_weight
5079 *
5080 * SMMU Translation Arbitration Weight Register
5081 * This register contains weight values of arbitration between translation sources.
5082 */
5083 union ody_smmux_s_imp_txn_arb_weight {
5084 uint32_t u;
5085 struct ody_smmux_s_imp_txn_arb_weight_s {
5086 uint32_t txn_iob : 16;
5087 uint32_t imp_txn_src_weight : 1;
5088 uint32_t reserved_17_31 : 15;
5089 } s;
5090 /* struct ody_smmux_s_imp_txn_arb_weight_s cn; */
5091 };
5092 typedef union ody_smmux_s_imp_txn_arb_weight ody_smmux_s_imp_txn_arb_weight_t;
5093
5094 static inline uint64_t ODY_SMMUX_S_IMP_TXN_ARB_WEIGHT(uint64_t a) __attribute__ ((pure, always_inline));
ODY_SMMUX_S_IMP_TXN_ARB_WEIGHT(uint64_t a)5095 static inline uint64_t ODY_SMMUX_S_IMP_TXN_ARB_WEIGHT(uint64_t a)
5096 {
5097 if (a <= 3)
5098 return 0x830000008e68ll + 0x1000000000ll * ((a) & 0x3);
5099 __ody_csr_fatal("SMMUX_S_IMP_TXN_ARB_WEIGHT", 1, a, 0, 0, 0, 0, 0);
5100 }
5101
5102 #define typedef_ODY_SMMUX_S_IMP_TXN_ARB_WEIGHT(a) ody_smmux_s_imp_txn_arb_weight_t
5103 #define bustype_ODY_SMMUX_S_IMP_TXN_ARB_WEIGHT(a) CSR_TYPE_NCB32b
5104 #define basename_ODY_SMMUX_S_IMP_TXN_ARB_WEIGHT(a) "SMMUX_S_IMP_TXN_ARB_WEIGHT"
5105 #define device_bar_ODY_SMMUX_S_IMP_TXN_ARB_WEIGHT(a) 0x0 /* PF_BAR0 */
5106 #define busnum_ODY_SMMUX_S_IMP_TXN_ARB_WEIGHT(a) (a)
5107 #define arguments_ODY_SMMUX_S_IMP_TXN_ARB_WEIGHT(a) (a), -1, -1, -1
5108
5109 /**
5110 * Register (NCB32b) smmu#_s_imp_txreq_arb_weight
5111 *
5112 * SMMU Fetches Arbitration Weight Register
5113 * This register contains weight values of arbitration between SMMU fetches and store to
5114 * external memory.
5115 */
5116 union ody_smmux_s_imp_txreq_arb_weight {
5117 uint32_t u;
5118 struct ody_smmux_s_imp_txreq_arb_weight_s {
5119 uint32_t imp_event_store : 2;
5120 uint32_t imp_cmd_fetch : 2;
5121 uint32_t imp_walker_fetch : 2;
5122 uint32_t imp_pri_store : 2;
5123 uint32_t reserved_8_31 : 24;
5124 } s;
5125 /* struct ody_smmux_s_imp_txreq_arb_weight_s cn; */
5126 };
5127 typedef union ody_smmux_s_imp_txreq_arb_weight ody_smmux_s_imp_txreq_arb_weight_t;
5128
5129 static inline uint64_t ODY_SMMUX_S_IMP_TXREQ_ARB_WEIGHT(uint64_t a) __attribute__ ((pure, always_inline));
ODY_SMMUX_S_IMP_TXREQ_ARB_WEIGHT(uint64_t a)5130 static inline uint64_t ODY_SMMUX_S_IMP_TXREQ_ARB_WEIGHT(uint64_t a)
5131 {
5132 if (a <= 3)
5133 return 0x830000008e6cll + 0x1000000000ll * ((a) & 0x3);
5134 __ody_csr_fatal("SMMUX_S_IMP_TXREQ_ARB_WEIGHT", 1, a, 0, 0, 0, 0, 0);
5135 }
5136
5137 #define typedef_ODY_SMMUX_S_IMP_TXREQ_ARB_WEIGHT(a) ody_smmux_s_imp_txreq_arb_weight_t
5138 #define bustype_ODY_SMMUX_S_IMP_TXREQ_ARB_WEIGHT(a) CSR_TYPE_NCB32b
5139 #define basename_ODY_SMMUX_S_IMP_TXREQ_ARB_WEIGHT(a) "SMMUX_S_IMP_TXREQ_ARB_WEIGHT"
5140 #define device_bar_ODY_SMMUX_S_IMP_TXREQ_ARB_WEIGHT(a) 0x0 /* PF_BAR0 */
5141 #define busnum_ODY_SMMUX_S_IMP_TXREQ_ARB_WEIGHT(a) (a)
5142 #define arguments_ODY_SMMUX_S_IMP_TXREQ_ARB_WEIGHT(a) (a), -1, -1, -1
5143
5144 /**
5145 * Register (NCB32b) smmu#_s_imp_typ_arb_weight
5146 *
5147 * SMMU Translations Type Arbitration Weight Register
5148 * This register contains weight values of arbitration between translation types.
5149 */
5150 union ody_smmux_s_imp_typ_arb_weight {
5151 uint32_t u;
5152 struct ody_smmux_s_imp_typ_arb_weight_s {
5153 uint32_t imp_prefetch_s_prio : 3;
5154 uint32_t imp_prefetch_ns_prio : 3;
5155 uint32_t imp_gatos_s_prio : 3;
5156 uint32_t imp_gatos_ns_prio : 3;
5157 uint32_t imp_replay_prio : 3;
5158 uint32_t imp_txn_prio : 3;
5159 uint32_t reserved_18_31 : 14;
5160 } s;
5161 /* struct ody_smmux_s_imp_typ_arb_weight_s cn; */
5162 };
5163 typedef union ody_smmux_s_imp_typ_arb_weight ody_smmux_s_imp_typ_arb_weight_t;
5164
5165 static inline uint64_t ODY_SMMUX_S_IMP_TYP_ARB_WEIGHT(uint64_t a) __attribute__ ((pure, always_inline));
ODY_SMMUX_S_IMP_TYP_ARB_WEIGHT(uint64_t a)5166 static inline uint64_t ODY_SMMUX_S_IMP_TYP_ARB_WEIGHT(uint64_t a)
5167 {
5168 if (a <= 3)
5169 return 0x830000008e64ll + 0x1000000000ll * ((a) & 0x3);
5170 __ody_csr_fatal("SMMUX_S_IMP_TYP_ARB_WEIGHT", 1, a, 0, 0, 0, 0, 0);
5171 }
5172
5173 #define typedef_ODY_SMMUX_S_IMP_TYP_ARB_WEIGHT(a) ody_smmux_s_imp_typ_arb_weight_t
5174 #define bustype_ODY_SMMUX_S_IMP_TYP_ARB_WEIGHT(a) CSR_TYPE_NCB32b
5175 #define basename_ODY_SMMUX_S_IMP_TYP_ARB_WEIGHT(a) "SMMUX_S_IMP_TYP_ARB_WEIGHT"
5176 #define device_bar_ODY_SMMUX_S_IMP_TYP_ARB_WEIGHT(a) 0x0 /* PF_BAR0 */
5177 #define busnum_ODY_SMMUX_S_IMP_TYP_ARB_WEIGHT(a) (a)
5178 #define arguments_ODY_SMMUX_S_IMP_TYP_ARB_WEIGHT(a) (a), -1, -1, -1
5179
5180 /**
5181 * Register (NCB32b) smmu#_s_imp_wlk_dis
5182 *
5183 * SMMU Walker Disable Register
5184 */
5185 union ody_smmux_s_imp_wlk_dis {
5186 uint32_t u;
5187 struct ody_smmux_s_imp_wlk_dis_s {
5188 uint32_t wlk_dis : 32;
5189 } s;
5190 /* struct ody_smmux_s_imp_wlk_dis_s cn; */
5191 };
5192 typedef union ody_smmux_s_imp_wlk_dis ody_smmux_s_imp_wlk_dis_t;
5193
5194 static inline uint64_t ODY_SMMUX_S_IMP_WLK_DIS(uint64_t a) __attribute__ ((pure, always_inline));
ODY_SMMUX_S_IMP_WLK_DIS(uint64_t a)5195 static inline uint64_t ODY_SMMUX_S_IMP_WLK_DIS(uint64_t a)
5196 {
5197 if (a <= 3)
5198 return 0x830000008e80ll + 0x1000000000ll * ((a) & 0x3);
5199 __ody_csr_fatal("SMMUX_S_IMP_WLK_DIS", 1, a, 0, 0, 0, 0, 0);
5200 }
5201
5202 #define typedef_ODY_SMMUX_S_IMP_WLK_DIS(a) ody_smmux_s_imp_wlk_dis_t
5203 #define bustype_ODY_SMMUX_S_IMP_WLK_DIS(a) CSR_TYPE_NCB32b
5204 #define basename_ODY_SMMUX_S_IMP_WLK_DIS(a) "SMMUX_S_IMP_WLK_DIS"
5205 #define device_bar_ODY_SMMUX_S_IMP_WLK_DIS(a) 0x0 /* PF_BAR0 */
5206 #define busnum_ODY_SMMUX_S_IMP_WLK_DIS(a) (a)
5207 #define arguments_ODY_SMMUX_S_IMP_WLK_DIS(a) (a), -1, -1, -1
5208
5209 /**
5210 * Register (NCB32b) smmu#_s_imp_wlk_skip_lu
5211 *
5212 * SMMU Walker Skip Look Up Register
5213 */
5214 union ody_smmux_s_imp_wlk_skip_lu {
5215 uint32_t u;
5216 struct ody_smmux_s_imp_wlk_skip_lu_s {
5217 uint32_t skip : 31;
5218 uint32_t reserved_31 : 1;
5219 } s;
5220 /* struct ody_smmux_s_imp_wlk_skip_lu_s cn; */
5221 };
5222 typedef union ody_smmux_s_imp_wlk_skip_lu ody_smmux_s_imp_wlk_skip_lu_t;
5223
5224 static inline uint64_t ODY_SMMUX_S_IMP_WLK_SKIP_LU(uint64_t a) __attribute__ ((pure, always_inline));
ODY_SMMUX_S_IMP_WLK_SKIP_LU(uint64_t a)5225 static inline uint64_t ODY_SMMUX_S_IMP_WLK_SKIP_LU(uint64_t a)
5226 {
5227 if (a <= 3)
5228 return 0x830000008e84ll + 0x1000000000ll * ((a) & 0x3);
5229 __ody_csr_fatal("SMMUX_S_IMP_WLK_SKIP_LU", 1, a, 0, 0, 0, 0, 0);
5230 }
5231
5232 #define typedef_ODY_SMMUX_S_IMP_WLK_SKIP_LU(a) ody_smmux_s_imp_wlk_skip_lu_t
5233 #define bustype_ODY_SMMUX_S_IMP_WLK_SKIP_LU(a) CSR_TYPE_NCB32b
5234 #define basename_ODY_SMMUX_S_IMP_WLK_SKIP_LU(a) "SMMUX_S_IMP_WLK_SKIP_LU"
5235 #define device_bar_ODY_SMMUX_S_IMP_WLK_SKIP_LU(a) 0x0 /* PF_BAR0 */
5236 #define busnum_ODY_SMMUX_S_IMP_WLK_SKIP_LU(a) (a)
5237 #define arguments_ODY_SMMUX_S_IMP_WLK_SKIP_LU(a) (a), -1, -1, -1
5238
5239 /**
5240 * Register (NCB32b) smmu#_s_init
5241 *
5242 * SMMU Secure INIT Register
5243 */
5244 union ody_smmux_s_init {
5245 uint32_t u;
5246 struct ody_smmux_s_init_s {
5247 uint32_t inv_all : 1;
5248 uint32_t reserved_1_31 : 31;
5249 } s;
5250 /* struct ody_smmux_s_init_s cn; */
5251 };
5252 typedef union ody_smmux_s_init ody_smmux_s_init_t;
5253
5254 static inline uint64_t ODY_SMMUX_S_INIT(uint64_t a) __attribute__ ((pure, always_inline));
ODY_SMMUX_S_INIT(uint64_t a)5255 static inline uint64_t ODY_SMMUX_S_INIT(uint64_t a)
5256 {
5257 if (a <= 3)
5258 return 0x83000000803cll + 0x1000000000ll * ((a) & 0x3);
5259 __ody_csr_fatal("SMMUX_S_INIT", 1, a, 0, 0, 0, 0, 0);
5260 }
5261
5262 #define typedef_ODY_SMMUX_S_INIT(a) ody_smmux_s_init_t
5263 #define bustype_ODY_SMMUX_S_INIT(a) CSR_TYPE_NCB32b
5264 #define basename_ODY_SMMUX_S_INIT(a) "SMMUX_S_INIT"
5265 #define device_bar_ODY_SMMUX_S_INIT(a) 0x0 /* PF_BAR0 */
5266 #define busnum_ODY_SMMUX_S_INIT(a) (a)
5267 #define arguments_ODY_SMMUX_S_INIT(a) (a), -1, -1, -1
5268
5269 /**
5270 * Register (NCB32b) smmu#_s_irq_ctrl
5271 *
5272 * SMMU Secure IRQ Control Register
5273 * An update to a field in SMMU()_S_IRQ_CTRL is not considered complete, along with any
5274 * side-effects, until the respective field in SMMU()_S_IRQ_CTRLACK is observed to take
5275 * the new value.
5276 */
5277 union ody_smmux_s_irq_ctrl {
5278 uint32_t u;
5279 struct ody_smmux_s_irq_ctrl_s {
5280 uint32_t gerror_irqen : 1;
5281 uint32_t reserved_1 : 1;
5282 uint32_t eventq_irqen : 1;
5283 uint32_t reserved_3_31 : 29;
5284 } s;
5285 /* struct ody_smmux_s_irq_ctrl_s cn; */
5286 };
5287 typedef union ody_smmux_s_irq_ctrl ody_smmux_s_irq_ctrl_t;
5288
5289 static inline uint64_t ODY_SMMUX_S_IRQ_CTRL(uint64_t a) __attribute__ ((pure, always_inline));
ODY_SMMUX_S_IRQ_CTRL(uint64_t a)5290 static inline uint64_t ODY_SMMUX_S_IRQ_CTRL(uint64_t a)
5291 {
5292 if (a <= 3)
5293 return 0x830000008050ll + 0x1000000000ll * ((a) & 0x3);
5294 __ody_csr_fatal("SMMUX_S_IRQ_CTRL", 1, a, 0, 0, 0, 0, 0);
5295 }
5296
5297 #define typedef_ODY_SMMUX_S_IRQ_CTRL(a) ody_smmux_s_irq_ctrl_t
5298 #define bustype_ODY_SMMUX_S_IRQ_CTRL(a) CSR_TYPE_NCB32b
5299 #define basename_ODY_SMMUX_S_IRQ_CTRL(a) "SMMUX_S_IRQ_CTRL"
5300 #define device_bar_ODY_SMMUX_S_IRQ_CTRL(a) 0x0 /* PF_BAR0 */
5301 #define busnum_ODY_SMMUX_S_IRQ_CTRL(a) (a)
5302 #define arguments_ODY_SMMUX_S_IRQ_CTRL(a) (a), -1, -1, -1
5303
5304 /**
5305 * Register (NCB32b) smmu#_s_irq_ctrlack
5306 *
5307 * SMMU Secure IRQ Control Acknowledgement Register
5308 * This register is a read-only copy of SMMU()_S_IRQ_CTRL.
5309 */
5310 union ody_smmux_s_irq_ctrlack {
5311 uint32_t u;
5312 struct ody_smmux_s_irq_ctrlack_s {
5313 uint32_t gerror_irqen : 1;
5314 uint32_t reserved_1 : 1;
5315 uint32_t eventq_irqen : 1;
5316 uint32_t reserved_3_31 : 29;
5317 } s;
5318 /* struct ody_smmux_s_irq_ctrlack_s cn; */
5319 };
5320 typedef union ody_smmux_s_irq_ctrlack ody_smmux_s_irq_ctrlack_t;
5321
5322 static inline uint64_t ODY_SMMUX_S_IRQ_CTRLACK(uint64_t a) __attribute__ ((pure, always_inline));
ODY_SMMUX_S_IRQ_CTRLACK(uint64_t a)5323 static inline uint64_t ODY_SMMUX_S_IRQ_CTRLACK(uint64_t a)
5324 {
5325 if (a <= 3)
5326 return 0x830000008054ll + 0x1000000000ll * ((a) & 0x3);
5327 __ody_csr_fatal("SMMUX_S_IRQ_CTRLACK", 1, a, 0, 0, 0, 0, 0);
5328 }
5329
5330 #define typedef_ODY_SMMUX_S_IRQ_CTRLACK(a) ody_smmux_s_irq_ctrlack_t
5331 #define bustype_ODY_SMMUX_S_IRQ_CTRLACK(a) CSR_TYPE_NCB32b
5332 #define basename_ODY_SMMUX_S_IRQ_CTRLACK(a) "SMMUX_S_IRQ_CTRLACK"
5333 #define device_bar_ODY_SMMUX_S_IRQ_CTRLACK(a) 0x0 /* PF_BAR0 */
5334 #define busnum_ODY_SMMUX_S_IRQ_CTRLACK(a) (a)
5335 #define arguments_ODY_SMMUX_S_IRQ_CTRLACK(a) (a), -1, -1, -1
5336
5337 /**
5338 * Register (NCB32b) smmu#_s_mpamidr
5339 *
5340 * MPAM capability identification for secure state Register
5341 */
5342 union ody_smmux_s_mpamidr {
5343 uint32_t u;
5344 struct ody_smmux_s_mpamidr_s {
5345 uint32_t partid_max : 16;
5346 uint32_t pmg_max : 8;
5347 uint32_t reserved_24 : 1;
5348 uint32_t has_mpam_ns : 1;
5349 uint32_t reserved_26_31 : 6;
5350 } s;
5351 /* struct ody_smmux_s_mpamidr_s cn; */
5352 };
5353 typedef union ody_smmux_s_mpamidr ody_smmux_s_mpamidr_t;
5354
5355 static inline uint64_t ODY_SMMUX_S_MPAMIDR(uint64_t a) __attribute__ ((pure, always_inline));
ODY_SMMUX_S_MPAMIDR(uint64_t a)5356 static inline uint64_t ODY_SMMUX_S_MPAMIDR(uint64_t a)
5357 {
5358 if (a <= 3)
5359 return 0x830000008130ll + 0x1000000000ll * ((a) & 0x3);
5360 __ody_csr_fatal("SMMUX_S_MPAMIDR", 1, a, 0, 0, 0, 0, 0);
5361 }
5362
5363 #define typedef_ODY_SMMUX_S_MPAMIDR(a) ody_smmux_s_mpamidr_t
5364 #define bustype_ODY_SMMUX_S_MPAMIDR(a) CSR_TYPE_NCB32b
5365 #define basename_ODY_SMMUX_S_MPAMIDR(a) "SMMUX_S_MPAMIDR"
5366 #define device_bar_ODY_SMMUX_S_MPAMIDR(a) 0x0 /* PF_BAR0 */
5367 #define busnum_ODY_SMMUX_S_MPAMIDR(a) (a)
5368 #define arguments_ODY_SMMUX_S_MPAMIDR(a) (a), -1, -1, -1
5369
5370 /**
5371 * Register (NCB) smmu#_s_strtab_base
5372 *
5373 * SMMU Secure STRTAB Base Register
5374 */
5375 union ody_smmux_s_strtab_base {
5376 uint64_t u;
5377 struct ody_smmux_s_strtab_base_s {
5378 uint64_t reserved_0_5 : 6;
5379 uint64_t addr : 46;
5380 uint64_t reserved_52_61 : 10;
5381 uint64_t ra : 1;
5382 uint64_t reserved_63 : 1;
5383 } s;
5384 /* struct ody_smmux_s_strtab_base_s cn; */
5385 };
5386 typedef union ody_smmux_s_strtab_base ody_smmux_s_strtab_base_t;
5387
5388 static inline uint64_t ODY_SMMUX_S_STRTAB_BASE(uint64_t a) __attribute__ ((pure, always_inline));
ODY_SMMUX_S_STRTAB_BASE(uint64_t a)5389 static inline uint64_t ODY_SMMUX_S_STRTAB_BASE(uint64_t a)
5390 {
5391 if (a <= 3)
5392 return 0x830000008080ll + 0x1000000000ll * ((a) & 0x3);
5393 __ody_csr_fatal("SMMUX_S_STRTAB_BASE", 1, a, 0, 0, 0, 0, 0);
5394 }
5395
5396 #define typedef_ODY_SMMUX_S_STRTAB_BASE(a) ody_smmux_s_strtab_base_t
5397 #define bustype_ODY_SMMUX_S_STRTAB_BASE(a) CSR_TYPE_NCB
5398 #define basename_ODY_SMMUX_S_STRTAB_BASE(a) "SMMUX_S_STRTAB_BASE"
5399 #define device_bar_ODY_SMMUX_S_STRTAB_BASE(a) 0x0 /* PF_BAR0 */
5400 #define busnum_ODY_SMMUX_S_STRTAB_BASE(a) (a)
5401 #define arguments_ODY_SMMUX_S_STRTAB_BASE(a) (a), -1, -1, -1
5402
5403 /**
5404 * Register (NCB32b) smmu#_s_strtab_base_cfg
5405 *
5406 * SMMU Secure Command Queue Base Register
5407 * SMMU()_S_STRTAB_BASE_CFG is guarded by the respective SMMU()_S_CR0[SMMUEN] and
5408 * must only be modified when SMMU()_S_CR0[SMMUEN]=0. A write whilst
5409 * SMMU()_S_CR0[SMMUEN]=1 is constrained unpredictable and has one of the following
5410 * behaviors:
5411 *
5412 * * The register takes on any value, which might cause STEs to be fetched from an unpredictable
5413 * address.
5414 *
5415 * * The write is ignored.
5416 *
5417 * A read following such a write will return an unknown value.
5418 *
5419 * Use of any reserved value or unsupported value combination in this register (for
5420 * example, selection of a two-level table when unsupported where
5421 * SMMU()_IDR0[ST_LEVEL]=0x0) causes the stream table to become inaccessible; a
5422 * transaction causing a lookup of an STE is terminated with abort and a SMMU_C_BAD_STREAMID_S
5423 * event recorded.
5424 */
5425 union ody_smmux_s_strtab_base_cfg {
5426 uint32_t u;
5427 struct ody_smmux_s_strtab_base_cfg_s {
5428 uint32_t log2size : 6;
5429 uint32_t split : 5;
5430 uint32_t reserved_11_15 : 5;
5431 uint32_t fmt : 2;
5432 uint32_t reserved_18_31 : 14;
5433 } s;
5434 /* struct ody_smmux_s_strtab_base_cfg_s cn; */
5435 };
5436 typedef union ody_smmux_s_strtab_base_cfg ody_smmux_s_strtab_base_cfg_t;
5437
5438 static inline uint64_t ODY_SMMUX_S_STRTAB_BASE_CFG(uint64_t a) __attribute__ ((pure, always_inline));
ODY_SMMUX_S_STRTAB_BASE_CFG(uint64_t a)5439 static inline uint64_t ODY_SMMUX_S_STRTAB_BASE_CFG(uint64_t a)
5440 {
5441 if (a <= 3)
5442 return 0x830000008088ll + 0x1000000000ll * ((a) & 0x3);
5443 __ody_csr_fatal("SMMUX_S_STRTAB_BASE_CFG", 1, a, 0, 0, 0, 0, 0);
5444 }
5445
5446 #define typedef_ODY_SMMUX_S_STRTAB_BASE_CFG(a) ody_smmux_s_strtab_base_cfg_t
5447 #define bustype_ODY_SMMUX_S_STRTAB_BASE_CFG(a) CSR_TYPE_NCB32b
5448 #define basename_ODY_SMMUX_S_STRTAB_BASE_CFG(a) "SMMUX_S_STRTAB_BASE_CFG"
5449 #define device_bar_ODY_SMMUX_S_STRTAB_BASE_CFG(a) 0x0 /* PF_BAR0 */
5450 #define busnum_ODY_SMMUX_S_STRTAB_BASE_CFG(a) (a)
5451 #define arguments_ODY_SMMUX_S_STRTAB_BASE_CFG(a) (a), -1, -1, -1
5452
5453 /**
5454 * Register (NCB32b) smmu#_statusr
5455 *
5456 * SMMU Status Register
5457 */
5458 union ody_smmux_statusr {
5459 uint32_t u;
5460 struct ody_smmux_statusr_s {
5461 uint32_t dormant : 1;
5462 uint32_t reserved_1_31 : 31;
5463 } s;
5464 /* struct ody_smmux_statusr_s cn; */
5465 };
5466 typedef union ody_smmux_statusr ody_smmux_statusr_t;
5467
5468 static inline uint64_t ODY_SMMUX_STATUSR(uint64_t a) __attribute__ ((pure, always_inline));
ODY_SMMUX_STATUSR(uint64_t a)5469 static inline uint64_t ODY_SMMUX_STATUSR(uint64_t a)
5470 {
5471 if (a <= 3)
5472 return 0x830000000040ll + 0x1000000000ll * ((a) & 0x3);
5473 __ody_csr_fatal("SMMUX_STATUSR", 1, a, 0, 0, 0, 0, 0);
5474 }
5475
5476 #define typedef_ODY_SMMUX_STATUSR(a) ody_smmux_statusr_t
5477 #define bustype_ODY_SMMUX_STATUSR(a) CSR_TYPE_NCB32b
5478 #define basename_ODY_SMMUX_STATUSR(a) "SMMUX_STATUSR"
5479 #define device_bar_ODY_SMMUX_STATUSR(a) 0x0 /* PF_BAR0 */
5480 #define busnum_ODY_SMMUX_STATUSR(a) (a)
5481 #define arguments_ODY_SMMUX_STATUSR(a) (a), -1, -1, -1
5482
5483 /**
5484 * Register (NCB) smmu#_strtab_base
5485 *
5486 * SMMU Stream Table Base Register
5487 */
5488 union ody_smmux_strtab_base {
5489 uint64_t u;
5490 struct ody_smmux_strtab_base_s {
5491 uint64_t reserved_0_5 : 6;
5492 uint64_t addr : 46;
5493 uint64_t reserved_52_61 : 10;
5494 uint64_t ra : 1;
5495 uint64_t reserved_63 : 1;
5496 } s;
5497 /* struct ody_smmux_strtab_base_s cn; */
5498 };
5499 typedef union ody_smmux_strtab_base ody_smmux_strtab_base_t;
5500
5501 static inline uint64_t ODY_SMMUX_STRTAB_BASE(uint64_t a) __attribute__ ((pure, always_inline));
ODY_SMMUX_STRTAB_BASE(uint64_t a)5502 static inline uint64_t ODY_SMMUX_STRTAB_BASE(uint64_t a)
5503 {
5504 if (a <= 3)
5505 return 0x830000000080ll + 0x1000000000ll * ((a) & 0x3);
5506 __ody_csr_fatal("SMMUX_STRTAB_BASE", 1, a, 0, 0, 0, 0, 0);
5507 }
5508
5509 #define typedef_ODY_SMMUX_STRTAB_BASE(a) ody_smmux_strtab_base_t
5510 #define bustype_ODY_SMMUX_STRTAB_BASE(a) CSR_TYPE_NCB
5511 #define basename_ODY_SMMUX_STRTAB_BASE(a) "SMMUX_STRTAB_BASE"
5512 #define device_bar_ODY_SMMUX_STRTAB_BASE(a) 0x0 /* PF_BAR0 */
5513 #define busnum_ODY_SMMUX_STRTAB_BASE(a) (a)
5514 #define arguments_ODY_SMMUX_STRTAB_BASE(a) (a), -1, -1, -1
5515
5516 /**
5517 * Register (NCB32b) smmu#_strtab_base_cfg
5518 *
5519 * SMMU Stream Table Base Configuration Register
5520 * SMMU()_S_STRTAB_BASE_CFG is guarded by the respective SMMU()_S_CR0[SMMUEN] and
5521 * must only be modified when SMMU()_S_CR0[SMMUEN]=0. A write whilst
5522 * SMMU()_S_CR0[SMMUEN]=1 is constrained unpredictable and has one of the following
5523 * behaviors:
5524 *
5525 * * The register takes on any value, which might cause STEs to be fetched from an unpredictable
5526 * address.
5527 *
5528 * * The write is ignored.
5529 *
5530 * A read following such a write will return an unknown value.
5531 *
5532 * Use of any reserved value or unsupported value combination in this register (for
5533 * example, selection of a two-level table when unsupported where
5534 * SMMU()_IDR0[ST_LEVEL]=0x0) causes the stream table to become inaccessible; a
5535 * transaction causing a lookup of an STE is terminated with abort and a SMMU_C_BAD_STREAMID_S
5536 * event recorded.
5537 */
5538 union ody_smmux_strtab_base_cfg {
5539 uint32_t u;
5540 struct ody_smmux_strtab_base_cfg_s {
5541 uint32_t log2size : 6;
5542 uint32_t split : 5;
5543 uint32_t reserved_11_15 : 5;
5544 uint32_t fmt : 2;
5545 uint32_t reserved_18_31 : 14;
5546 } s;
5547 /* struct ody_smmux_strtab_base_cfg_s cn; */
5548 };
5549 typedef union ody_smmux_strtab_base_cfg ody_smmux_strtab_base_cfg_t;
5550
5551 static inline uint64_t ODY_SMMUX_STRTAB_BASE_CFG(uint64_t a) __attribute__ ((pure, always_inline));
ODY_SMMUX_STRTAB_BASE_CFG(uint64_t a)5552 static inline uint64_t ODY_SMMUX_STRTAB_BASE_CFG(uint64_t a)
5553 {
5554 if (a <= 3)
5555 return 0x830000000088ll + 0x1000000000ll * ((a) & 0x3);
5556 __ody_csr_fatal("SMMUX_STRTAB_BASE_CFG", 1, a, 0, 0, 0, 0, 0);
5557 }
5558
5559 #define typedef_ODY_SMMUX_STRTAB_BASE_CFG(a) ody_smmux_strtab_base_cfg_t
5560 #define bustype_ODY_SMMUX_STRTAB_BASE_CFG(a) CSR_TYPE_NCB32b
5561 #define basename_ODY_SMMUX_STRTAB_BASE_CFG(a) "SMMUX_STRTAB_BASE_CFG"
5562 #define device_bar_ODY_SMMUX_STRTAB_BASE_CFG(a) 0x0 /* PF_BAR0 */
5563 #define busnum_ODY_SMMUX_STRTAB_BASE_CFG(a) (a)
5564 #define arguments_ODY_SMMUX_STRTAB_BASE_CFG(a) (a), -1, -1, -1
5565
5566 /**
5567 * Register (NCB32b) smmu#_vatos_sel
5568 *
5569 * SMMU VATOS SEL Register
5570 */
5571 union ody_smmux_vatos_sel {
5572 uint32_t u;
5573 struct ody_smmux_vatos_sel_s {
5574 uint32_t vmid : 16;
5575 uint32_t reserved_16_31 : 16;
5576 } s;
5577 /* struct ody_smmux_vatos_sel_s cn; */
5578 };
5579 typedef union ody_smmux_vatos_sel ody_smmux_vatos_sel_t;
5580
5581 static inline uint64_t ODY_SMMUX_VATOS_SEL(uint64_t a) __attribute__ ((pure, always_inline));
ODY_SMMUX_VATOS_SEL(uint64_t a)5582 static inline uint64_t ODY_SMMUX_VATOS_SEL(uint64_t a)
5583 {
5584 if (a <= 3)
5585 return 0x830000000180ll + 0x1000000000ll * ((a) & 0x3);
5586 __ody_csr_fatal("SMMUX_VATOS_SEL", 1, a, 0, 0, 0, 0, 0);
5587 }
5588
5589 #define typedef_ODY_SMMUX_VATOS_SEL(a) ody_smmux_vatos_sel_t
5590 #define bustype_ODY_SMMUX_VATOS_SEL(a) CSR_TYPE_NCB32b
5591 #define basename_ODY_SMMUX_VATOS_SEL(a) "SMMUX_VATOS_SEL"
5592 #define device_bar_ODY_SMMUX_VATOS_SEL(a) 0x0 /* PF_BAR0 */
5593 #define busnum_ODY_SMMUX_VATOS_SEL(a) (a)
5594 #define arguments_ODY_SMMUX_VATOS_SEL(a) (a), -1, -1, -1
5595
5596 #endif /* __ODY_CSRS_SMMU_H__ */
5597