1 #ifndef __ODY_CSRS_TAD_H__
2 #define __ODY_CSRS_TAD_H__
3 /* This file is auto-generated. Do not edit */
4
5 /***********************license start***********************************
6 * Copyright (C) 2021-2026 Marvell.
7 * SPDX-License-Identifier: BSD-3-Clause
8 * https://spdx.org/licenses
9 ***********************license end**************************************/
10
11
12 /**
13 * @file
14 *
15 * Configuration and status register (CSR) address and type definitions for
16 * TAD.
17 *
18 * This file is auto generated. Do not edit.
19 *
20 */
21
22 /**
23 * Enumeration tad_bar_e
24 *
25 * TAD Base Address Register Enumeration
26 * Enumerates the base address registers.
27 */
28 #define ODY_TAD_BAR_E_TADX_PF_BAR0(a) (0x87e22b000000ll + 0x1000000ll * (a))
29 #define ODY_TAD_BAR_E_TADX_PF_BAR0_SIZE 0x800000ull
30 #define ODY_TAD_BAR_E_TADX_PF_BAR4(a) (0x87e22b800000ll + 0x1000000ll * (a))
31 #define ODY_TAD_BAR_E_TADX_PF_BAR4_SIZE 0x800000ull
32
33 /**
34 * Enumeration tad_pf_int_vec_e
35 *
36 * TAD MSI-X Vector Enumeration
37 * Enumerates the MSI-X interrupt vectors.
38 */
39 #define ODY_TAD_PF_INT_VEC_E_TAD_INT (0)
40
41 /**
42 * Enumeration tad_prf_sel_e
43 *
44 * TAD Performance Counter Select Enumeration
45 * Enumerates the different TAD performance counter selects.
46 */
47 #define ODY_TAD_PRF_SEL_E_ALLOC_ANY (0x1c)
48 #define ODY_TAD_PRF_SEL_E_ALLOC_DTG (0x1a)
49 #define ODY_TAD_PRF_SEL_E_ALLOC_LTG (0x1b)
50 #define ODY_TAD_PRF_SEL_E_DAT_MSH_IN_ANY (9)
51 #define ODY_TAD_PRF_SEL_E_DAT_MSH_IN_DSS (0xa)
52 #define ODY_TAD_PRF_SEL_E_DAT_MSH_OUT_ANY (0x17)
53 #define ODY_TAD_PRF_SEL_E_DAT_MSH_OUT_DSS (0x19)
54 #define ODY_TAD_PRF_SEL_E_DAT_MSH_OUT_FILL (0x18)
55 #define ODY_TAD_PRF_SEL_E_DAT_RD (0x21)
56 #define ODY_TAD_PRF_SEL_E_DAT_RD_BYP (0x22)
57 #define ODY_TAD_PRF_SEL_E_HIT_ANY (0x1f)
58 #define ODY_TAD_PRF_SEL_E_HIT_DTG (0x1d)
59 #define ODY_TAD_PRF_SEL_E_HIT_LTG (0x1e)
60 #define ODY_TAD_PRF_SEL_E_IFB_OCC (0x23)
61 #define ODY_TAD_PRF_SEL_E_NONE (0)
62 #define ODY_TAD_PRF_SEL_E_REQ_MSH_IN_ANY (1)
63 #define ODY_TAD_PRF_SEL_E_REQ_MSH_IN_EXLMN (3)
64 #define ODY_TAD_PRF_SEL_E_REQ_MSH_IN_MN (2)
65 #define ODY_TAD_PRF_SEL_E_REQ_MSH_OUT_ANY (0xb)
66 #define ODY_TAD_PRF_SEL_E_REQ_MSH_OUT_DSS_RD (0xc)
67 #define ODY_TAD_PRF_SEL_E_REQ_MSH_OUT_DSS_WR (0xd)
68 #define ODY_TAD_PRF_SEL_E_REQ_MSH_OUT_DTG_EVICT (0x25)
69 #define ODY_TAD_PRF_SEL_E_REQ_MSH_OUT_EVICT (0xe)
70 #define ODY_TAD_PRF_SEL_E_REQ_MSH_OUT_LTG_EVICT (0x26)
71 #define ODY_TAD_PRF_SEL_E_REQ_OCC (0x24)
72 #define ODY_TAD_PRF_SEL_E_RSP_MSH_IN_ANY (4)
73 #define ODY_TAD_PRF_SEL_E_RSP_MSH_IN_DSS (7)
74 #define ODY_TAD_PRF_SEL_E_RSP_MSH_IN_EXLMN (6)
75 #define ODY_TAD_PRF_SEL_E_RSP_MSH_IN_MN (5)
76 #define ODY_TAD_PRF_SEL_E_RSP_MSH_IN_RETRY_DSS (8)
77 #define ODY_TAD_PRF_SEL_E_RSP_MSH_OUT_ANY (0xf)
78 #define ODY_TAD_PRF_SEL_E_RSP_MSH_OUT_EXLMN (0x12)
79 #define ODY_TAD_PRF_SEL_E_RSP_MSH_OUT_MN (0x13)
80 #define ODY_TAD_PRF_SEL_E_RSP_MSH_OUT_RETRY_EXLMN (0x10)
81 #define ODY_TAD_PRF_SEL_E_RSP_MSH_OUT_RETRY_MN (0x11)
82 #define ODY_TAD_PRF_SEL_E_SNP_MSH_OUT_ANY (0x14)
83 #define ODY_TAD_PRF_SEL_E_SNP_MSH_OUT_EXLMN (0x16)
84 #define ODY_TAD_PRF_SEL_E_SNP_MSH_OUT_MN (0x15)
85 #define ODY_TAD_PRF_SEL_E_TAG_RD (0x20)
86 #define ODY_TAD_PRF_SEL_E_TOT_CYCLE (0xff)
87
88 /**
89 * Register (RSL) tad#_cache_flush_status
90 *
91 * TAD Cache Flush Status Register
92 * Status for Cache Flush operation.
93 */
94 union ody_tadx_cache_flush_status {
95 uint64_t u;
96 struct ody_tadx_cache_flush_status_s {
97 uint64_t done : 1;
98 uint64_t reserved_1_63 : 63;
99 } s;
100 /* struct ody_tadx_cache_flush_status_s cn; */
101 };
102 typedef union ody_tadx_cache_flush_status ody_tadx_cache_flush_status_t;
103
104 static inline uint64_t ODY_TADX_CACHE_FLUSH_STATUS(uint64_t a) __attribute__ ((pure, always_inline));
ODY_TADX_CACHE_FLUSH_STATUS(uint64_t a)105 static inline uint64_t ODY_TADX_CACHE_FLUSH_STATUS(uint64_t a)
106 {
107 if (a <= 89)
108 return 0x87e22b000038ll + 0x1000000ll * ((a) & 0x7f);
109 __ody_csr_fatal("TADX_CACHE_FLUSH_STATUS", 1, a, 0, 0, 0, 0, 0);
110 }
111
112 #define typedef_ODY_TADX_CACHE_FLUSH_STATUS(a) ody_tadx_cache_flush_status_t
113 #define bustype_ODY_TADX_CACHE_FLUSH_STATUS(a) CSR_TYPE_RSL
114 #define basename_ODY_TADX_CACHE_FLUSH_STATUS(a) "TADX_CACHE_FLUSH_STATUS"
115 #define device_bar_ODY_TADX_CACHE_FLUSH_STATUS(a) 0x0 /* PF_BAR0 */
116 #define busnum_ODY_TADX_CACHE_FLUSH_STATUS(a) (a)
117 #define arguments_ODY_TADX_CACHE_FLUSH_STATUS(a) (a), -1, -1, -1
118
119 /**
120 * Register (RSL) tad#_derr_addr
121 *
122 * TAD DAT Error Address Register
123 * This register records error address for Data Error interrupts occurring in data read
124 * from the LLC, FBF, SBF, or mesh input to the MN. The first [DATMBE, FBFMBE, SBFMBE, MNMBE]
125 * error will lock the register until the logged error type is cleared;
126 * [DATSBE, FBFSBE, SBFSBE, MNSBE] errors lock the register until either the logged
127 * error type is cleared or a [DATMBE, FBFMBE, SBFMBE, MNMBE] error is logged.
128 * Only one of [*MBE, *SBE] should be set at a time. In the event the register is
129 * read with all [*MBE] and [*SBE] equal to 0 during interrupt handling that is an
130 * indication that, due to a register set/clear race, information about one or more
131 * errors was lost while processing an earlier error. Note that fields NONSEC, ADDR, OW
132 * don't apply for MNMBE, MNSBE.
133 * [DISCUSSION OF HOW TO SCRUB ERRORS]
134 */
135 union ody_tadx_derr_addr {
136 uint64_t u;
137 struct ody_tadx_derr_addr_s {
138 uint64_t reserved_0_3 : 4;
139 uint64_t ow : 2;
140 uint64_t addr : 42;
141 uint64_t reserved_48_51 : 4;
142 uint64_t nonsec : 1;
143 uint64_t reserved_53_55 : 3;
144 uint64_t mnsbe : 1;
145 uint64_t sbfsbe : 1;
146 uint64_t fbfsbe : 1;
147 uint64_t datsbe : 1;
148 uint64_t mnmbe : 1;
149 uint64_t sbfmbe : 1;
150 uint64_t fbfmbe : 1;
151 uint64_t datmbe : 1;
152 } s;
153 /* struct ody_tadx_derr_addr_s cn; */
154 };
155 typedef union ody_tadx_derr_addr ody_tadx_derr_addr_t;
156
157 static inline uint64_t ODY_TADX_DERR_ADDR(uint64_t a) __attribute__ ((pure, always_inline));
ODY_TADX_DERR_ADDR(uint64_t a)158 static inline uint64_t ODY_TADX_DERR_ADDR(uint64_t a)
159 {
160 if (a <= 89)
161 return 0x87e22b000218ll + 0x1000000ll * ((a) & 0x7f);
162 __ody_csr_fatal("TADX_DERR_ADDR", 1, a, 0, 0, 0, 0, 0);
163 }
164
165 #define typedef_ODY_TADX_DERR_ADDR(a) ody_tadx_derr_addr_t
166 #define bustype_ODY_TADX_DERR_ADDR(a) CSR_TYPE_RSL
167 #define basename_ODY_TADX_DERR_ADDR(a) "TADX_DERR_ADDR"
168 #define device_bar_ODY_TADX_DERR_ADDR(a) 0x0 /* PF_BAR0 */
169 #define busnum_ODY_TADX_DERR_ADDR(a) (a)
170 #define arguments_ODY_TADX_DERR_ADDR(a) (a), -1, -1, -1
171
172 /**
173 * Register (RSL) tad#_int_ena_w1c
174 *
175 * TAD Interrupt Enable Clear Registers
176 * This register clears interrupt enable bits.
177 */
178 union ody_tadx_int_ena_w1c {
179 uint64_t u;
180 struct ody_tadx_int_ena_w1c_s {
181 uint64_t rdnxm : 1;
182 uint64_t wrnxm : 1;
183 uint64_t req_perr : 1;
184 uint64_t rsp_perr : 1;
185 uint64_t dat_perr : 1;
186 uint64_t mn_sbe : 1;
187 uint64_t mn_mbe : 1;
188 uint64_t sbf_sbe : 1;
189 uint64_t sbf_mbe : 1;
190 uint64_t fbf_sbe : 1;
191 uint64_t fbf_mbe : 1;
192 uint64_t dat_nderr : 1;
193 uint64_t reserved_12_63 : 52;
194 } s;
195 /* struct ody_tadx_int_ena_w1c_s cn; */
196 };
197 typedef union ody_tadx_int_ena_w1c ody_tadx_int_ena_w1c_t;
198
199 static inline uint64_t ODY_TADX_INT_ENA_W1C(uint64_t a) __attribute__ ((pure, always_inline));
ODY_TADX_INT_ENA_W1C(uint64_t a)200 static inline uint64_t ODY_TADX_INT_ENA_W1C(uint64_t a)
201 {
202 if (a <= 89)
203 return 0x87e22b008010ll + 0x1000000ll * ((a) & 0x7f);
204 __ody_csr_fatal("TADX_INT_ENA_W1C", 1, a, 0, 0, 0, 0, 0);
205 }
206
207 #define typedef_ODY_TADX_INT_ENA_W1C(a) ody_tadx_int_ena_w1c_t
208 #define bustype_ODY_TADX_INT_ENA_W1C(a) CSR_TYPE_RSL
209 #define basename_ODY_TADX_INT_ENA_W1C(a) "TADX_INT_ENA_W1C"
210 #define device_bar_ODY_TADX_INT_ENA_W1C(a) 0x0 /* PF_BAR0 */
211 #define busnum_ODY_TADX_INT_ENA_W1C(a) (a)
212 #define arguments_ODY_TADX_INT_ENA_W1C(a) (a), -1, -1, -1
213
214 /**
215 * Register (RSL) tad#_int_ena_w1s
216 *
217 * TAD Interrupt Enable Set Registers
218 * This register sets interrupt enable bits.
219 */
220 union ody_tadx_int_ena_w1s {
221 uint64_t u;
222 struct ody_tadx_int_ena_w1s_s {
223 uint64_t rdnxm : 1;
224 uint64_t wrnxm : 1;
225 uint64_t req_perr : 1;
226 uint64_t rsp_perr : 1;
227 uint64_t dat_perr : 1;
228 uint64_t mn_sbe : 1;
229 uint64_t mn_mbe : 1;
230 uint64_t sbf_sbe : 1;
231 uint64_t sbf_mbe : 1;
232 uint64_t fbf_sbe : 1;
233 uint64_t fbf_mbe : 1;
234 uint64_t dat_nderr : 1;
235 uint64_t reserved_12_63 : 52;
236 } s;
237 /* struct ody_tadx_int_ena_w1s_s cn; */
238 };
239 typedef union ody_tadx_int_ena_w1s ody_tadx_int_ena_w1s_t;
240
241 static inline uint64_t ODY_TADX_INT_ENA_W1S(uint64_t a) __attribute__ ((pure, always_inline));
ODY_TADX_INT_ENA_W1S(uint64_t a)242 static inline uint64_t ODY_TADX_INT_ENA_W1S(uint64_t a)
243 {
244 if (a <= 89)
245 return 0x87e22b008018ll + 0x1000000ll * ((a) & 0x7f);
246 __ody_csr_fatal("TADX_INT_ENA_W1S", 1, a, 0, 0, 0, 0, 0);
247 }
248
249 #define typedef_ODY_TADX_INT_ENA_W1S(a) ody_tadx_int_ena_w1s_t
250 #define bustype_ODY_TADX_INT_ENA_W1S(a) CSR_TYPE_RSL
251 #define basename_ODY_TADX_INT_ENA_W1S(a) "TADX_INT_ENA_W1S"
252 #define device_bar_ODY_TADX_INT_ENA_W1S(a) 0x0 /* PF_BAR0 */
253 #define busnum_ODY_TADX_INT_ENA_W1S(a) (a)
254 #define arguments_ODY_TADX_INT_ENA_W1S(a) (a), -1, -1, -1
255
256 /**
257 * Register (RSL) tad#_int_w1c
258 *
259 * TAD Interrupt Register
260 * This register is for TAD-based interrupts.
261 */
262 union ody_tadx_int_w1c {
263 uint64_t u;
264 struct ody_tadx_int_w1c_s {
265 uint64_t rdnxm : 1;
266 uint64_t wrnxm : 1;
267 uint64_t req_perr : 1;
268 uint64_t rsp_perr : 1;
269 uint64_t dat_perr : 1;
270 uint64_t mn_sbe : 1;
271 uint64_t mn_mbe : 1;
272 uint64_t sbf_sbe : 1;
273 uint64_t sbf_mbe : 1;
274 uint64_t fbf_sbe : 1;
275 uint64_t fbf_mbe : 1;
276 uint64_t dat_nderr : 1;
277 uint64_t reserved_12_63 : 52;
278 } s;
279 /* struct ody_tadx_int_w1c_s cn; */
280 };
281 typedef union ody_tadx_int_w1c ody_tadx_int_w1c_t;
282
283 static inline uint64_t ODY_TADX_INT_W1C(uint64_t a) __attribute__ ((pure, always_inline));
ODY_TADX_INT_W1C(uint64_t a)284 static inline uint64_t ODY_TADX_INT_W1C(uint64_t a)
285 {
286 if (a <= 89)
287 return 0x87e22b008000ll + 0x1000000ll * ((a) & 0x7f);
288 __ody_csr_fatal("TADX_INT_W1C", 1, a, 0, 0, 0, 0, 0);
289 }
290
291 #define typedef_ODY_TADX_INT_W1C(a) ody_tadx_int_w1c_t
292 #define bustype_ODY_TADX_INT_W1C(a) CSR_TYPE_RSL
293 #define basename_ODY_TADX_INT_W1C(a) "TADX_INT_W1C"
294 #define device_bar_ODY_TADX_INT_W1C(a) 0x0 /* PF_BAR0 */
295 #define busnum_ODY_TADX_INT_W1C(a) (a)
296 #define arguments_ODY_TADX_INT_W1C(a) (a), -1, -1, -1
297
298 /**
299 * Register (RSL) tad#_int_w1s
300 *
301 * TAD Interrupt Set Registers
302 * This register sets interrupt bits.
303 */
304 union ody_tadx_int_w1s {
305 uint64_t u;
306 struct ody_tadx_int_w1s_s {
307 uint64_t rdnxm : 1;
308 uint64_t wrnxm : 1;
309 uint64_t req_perr : 1;
310 uint64_t rsp_perr : 1;
311 uint64_t dat_perr : 1;
312 uint64_t mn_sbe : 1;
313 uint64_t mn_mbe : 1;
314 uint64_t sbf_sbe : 1;
315 uint64_t sbf_mbe : 1;
316 uint64_t fbf_sbe : 1;
317 uint64_t fbf_mbe : 1;
318 uint64_t dat_nderr : 1;
319 uint64_t reserved_12_63 : 52;
320 } s;
321 /* struct ody_tadx_int_w1s_s cn; */
322 };
323 typedef union ody_tadx_int_w1s ody_tadx_int_w1s_t;
324
325 static inline uint64_t ODY_TADX_INT_W1S(uint64_t a) __attribute__ ((pure, always_inline));
ODY_TADX_INT_W1S(uint64_t a)326 static inline uint64_t ODY_TADX_INT_W1S(uint64_t a)
327 {
328 if (a <= 89)
329 return 0x87e22b008008ll + 0x1000000ll * ((a) & 0x7f);
330 __ody_csr_fatal("TADX_INT_W1S", 1, a, 0, 0, 0, 0, 0);
331 }
332
333 #define typedef_ODY_TADX_INT_W1S(a) ody_tadx_int_w1s_t
334 #define bustype_ODY_TADX_INT_W1S(a) CSR_TYPE_RSL
335 #define basename_ODY_TADX_INT_W1S(a) "TADX_INT_W1S"
336 #define device_bar_ODY_TADX_INT_W1S(a) 0x0 /* PF_BAR0 */
337 #define busnum_ODY_TADX_INT_W1S(a) (a)
338 #define arguments_ODY_TADX_INT_W1S(a) (a), -1, -1, -1
339
340 /**
341 * Register (RSL) tad#_mpam#_rcnt
342 *
343 * TAD Memory Partitioning Resource Count Registers
344 */
345 union ody_tadx_mpamx_rcnt {
346 uint64_t u;
347 struct ody_tadx_mpamx_rcnt_s {
348 uint64_t cnt : 7;
349 uint64_t reserved_7_63 : 57;
350 } s;
351 /* struct ody_tadx_mpamx_rcnt_s cn; */
352 };
353 typedef union ody_tadx_mpamx_rcnt ody_tadx_mpamx_rcnt_t;
354
355 static inline uint64_t ODY_TADX_MPAMX_RCNT(uint64_t a, uint64_t b) __attribute__ ((pure, always_inline));
ODY_TADX_MPAMX_RCNT(uint64_t a,uint64_t b)356 static inline uint64_t ODY_TADX_MPAMX_RCNT(uint64_t a, uint64_t b)
357 {
358 if ((a <= 89) && (b <= 271))
359 return 0x87e22b002000ll + 0x1000000ll * ((a) & 0x7f) + 0x10ll * ((b) & 0x1ff);
360 __ody_csr_fatal("TADX_MPAMX_RCNT", 2, a, b, 0, 0, 0, 0);
361 }
362
363 #define typedef_ODY_TADX_MPAMX_RCNT(a, b) ody_tadx_mpamx_rcnt_t
364 #define bustype_ODY_TADX_MPAMX_RCNT(a, b) CSR_TYPE_RSL
365 #define basename_ODY_TADX_MPAMX_RCNT(a, b) "TADX_MPAMX_RCNT"
366 #define device_bar_ODY_TADX_MPAMX_RCNT(a, b) 0x0 /* PF_BAR0 */
367 #define busnum_ODY_TADX_MPAMX_RCNT(a, b) (a)
368 #define arguments_ODY_TADX_MPAMX_RCNT(a, b) (a), (b), -1, -1
369
370 /**
371 * Register (RSL) tad#_msix_pba#
372 *
373 * TAD MSI-X Pending Bit Array Registers
374 */
375 union ody_tadx_msix_pbax {
376 uint64_t u;
377 struct ody_tadx_msix_pbax_s {
378 uint64_t pend : 64;
379 } s;
380 /* struct ody_tadx_msix_pbax_s cn; */
381 };
382 typedef union ody_tadx_msix_pbax ody_tadx_msix_pbax_t;
383
384 static inline uint64_t ODY_TADX_MSIX_PBAX(uint64_t a, uint64_t b) __attribute__ ((pure, always_inline));
ODY_TADX_MSIX_PBAX(uint64_t a,uint64_t b)385 static inline uint64_t ODY_TADX_MSIX_PBAX(uint64_t a, uint64_t b)
386 {
387 if ((a <= 89) && (b == 0))
388 return 0x87e22b8f0000ll + 0x1000000ll * ((a) & 0x7f);
389 __ody_csr_fatal("TADX_MSIX_PBAX", 2, a, b, 0, 0, 0, 0);
390 }
391
392 #define typedef_ODY_TADX_MSIX_PBAX(a, b) ody_tadx_msix_pbax_t
393 #define bustype_ODY_TADX_MSIX_PBAX(a, b) CSR_TYPE_RSL
394 #define basename_ODY_TADX_MSIX_PBAX(a, b) "TADX_MSIX_PBAX"
395 #define device_bar_ODY_TADX_MSIX_PBAX(a, b) 0x4 /* PF_BAR4 */
396 #define busnum_ODY_TADX_MSIX_PBAX(a, b) (a)
397 #define arguments_ODY_TADX_MSIX_PBAX(a, b) (a), (b), -1, -1
398
399 /**
400 * Register (RSL) tad#_msix_vec#_addr
401 *
402 * TAD MSI-X Vector-Table Address Register
403 * This register is the MSI-X vector table, indexed by the TAD_PF_INT_VEC_E enumeration.
404 */
405 union ody_tadx_msix_vecx_addr {
406 uint64_t u;
407 struct ody_tadx_msix_vecx_addr_s {
408 uint64_t secvec : 1;
409 uint64_t reserved_1 : 1;
410 uint64_t addr : 51;
411 uint64_t reserved_53_63 : 11;
412 } s;
413 /* struct ody_tadx_msix_vecx_addr_s cn; */
414 };
415 typedef union ody_tadx_msix_vecx_addr ody_tadx_msix_vecx_addr_t;
416
417 static inline uint64_t ODY_TADX_MSIX_VECX_ADDR(uint64_t a, uint64_t b) __attribute__ ((pure, always_inline));
ODY_TADX_MSIX_VECX_ADDR(uint64_t a,uint64_t b)418 static inline uint64_t ODY_TADX_MSIX_VECX_ADDR(uint64_t a, uint64_t b)
419 {
420 if ((a <= 89) && (b == 0))
421 return 0x87e22b800000ll + 0x1000000ll * ((a) & 0x7f);
422 __ody_csr_fatal("TADX_MSIX_VECX_ADDR", 2, a, b, 0, 0, 0, 0);
423 }
424
425 #define typedef_ODY_TADX_MSIX_VECX_ADDR(a, b) ody_tadx_msix_vecx_addr_t
426 #define bustype_ODY_TADX_MSIX_VECX_ADDR(a, b) CSR_TYPE_RSL
427 #define basename_ODY_TADX_MSIX_VECX_ADDR(a, b) "TADX_MSIX_VECX_ADDR"
428 #define device_bar_ODY_TADX_MSIX_VECX_ADDR(a, b) 0x4 /* PF_BAR4 */
429 #define busnum_ODY_TADX_MSIX_VECX_ADDR(a, b) (a)
430 #define arguments_ODY_TADX_MSIX_VECX_ADDR(a, b) (a), (b), -1, -1
431
432 /**
433 * Register (RSL) tad#_msix_vec#_ctl
434 *
435 * TAD MSI-X Vector-Table Control and Data Register
436 * This register is the MSI-X vector table, indexed by the TAD_PF_INT_VEC_E enumeration.
437 */
438 union ody_tadx_msix_vecx_ctl {
439 uint64_t u;
440 struct ody_tadx_msix_vecx_ctl_s {
441 uint64_t data : 32;
442 uint64_t mask : 1;
443 uint64_t reserved_33_63 : 31;
444 } s;
445 /* struct ody_tadx_msix_vecx_ctl_s cn; */
446 };
447 typedef union ody_tadx_msix_vecx_ctl ody_tadx_msix_vecx_ctl_t;
448
449 static inline uint64_t ODY_TADX_MSIX_VECX_CTL(uint64_t a, uint64_t b) __attribute__ ((pure, always_inline));
ODY_TADX_MSIX_VECX_CTL(uint64_t a,uint64_t b)450 static inline uint64_t ODY_TADX_MSIX_VECX_CTL(uint64_t a, uint64_t b)
451 {
452 if ((a <= 89) && (b == 0))
453 return 0x87e22b800008ll + 0x1000000ll * ((a) & 0x7f);
454 __ody_csr_fatal("TADX_MSIX_VECX_CTL", 2, a, b, 0, 0, 0, 0);
455 }
456
457 #define typedef_ODY_TADX_MSIX_VECX_CTL(a, b) ody_tadx_msix_vecx_ctl_t
458 #define bustype_ODY_TADX_MSIX_VECX_CTL(a, b) CSR_TYPE_RSL
459 #define basename_ODY_TADX_MSIX_VECX_CTL(a, b) "TADX_MSIX_VECX_CTL"
460 #define device_bar_ODY_TADX_MSIX_VECX_CTL(a, b) 0x4 /* PF_BAR4 */
461 #define busnum_ODY_TADX_MSIX_VECX_CTL(a, b) (a)
462 #define arguments_ODY_TADX_MSIX_VECX_CTL(a, b) (a), (b), -1, -1
463
464 /**
465 * Register (RSL) tad#_msmon_csu_ns
466 *
467 * MPAM Cache Storage Usage Monitor Register
468 * Accesses the CSU monitor selected by TAD_CMN_MSMON_CFG_MON_SEL_NS.
469 * TAD_MSMON_CSU_NS is the Non-secure cache storage usage monitor instance selected by the
470 * Non-secure instance of TAD_CMN_MSMON_CFG_MON_SEL_NS.
471 */
472 union ody_tadx_msmon_csu_ns {
473 uint64_t u;
474 struct ody_tadx_msmon_csu_ns_s {
475 uint64_t value : 31;
476 uint64_t nrdy : 1;
477 uint64_t reserved_32_63 : 32;
478 } s;
479 /* struct ody_tadx_msmon_csu_ns_s cn; */
480 };
481 typedef union ody_tadx_msmon_csu_ns ody_tadx_msmon_csu_ns_t;
482
483 static inline uint64_t ODY_TADX_MSMON_CSU_NS(uint64_t a) __attribute__ ((pure, always_inline));
ODY_TADX_MSMON_CSU_NS(uint64_t a)484 static inline uint64_t ODY_TADX_MSMON_CSU_NS(uint64_t a)
485 {
486 if (a <= 89)
487 return 0x87e22b010840ll + 0x1000000ll * ((a) & 0x7f);
488 __ody_csr_fatal("TADX_MSMON_CSU_NS", 1, a, 0, 0, 0, 0, 0);
489 }
490
491 #define typedef_ODY_TADX_MSMON_CSU_NS(a) ody_tadx_msmon_csu_ns_t
492 #define bustype_ODY_TADX_MSMON_CSU_NS(a) CSR_TYPE_RSL
493 #define basename_ODY_TADX_MSMON_CSU_NS(a) "TADX_MSMON_CSU_NS"
494 #define device_bar_ODY_TADX_MSMON_CSU_NS(a) 0x0 /* PF_BAR0 */
495 #define busnum_ODY_TADX_MSMON_CSU_NS(a) (a)
496 #define arguments_ODY_TADX_MSMON_CSU_NS(a) (a), -1, -1, -1
497
498 /**
499 * Register (RSL) tad#_msmon_csu_s
500 *
501 * MPAM Cache Storage Usage Monitor Register
502 * Accesses the CSU monitor selected by TAD_CMN_MSMON_CFG_MON_SEL_S.
503 * TAD_MSMON_CSU_S is the secure cache storage usage monitor instance selected by the
504 * Non-secure instance of TAD_CMN_MSMON_CFG_MON_SEL_S.
505 */
506 union ody_tadx_msmon_csu_s {
507 uint64_t u;
508 struct ody_tadx_msmon_csu_s_s {
509 uint64_t value : 31;
510 uint64_t nrdy : 1;
511 uint64_t reserved_32_63 : 32;
512 } s;
513 /* struct ody_tadx_msmon_csu_s_s cn; */
514 };
515 typedef union ody_tadx_msmon_csu_s ody_tadx_msmon_csu_s_t;
516
517 static inline uint64_t ODY_TADX_MSMON_CSU_S(uint64_t a) __attribute__ ((pure, always_inline));
ODY_TADX_MSMON_CSU_S(uint64_t a)518 static inline uint64_t ODY_TADX_MSMON_CSU_S(uint64_t a)
519 {
520 if (a <= 89)
521 return 0x87e22b020840ll + 0x1000000ll * ((a) & 0x7f);
522 __ody_csr_fatal("TADX_MSMON_CSU_S", 1, a, 0, 0, 0, 0, 0);
523 }
524
525 #define typedef_ODY_TADX_MSMON_CSU_S(a) ody_tadx_msmon_csu_s_t
526 #define bustype_ODY_TADX_MSMON_CSU_S(a) CSR_TYPE_RSL
527 #define basename_ODY_TADX_MSMON_CSU_S(a) "TADX_MSMON_CSU_S"
528 #define device_bar_ODY_TADX_MSMON_CSU_S(a) 0x0 /* PF_BAR0 */
529 #define busnum_ODY_TADX_MSMON_CSU_S(a) (a)
530 #define arguments_ODY_TADX_MSMON_CSU_S(a) (a), -1, -1, -1
531
532 /**
533 * Register (RSL) tad#_nderr_addr
534 *
535 * TAD Non-Data Error Address Register
536 * This register records the error address for Non-Data Error interrupts triggered from
537 * the REQ mesh [RDNXM, WRNXM, REQ_PERR]. The first [WRNXM, REQ_PERR] error will lock
538 * the register until the logged error type is cleared; [RDNXM] errors lock the
539 * register until either the logged error type is cleared or a [WRNXM, REQ_PERR] error
540 * is logged. See TAD_NDERR_INFO for error opcode and srcid logging.
541 */
542 union ody_tadx_nderr_addr {
543 uint64_t u;
544 struct ody_tadx_nderr_addr_s {
545 uint64_t addr : 48;
546 uint64_t reserved_48_51 : 4;
547 uint64_t nonsec : 1;
548 uint64_t reserved_53_63 : 11;
549 } s;
550 /* struct ody_tadx_nderr_addr_s cn; */
551 };
552 typedef union ody_tadx_nderr_addr ody_tadx_nderr_addr_t;
553
554 static inline uint64_t ODY_TADX_NDERR_ADDR(uint64_t a) __attribute__ ((pure, always_inline));
ODY_TADX_NDERR_ADDR(uint64_t a)555 static inline uint64_t ODY_TADX_NDERR_ADDR(uint64_t a)
556 {
557 if (a <= 89)
558 return 0x87e22b000208ll + 0x1000000ll * ((a) & 0x7f);
559 __ody_csr_fatal("TADX_NDERR_ADDR", 1, a, 0, 0, 0, 0, 0);
560 }
561
562 #define typedef_ODY_TADX_NDERR_ADDR(a) ody_tadx_nderr_addr_t
563 #define bustype_ODY_TADX_NDERR_ADDR(a) CSR_TYPE_RSL
564 #define basename_ODY_TADX_NDERR_ADDR(a) "TADX_NDERR_ADDR"
565 #define device_bar_ODY_TADX_NDERR_ADDR(a) 0x0 /* PF_BAR0 */
566 #define busnum_ODY_TADX_NDERR_ADDR(a) (a)
567 #define arguments_ODY_TADX_NDERR_ADDR(a) (a), -1, -1, -1
568
569 /**
570 * Register (RSL) tad#_nderr_info
571 *
572 * TAD Non-Data Error Info Register
573 * This register records error information for Non-Data Error interrupts [RDNXM, WRNXM,
574 * REQ_PERR, RSP_PERR, DAT_PERR, DAT_NDERR]. The first [WRNXM, REQ_PERR, RSP_PERR,
575 * DAT_PERR, DAT_NDERR] error will lock the register until the logged error type is
576 * cleared; [RDNXM] errors lock the register until either the logged error type is
577 * cleared or a [WRNXM, REQ_PERR, RSP_PERR, DAT_PERR, DAT_NDERR] error is logged.
578 * See TAD_NDERR_ADDR for error address logging.
579 */
580 union ody_tadx_nderr_info {
581 uint64_t u;
582 struct ody_tadx_nderr_info_s {
583 uint64_t srcid : 11;
584 uint64_t opcode : 7;
585 uint64_t rspnum : 1;
586 uint64_t reserved_19_57 : 39;
587 uint64_t dat_nderr : 1;
588 uint64_t dat_perr : 1;
589 uint64_t rsp_perr : 1;
590 uint64_t req_perr : 1;
591 uint64_t wrnxm : 1;
592 uint64_t rdnxm : 1;
593 } s;
594 /* struct ody_tadx_nderr_info_s cn; */
595 };
596 typedef union ody_tadx_nderr_info ody_tadx_nderr_info_t;
597
598 static inline uint64_t ODY_TADX_NDERR_INFO(uint64_t a) __attribute__ ((pure, always_inline));
ODY_TADX_NDERR_INFO(uint64_t a)599 static inline uint64_t ODY_TADX_NDERR_INFO(uint64_t a)
600 {
601 if (a <= 89)
602 return 0x87e22b000200ll + 0x1000000ll * ((a) & 0x7f);
603 __ody_csr_fatal("TADX_NDERR_INFO", 1, a, 0, 0, 0, 0, 0);
604 }
605
606 #define typedef_ODY_TADX_NDERR_INFO(a) ody_tadx_nderr_info_t
607 #define bustype_ODY_TADX_NDERR_INFO(a) CSR_TYPE_RSL
608 #define basename_ODY_TADX_NDERR_INFO(a) "TADX_NDERR_INFO"
609 #define device_bar_ODY_TADX_NDERR_INFO(a) 0x0 /* PF_BAR0 */
610 #define busnum_ODY_TADX_NDERR_INFO(a) (a)
611 #define arguments_ODY_TADX_NDERR_INFO(a) (a), -1, -1, -1
612
613 /**
614 * Register (RSL) tad#_pfc_ns#
615 *
616 * TAD Performance Counter Non-Secure Registers
617 */
618 union ody_tadx_pfc_nsx {
619 uint64_t u;
620 struct ody_tadx_pfc_nsx_s {
621 uint64_t count : 64;
622 } s;
623 /* struct ody_tadx_pfc_nsx_s cn; */
624 };
625 typedef union ody_tadx_pfc_nsx ody_tadx_pfc_nsx_t;
626
627 static inline uint64_t ODY_TADX_PFC_NSX(uint64_t a, uint64_t b) __attribute__ ((pure, always_inline));
ODY_TADX_PFC_NSX(uint64_t a,uint64_t b)628 static inline uint64_t ODY_TADX_PFC_NSX(uint64_t a, uint64_t b)
629 {
630 if ((a <= 89) && (b <= 7))
631 return 0x87e22b030800ll + 0x1000000ll * ((a) & 0x7f) + 8ll * ((b) & 0x7);
632 __ody_csr_fatal("TADX_PFC_NSX", 2, a, b, 0, 0, 0, 0);
633 }
634
635 #define typedef_ODY_TADX_PFC_NSX(a, b) ody_tadx_pfc_nsx_t
636 #define bustype_ODY_TADX_PFC_NSX(a, b) CSR_TYPE_RSL
637 #define basename_ODY_TADX_PFC_NSX(a, b) "TADX_PFC_NSX"
638 #define device_bar_ODY_TADX_PFC_NSX(a, b) 0x0 /* PF_BAR0 */
639 #define busnum_ODY_TADX_PFC_NSX(a, b) (a)
640 #define arguments_ODY_TADX_PFC_NSX(a, b) (a), (b), -1, -1
641
642 /**
643 * Register (RSL) tad#_pfc_s#
644 *
645 * TAD Performance Counter Secure Registers
646 */
647 union ody_tadx_pfc_sx {
648 uint64_t u;
649 struct ody_tadx_pfc_sx_s {
650 uint64_t count : 64;
651 } s;
652 /* struct ody_tadx_pfc_sx_s cn; */
653 };
654 typedef union ody_tadx_pfc_sx ody_tadx_pfc_sx_t;
655
656 static inline uint64_t ODY_TADX_PFC_SX(uint64_t a, uint64_t b) __attribute__ ((pure, always_inline));
ODY_TADX_PFC_SX(uint64_t a,uint64_t b)657 static inline uint64_t ODY_TADX_PFC_SX(uint64_t a, uint64_t b)
658 {
659 if ((a <= 89) && (b <= 7))
660 return 0x87e22b000800ll + 0x1000000ll * ((a) & 0x7f) + 8ll * ((b) & 0x7);
661 __ody_csr_fatal("TADX_PFC_SX", 2, a, b, 0, 0, 0, 0);
662 }
663
664 #define typedef_ODY_TADX_PFC_SX(a, b) ody_tadx_pfc_sx_t
665 #define bustype_ODY_TADX_PFC_SX(a, b) CSR_TYPE_RSL
666 #define basename_ODY_TADX_PFC_SX(a, b) "TADX_PFC_SX"
667 #define device_bar_ODY_TADX_PFC_SX(a, b) 0x0 /* PF_BAR0 */
668 #define busnum_ODY_TADX_PFC_SX(a, b) (a)
669 #define arguments_ODY_TADX_PFC_SX(a, b) (a), (b), -1, -1
670
671 /**
672 * Register (RSL) tad#_prf_ns#
673 *
674 * TAD Performance Counter Control Non-Secure Registers
675 * Selects event to count for each TAD_PFC, and specifies optional
676 * filters for PMG and PARTID.
677 */
678 union ody_tadx_prf_nsx {
679 uint64_t u;
680 struct ody_tadx_prf_nsx_s {
681 uint64_t cntsel : 8;
682 uint64_t match_partid : 1;
683 uint64_t match_pmg : 1;
684 uint64_t partid_val : 9;
685 uint64_t reserved_19_26 : 8;
686 uint64_t pmg_val : 1;
687 uint64_t reserved_28_34 : 7;
688 uint64_t match_stream : 1;
689 uint64_t stream_val : 1;
690 uint64_t match_prefetch : 1;
691 uint64_t prefetch_val : 1;
692 uint64_t match_subsource : 1;
693 uint64_t subsource_val : 2;
694 uint64_t match_opcode : 1;
695 uint64_t opcode_val : 7;
696 uint64_t reserved_50_63 : 14;
697 } s;
698 /* struct ody_tadx_prf_nsx_s cn; */
699 };
700 typedef union ody_tadx_prf_nsx ody_tadx_prf_nsx_t;
701
702 static inline uint64_t ODY_TADX_PRF_NSX(uint64_t a, uint64_t b) __attribute__ ((pure, always_inline));
ODY_TADX_PRF_NSX(uint64_t a,uint64_t b)703 static inline uint64_t ODY_TADX_PRF_NSX(uint64_t a, uint64_t b)
704 {
705 if ((a <= 89) && (b <= 7))
706 return 0x87e22b030900ll + 0x1000000ll * ((a) & 0x7f) + 8ll * ((b) & 0x7);
707 __ody_csr_fatal("TADX_PRF_NSX", 2, a, b, 0, 0, 0, 0);
708 }
709
710 #define typedef_ODY_TADX_PRF_NSX(a, b) ody_tadx_prf_nsx_t
711 #define bustype_ODY_TADX_PRF_NSX(a, b) CSR_TYPE_RSL
712 #define basename_ODY_TADX_PRF_NSX(a, b) "TADX_PRF_NSX"
713 #define device_bar_ODY_TADX_PRF_NSX(a, b) 0x0 /* PF_BAR0 */
714 #define busnum_ODY_TADX_PRF_NSX(a, b) (a)
715 #define arguments_ODY_TADX_PRF_NSX(a, b) (a), (b), -1, -1
716
717 /**
718 * Register (RSL) tad#_prf_s#
719 *
720 * TAD Performance Counter Control Secure Registers
721 * Selects event to count for each TAD_PFC, and specifies optional
722 * filters for PMG and PARTID.
723 */
724 union ody_tadx_prf_sx {
725 uint64_t u;
726 struct ody_tadx_prf_sx_s {
727 uint64_t cntsel : 8;
728 uint64_t match_partid : 1;
729 uint64_t match_pmg : 1;
730 uint64_t partid_val : 9;
731 uint64_t reserved_19_26 : 8;
732 uint64_t pmg_val : 1;
733 uint64_t reserved_28_34 : 7;
734 uint64_t match_stream : 1;
735 uint64_t stream_val : 1;
736 uint64_t match_prefetch : 1;
737 uint64_t prefetch_val : 1;
738 uint64_t match_subsource : 1;
739 uint64_t subsource_val : 2;
740 uint64_t match_opcode : 1;
741 uint64_t opcode_val : 7;
742 uint64_t reserved_50_63 : 14;
743 } s;
744 /* struct ody_tadx_prf_sx_s cn; */
745 };
746 typedef union ody_tadx_prf_sx ody_tadx_prf_sx_t;
747
748 static inline uint64_t ODY_TADX_PRF_SX(uint64_t a, uint64_t b) __attribute__ ((pure, always_inline));
ODY_TADX_PRF_SX(uint64_t a,uint64_t b)749 static inline uint64_t ODY_TADX_PRF_SX(uint64_t a, uint64_t b)
750 {
751 if ((a <= 89) && (b <= 7))
752 return 0x87e22b000900ll + 0x1000000ll * ((a) & 0x7f) + 8ll * ((b) & 0x7);
753 __ody_csr_fatal("TADX_PRF_SX", 2, a, b, 0, 0, 0, 0);
754 }
755
756 #define typedef_ODY_TADX_PRF_SX(a, b) ody_tadx_prf_sx_t
757 #define bustype_ODY_TADX_PRF_SX(a, b) CSR_TYPE_RSL
758 #define basename_ODY_TADX_PRF_SX(a, b) "TADX_PRF_SX"
759 #define device_bar_ODY_TADX_PRF_SX(a, b) 0x0 /* PF_BAR0 */
760 #define busnum_ODY_TADX_PRF_SX(a, b) (a)
761 #define arguments_ODY_TADX_PRF_SX(a, b) (a), (b), -1, -1
762
763 /**
764 * Register (RSL) tad#_req_rcnt
765 *
766 * TAD Request Resource Count Registers
767 */
768 union ody_tadx_req_rcnt {
769 uint64_t u;
770 struct ody_tadx_req_rcnt_s {
771 uint64_t cnt : 7;
772 uint64_t reserved_7_63 : 57;
773 } s;
774 /* struct ody_tadx_req_rcnt_s cn; */
775 };
776 typedef union ody_tadx_req_rcnt ody_tadx_req_rcnt_t;
777
778 static inline uint64_t ODY_TADX_REQ_RCNT(uint64_t a) __attribute__ ((pure, always_inline));
ODY_TADX_REQ_RCNT(uint64_t a)779 static inline uint64_t ODY_TADX_REQ_RCNT(uint64_t a)
780 {
781 if (a <= 89)
782 return 0x87e22b002008ll + 0x1000000ll * ((a) & 0x7f);
783 __ody_csr_fatal("TADX_REQ_RCNT", 1, a, 0, 0, 0, 0, 0);
784 }
785
786 #define typedef_ODY_TADX_REQ_RCNT(a) ody_tadx_req_rcnt_t
787 #define bustype_ODY_TADX_REQ_RCNT(a) CSR_TYPE_RSL
788 #define basename_ODY_TADX_REQ_RCNT(a) "TADX_REQ_RCNT"
789 #define device_bar_ODY_TADX_REQ_RCNT(a) 0x0 /* PF_BAR0 */
790 #define busnum_ODY_TADX_REQ_RCNT(a) (a)
791 #define arguments_ODY_TADX_REQ_RCNT(a) (a), -1, -1, -1
792
793 #endif /* __ODY_CSRS_TAD_H__ */
794