Searched refs:irq_mask (Results 1 – 5 of 5) sorted by relevance
18 #define IRQ_MASK(x) irq_mask[(x) / 32U]21 static uint32_t irq_mask[IMR_NUM] = { 0x0 }; variable171 irq_mask[i] = in imx_set_sys_wakeup()174 irq_mask[i] = 0xFFFFFFFF; in imx_set_sys_wakeup()177 if (~irq_mask[i] & wakeup_irq_mask[i]) { in imx_set_sys_wakeup()189 0, IMR_NUM, irq_mask); in imx_set_sys_wakeup()192 0, IMR_NUM, irq_mask); in imx_set_sys_wakeup()
195 uint32_t irq_mask; in imx_set_sys_wakeup() local209 irq_mask = ~gicd_read_isenabler(gicd_base, 32 * (i + 1)); in imx_set_sys_wakeup()211 irq_mask = IMR_MASK_ALL; in imx_set_sys_wakeup()214 irq_mask); in imx_set_sys_wakeup()
31 uint32_t irq_mask; in imx_enable_irqstr_wakeup() local40 irq_mask = dist_ctx->gicd_isenabler[i]; in imx_enable_irqstr_wakeup()41 mmio_write_32(IMX_WUP_IRQSTR_BASE + 0x3c - 0x4 * i, irq_mask); in imx_enable_irqstr_wakeup()
40 uint32_t irq_mask; in imx_enable_irqstr_wakeup() local49 irq_mask = dist_ctx->gicd_isenabler[i]; in imx_enable_irqstr_wakeup()50 mmio_write_32(IMX_WUP_IRQSTR_BASE + 0x3c - 0x4 * i, irq_mask); in imx_enable_irqstr_wakeup()
181 uint32_t irq_mask; in collect_all_wakeup_events() local196 irq_mask = 0x1 << irq_offset; in collect_all_wakeup_events()206 & irq_mask; in collect_all_wakeup_events()