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Searched refs:idx (Results 1 – 25 of 124) sorted by relevance

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/rk3399_ARM-atf/plat/mediatek/mt8192/drivers/mcdi/
H A Dmt_lp_irqremain.c68 uint32_t idx; in mt_lp_irqremain_init() local
73 idx = remain_irqs.count; in mt_lp_irqremain_init()
74 remain_irqs.irqs[idx] = EDMA0_IRQ_ID; in mt_lp_irqremain_init()
75 remain_irqs.wakeupsrc_cat[idx] = 0; in mt_lp_irqremain_init()
76 remain_irqs.wakeupsrc[idx] = 0; in mt_lp_irqremain_init()
80 idx = remain_irqs.count; in mt_lp_irqremain_init()
81 remain_irqs.irqs[idx] = MDLA_IRQ_ID; in mt_lp_irqremain_init()
82 remain_irqs.wakeupsrc_cat[idx] = 0; in mt_lp_irqremain_init()
83 remain_irqs.wakeupsrc[idx] = 0; in mt_lp_irqremain_init()
87 idx = remain_irqs.count; in mt_lp_irqremain_init()
[all …]
/rk3399_ARM-atf/plat/imx/imx8m/
H A Dimx8m_csu.c19 val = mmio_read_32(CSLx_REG(csu->idx)); in imx_csu_init()
20 if (val & CSLx_LOCK(csu->idx)) { in imx_csu_init()
23 mmio_clrsetbits_32(CSLx_REG(csu->idx), CSLx_CFG(0xff, csu->idx), in imx_csu_init()
24 CSLx_CFG(csu->csl_level | (csu->lock << 8), csu->idx)); in imx_csu_init()
27 val = mmio_read_32(CSU_HP_REG(csu->idx)); in imx_csu_init()
28 if (val & CSU_HP_LOCK(csu->idx)) { in imx_csu_init()
31 mmio_clrsetbits_32(CSU_HP_REG(csu->idx), CSU_HP_CFG(0x1, csu->idx), in imx_csu_init()
32 CSU_HP_CFG(csu->hp | (csu->lock << 0x1), csu->idx)); in imx_csu_init()
35 val = mmio_read_32(CSU_SA_REG(csu->idx)); in imx_csu_init()
36 if (val & CSU_SA_LOCK(csu->idx)) { in imx_csu_init()
[all …]
/rk3399_ARM-atf/plat/mediatek/drivers/spm/version/pmic_wrap/v1/
H A Dmt_spm_pmic_wrap.c19 int idx; in mt_spm_pmic_wrap_set_phase() local
31 for (idx = 0; idx < current_phase->nr_idx; idx++) { in mt_spm_pmic_wrap_set_phase()
32 cmd_addr = current_phase->cmd[idx].cmd_addr; in mt_spm_pmic_wrap_set_phase()
33 cmd_data = current_phase->cmd[idx].cmd_data; in mt_spm_pmic_wrap_set_phase()
35 mmio_write_32(current_phase->cmd[idx].spm_pwrap_addr, in mt_spm_pmic_wrap_set_phase()
42 unsigned int idx, unsigned int cmd_data) in mt_spm_pmic_wrap_set_cmd() argument
53 if (idx >= pmic_wrap->phase[phase].nr_idx) in mt_spm_pmic_wrap_set_cmd()
57 current_phase->cmd[idx].cmd_data = cmd_data; in mt_spm_pmic_wrap_set_cmd()
58 cmd_addr = current_phase->cmd[idx].cmd_addr; in mt_spm_pmic_wrap_set_cmd()
60 mmio_write_32(current_phase->cmd[idx].spm_pwrap_addr, in mt_spm_pmic_wrap_set_cmd()
[all …]
/rk3399_ARM-atf/plat/mediatek/drivers/spm/version/notifier/v4/
H A Dmt_spm_sspm_notifier.c61 unsigned int idx = cur_mbox_index; in __mt_spm_get_available_index() local
65 if (__mt_spm_is_available_index(idx)) { in __mt_spm_get_available_index()
66 cur_mbox_index = (idx + 1) % SSPM_MBOX_SPM_SIZE; in __mt_spm_get_available_index()
67 return idx; in __mt_spm_get_available_index()
69 idx = (idx + 1) % SSPM_MBOX_SPM_SIZE; in __mt_spm_get_available_index()
74 static int __mt_spm_sspm_write_cmd_queue(int idx, int value) in __mt_spm_sspm_write_cmd_queue() argument
78 val = mmio_read_32(MT_SPM_MBOX_OFFSET(idx)); in __mt_spm_sspm_write_cmd_queue()
82 mmio_write_32(MT_SPM_MBOX_OFFSET(idx), val); in __mt_spm_sspm_write_cmd_queue()
89 int idx; in mt_spm_sspm_cmd_enqueue() local
91 idx = __mt_spm_get_available_index(); in mt_spm_sspm_cmd_enqueue()
[all …]
/rk3399_ARM-atf/drivers/arm/dsu/
H A Ddsu.c52 unsigned int idx = 0U; in save_dsu_pmu_state() local
70 for (idx = 0U ; idx < cluster_eventctr_num ; idx++) { in save_dsu_pmu_state()
71 write_clusterpmselr(idx); in save_dsu_pmu_state()
72 cluster_pmu_state->counter_val[idx] = read_clusterpmxevcntr(); in save_dsu_pmu_state()
73 cluster_pmu_state->counter_type[idx] = read_clusterpmxevtyper(); in save_dsu_pmu_state()
105 unsigned int idx = 0U; in restore_dsu_pmu_state() local
110 for (idx = 0U ; idx < cluster_eventctr_num ; idx++) { in restore_dsu_pmu_state()
111 write_clusterpmselr(idx); in restore_dsu_pmu_state()
112 write_clusterpmxevcntr(cluster_pmu_state->counter_val[idx]); in restore_dsu_pmu_state()
113 write_clusterpmxevtyper(cluster_pmu_state->counter_type[idx]); in restore_dsu_pmu_state()
/rk3399_ARM-atf/bl31/
H A Dehf.c34 #define PRI_BIT(idx) (((ehf_pri_bits_t) 1u) << (idx)) argument
40 #define IDX_TO_PRI(idx) \ argument
41 ((((unsigned) idx) << (7u - exception_data.pri_bits)) & 0x7fU)
44 #define IS_IDX_VALID(idx) \ argument
45 ((exception_data.ehf_priorities[idx].ehf_handler & EHF_PRI_VALID_) != 0U)
56 unsigned int idx; in pri_to_idx() local
58 idx = EHF_PRI_TO_IDX(priority, exception_data.pri_bits); in pri_to_idx()
59 assert(idx < exception_data.num_priorities); in pri_to_idx()
60 assert(IS_IDX_VALID(idx)); in pri_to_idx()
62 return idx; in pri_to_idx()
[all …]
/rk3399_ARM-atf/drivers/st/ddr/
H A Dstm32mp_ram.c46 uint32_t idx; in stm32mp_ddr_dt_get_param() local
48 for (idx = 0U; idx < param_size; idx++) { in stm32mp_ddr_dt_get_param()
49 ret = fdt_read_uint32_array(fdt, node, param[idx].name, param[idx].size, in stm32mp_ddr_dt_get_param()
50 (void *)(config + param[idx].offset)); in stm32mp_ddr_dt_get_param()
52 VERBOSE("%s: %s[0x%x] = %d\n", __func__, param[idx].name, param[idx].size, ret); in stm32mp_ddr_dt_get_param()
54 ERROR("%s: Cannot read %s, error=%d\n", __func__, param[idx].name, ret); in stm32mp_ddr_dt_get_param()
/rk3399_ARM-atf/plat/mediatek/drivers/cpu_pm/cpcv5_4/
H A Dmt_lp_irqremain.c40 unsigned int idx; in mt_lp_irqremain_set() local
45 idx = remain_irqs.count; in mt_lp_irqremain_set()
48 remain_irqs.irqs[idx] = info->val; in mt_lp_irqremain_set()
51 remain_irqs.wakeupsrc_cat[idx] = info->val; in mt_lp_irqremain_set()
54 remain_irqs.wakeupsrc[idx] = info->val; in mt_lp_irqremain_set()
60 int mt_lp_irqremain_get(unsigned int idx, unsigned int type, in mt_lp_irqremain_get() argument
63 if (!p_irqs || !info || (idx > remain_irqs.count)) in mt_lp_irqremain_get()
68 info->val = remain_irqs.irqs[idx]; in mt_lp_irqremain_get()
71 info->val = remain_irqs.wakeupsrc_cat[idx]; in mt_lp_irqremain_get()
74 info->val = remain_irqs.wakeupsrc[idx]; in mt_lp_irqremain_get()
/rk3399_ARM-atf/plat/mediatek/drivers/spm/mt8196/constraints/
H A Dmt_spm_rc_api.c33 uint32_t idx; in do_irqs_delivery() local
38 for (idx = 0; idx < irqs->count; idx++) { in do_irqs_delivery()
39 if ((wakeup->tr.comm.raw_sta & irqs->wakeupsrc[idx]) || in do_irqs_delivery()
40 (wakeup->tr.comm.r12 & irqs->wakeupsrc[idx])) { in do_irqs_delivery()
41 if ((irqs->wakeupsrc_cat[idx] & MT_IRQ_REMAIN_CAT_LOG)) in do_irqs_delivery()
42 mt_spm_irq_remain_dump(irqs, idx, wakeup); in do_irqs_delivery()
/rk3399_ARM-atf/plat/marvell/armada/common/
H A Dmarvell_gicv2.c35 #define A7K8K_ODMI_PMU_IRQ(idx) ((2 + idx) << 12) argument
37 #define A7K8K_ODMI_PMU_GIC_IRQ(idx) (130 + idx) argument
79 unsigned int idx = plat_my_core_pos(); in a7k8k_pmu_interrupt_handler() local
98 mmio_write_32(A7K8K_ODMIN_SET_REG, A7K8K_ODMI_PMU_IRQ(idx)); in a7k8k_pmu_interrupt_handler()
107 unsigned int idx; in mvebu_pmu_interrupt_enable() local
117 for (idx = 0; idx < PLATFORM_CORE_COUNT; idx++) in mvebu_pmu_interrupt_enable()
118 gicv2_interrupt_set_cfg(A7K8K_ODMI_PMU_GIC_IRQ(idx), in mvebu_pmu_interrupt_enable()
/rk3399_ARM-atf/lib/psci/
H A Dpsci_suspend.c46 static void psci_suspend_to_pwrdown_start(unsigned int idx, in psci_suspend_to_pwrdown_start() argument
51 PUBLISH_EVENT_ARG(psci_suspend_pwrdown_start, &idx); in psci_suspend_to_pwrdown_start()
116 int psci_cpu_suspend_start(unsigned int idx, in psci_cpu_suspend_start() argument
133 psci_get_parent_pwr_domain_nodes(idx, end_pwrlvl, parent_nodes); in psci_cpu_suspend_start()
157 rc = psci_validate_state_coordination(idx, end_pwrlvl, state_info); in psci_cpu_suspend_start()
168 psci_do_state_coordination(idx, end_pwrlvl, state_info); in psci_cpu_suspend_start()
183 psci_set_target_local_pwr_states(idx, end_pwrlvl, state_info); in psci_cpu_suspend_start()
187 psci_stats_update_pwr_down(idx, end_pwrlvl, state_info); in psci_cpu_suspend_start()
192 psci_suspend_to_pwrdown_start(idx, end_pwrlvl, end_pwrlvl, state_info); in psci_cpu_suspend_start()
197 gic_cpuif_disable(idx); in psci_cpu_suspend_start()
[all …]
H A Dpsci_off.c49 unsigned int idx = plat_my_core_pos(); in psci_do_cpu_off() local
82 psci_get_parent_pwr_domain_nodes(idx, end_pwrlvl, parent_nodes); in psci_do_cpu_off()
108 psci_do_state_coordination(idx, end_pwrlvl, &state_info); in psci_do_cpu_off()
111 psci_set_target_local_pwr_states(idx, end_pwrlvl, &state_info); in psci_do_cpu_off()
115 psci_stats_update_pwr_down(idx, end_pwrlvl, &state_info); in psci_do_cpu_off()
125 gic_cpuif_disable(idx); in psci_do_cpu_off()
127 gic_pcpu_off(idx); in psci_do_cpu_off()
/rk3399_ARM-atf/drivers/arm/rse/
H A Drse_comms.c84 size_t idx; in psa_call() local
106 for (idx = 0; idx < in_len; idx++) { in psa_call()
107 VERBOSE("in_vec[%lu].len=%lu\n", idx, in_vec[idx].len); in psa_call()
108 VERBOSE("in_vec[%lu].buf=%p\n", idx, (void *)in_vec[idx].base); in psa_call()
141 for (idx = 0U; idx < out_len; idx++) { in psa_call()
142 VERBOSE("out_vec[%lu].len=%lu\n", idx, out_vec[idx].len); in psa_call()
143 VERBOSE("out_vec[%lu].buf=%p\n", idx, (void *)out_vec[idx].base); in psa_call()
/rk3399_ARM-atf/lib/gpt_rme/
H A Dgpt_rme.c196 unsigned long idx = GPT_L1_INDEX(ALIGN_2MB(base)); in shatter_2mb() local
202 fill_desc(&gpi_info->gpt_l1_addr[idx], l1_desc, L1_QWORDS_2MB); in shatter_2mb()
208 unsigned long idx = GPT_L1_INDEX(ALIGN_2MB(base)); in shatter_32mb() local
209 const uint64_t *l1_gran = &gpi_info->gpt_l1_addr[idx]; in shatter_32mb()
217 idx = GPT_L1_INDEX(ALIGN_32MB(base)); in shatter_32mb()
218 l1 = &gpi_info->gpt_l1_addr[idx]; in shatter_32mb()
232 unsigned long idx = GPT_L1_INDEX(ALIGN_32MB(base)); in shatter_512mb() local
233 const uint64_t *l1_32mb = &gpi_info->gpt_l1_addr[idx]; in shatter_512mb()
241 idx = GPT_L1_INDEX(ALIGN_512MB(base)); in shatter_512mb()
242 l1 = &gpi_info->gpt_l1_addr[idx]; in shatter_512mb()
[all …]
/rk3399_ARM-atf/plat/mediatek/drivers/spm/mt8189/constraints/
H A Dmt_spm_rc_api.c75 uint32_t idx; in do_irqs_delivery() local
80 for (idx = 0; idx < irqs->count; idx++) { in do_irqs_delivery()
81 if ((wakeup->tr.comm.raw_sta & irqs->wakeupsrc[idx]) || in do_irqs_delivery()
82 (wakeup->tr.comm.r12 & irqs->wakeupsrc[idx])) { in do_irqs_delivery()
83 if ((irqs->wakeupsrc_cat[idx] & MT_IRQ_REMAIN_CAT_LOG)) in do_irqs_delivery()
84 mt_spm_irq_remain_dump(irqs, idx, wakeup); in do_irqs_delivery()
86 mt_irq_set_pending(irqs->irqs[idx]); in do_irqs_delivery()
/rk3399_ARM-atf/include/lib/extensions/
H A Dras_arch.h203 static inline uint64_t ser_get_feature(uintptr_t base, unsigned int idx) in ser_get_feature() argument
205 return mmio_read_64(base + ERR_FR(idx)); in ser_get_feature()
208 static inline uint64_t ser_get_control(uintptr_t base, unsigned int idx) in ser_get_control() argument
210 return mmio_read_64(base + ERR_CTLR(idx)); in ser_get_control()
213 static inline uint64_t ser_get_status(uintptr_t base, unsigned int idx) in ser_get_status() argument
215 return mmio_read_64(base + ERR_STATUS(idx)); in ser_get_status()
229 static inline void ser_set_status(uintptr_t base, unsigned int idx, in ser_set_status() argument
232 mmio_write_64(base + ERR_STATUS(idx), status); in ser_set_status()
235 static inline uint64_t ser_get_addr(uintptr_t base, unsigned int idx) in ser_get_addr() argument
237 return mmio_read_64(base + ERR_ADDR(idx)); in ser_get_addr()
[all …]
/rk3399_ARM-atf/plat/mediatek/mt8192/drivers/spm/
H A Dmt_spm_pmic_wrap.c102 uint32_t idx, addr, data; in mt_spm_pmic_wrap_set_phase() local
119 for (idx = 0U; idx < pw.set[phase].nr_idx; idx++) { in mt_spm_pmic_wrap_set_phase()
120 addr = pw.set[phase]._[idx].cmd_addr << SPM_DATA_SHIFT; in mt_spm_pmic_wrap_set_phase()
121 data = pw.set[phase]._[idx].cmd_wdata; in mt_spm_pmic_wrap_set_phase()
122 mmio_write_32(pw.addr[idx].cmd_addr, addr | data); in mt_spm_pmic_wrap_set_phase()
126 void mt_spm_pmic_wrap_set_cmd(enum pmic_wrap_phase_id phase, uint32_t idx, in mt_spm_pmic_wrap_set_cmd() argument
135 if (idx >= pw.set[phase].nr_idx) { in mt_spm_pmic_wrap_set_cmd()
139 pw.set[phase]._[idx].cmd_wdata = cmd_wdata; in mt_spm_pmic_wrap_set_cmd()
143 addr = pw.set[phase]._[idx].cmd_addr << SPM_DATA_SHIFT; in mt_spm_pmic_wrap_set_cmd()
144 mmio_write_32(pw.addr[idx].cmd_addr, addr | cmd_wdata); in mt_spm_pmic_wrap_set_cmd()
[all …]
/rk3399_ARM-atf/plat/mediatek/drivers/spm/mt8188/
H A Dmt_spm_pmic_wrap.c107 int idx; in mt_spm_pmic_wrap_set_phase() local
120 for (idx = 0; idx < pw.set[phase].nr_idx; idx++) { in mt_spm_pmic_wrap_set_phase()
121 mmio_write_32(pw.addr[idx].cmd_addr, in mt_spm_pmic_wrap_set_phase()
122 (pw.set[phase]._[idx].cmd_addr << SPM_DATA_SHIFT) | in mt_spm_pmic_wrap_set_phase()
123 (pw.set[phase]._[idx].cmd_wdata)); in mt_spm_pmic_wrap_set_phase()
127 void mt_spm_pmic_wrap_set_cmd(enum pmic_wrap_phase_id phase, unsigned int idx, in mt_spm_pmic_wrap_set_cmd() argument
131 if ((phase >= NR_PMIC_WRAP_PHASE) || (idx >= pw.set[phase].nr_idx)) { in mt_spm_pmic_wrap_set_cmd()
135 pw.set[phase]._[idx].cmd_wdata = cmd_wdata; in mt_spm_pmic_wrap_set_cmd()
139 mmio_write_32(pw.addr[idx].cmd_addr, in mt_spm_pmic_wrap_set_cmd()
140 (pw.set[phase]._[idx].cmd_addr << SPM_DATA_SHIFT) | cmd_wdata); in mt_spm_pmic_wrap_set_cmd()
[all …]
/rk3399_ARM-atf/plat/mediatek/mt8186/drivers/spm/
H A Dmt_spm_pmic_wrap.c113 uint32_t idx, addr, data; in mt_spm_pmic_wrap_set_phase() local
125 for (idx = 0; idx < pw->set[phase].nr_idx; idx++) { in mt_spm_pmic_wrap_set_phase()
126 addr = pw->set[phase]._[idx].cmd_addr << SPM_DATA_SHIFT; in mt_spm_pmic_wrap_set_phase()
127 data = pw->set[phase]._[idx].cmd_wdata; in mt_spm_pmic_wrap_set_phase()
128 mmio_write_32(pw->addr[idx].cmd_addr, addr | data); in mt_spm_pmic_wrap_set_phase()
134 void mt_spm_pmic_wrap_set_cmd(enum pmic_wrap_phase_id phase, uint32_t idx, in mt_spm_pmic_wrap_set_cmd() argument
143 if (pw == NULL || idx >= pw->set[phase].nr_idx) { in mt_spm_pmic_wrap_set_cmd()
147 pw->set[phase]._[idx].cmd_wdata = cmd_wdata; in mt_spm_pmic_wrap_set_cmd()
151 addr = pw->set[phase]._[idx].cmd_addr << SPM_DATA_SHIFT; in mt_spm_pmic_wrap_set_cmd()
152 mmio_write_32(pw->addr[idx].cmd_addr, addr | cmd_wdata); in mt_spm_pmic_wrap_set_cmd()
[all …]
/rk3399_ARM-atf/plat/mediatek/mt8195/drivers/spm/
H A Dmt_spm_pmic_wrap.c102 uint32_t idx, addr, data; in mt_spm_pmic_wrap_set_phase() local
119 for (idx = 0U; idx < pw.set[phase].nr_idx; idx++) { in mt_spm_pmic_wrap_set_phase()
120 addr = pw.set[phase]._[idx].cmd_addr << SPM_DATA_SHIFT; in mt_spm_pmic_wrap_set_phase()
121 data = pw.set[phase]._[idx].cmd_wdata; in mt_spm_pmic_wrap_set_phase()
122 mmio_write_32(pw.addr[idx].cmd_addr, addr | data); in mt_spm_pmic_wrap_set_phase()
126 void mt_spm_pmic_wrap_set_cmd(enum pmic_wrap_phase_id phase, uint32_t idx, in mt_spm_pmic_wrap_set_cmd() argument
135 if (idx >= pw.set[phase].nr_idx) { in mt_spm_pmic_wrap_set_cmd()
139 pw.set[phase]._[idx].cmd_wdata = cmd_wdata; in mt_spm_pmic_wrap_set_cmd()
143 addr = pw.set[phase]._[idx].cmd_addr << SPM_DATA_SHIFT; in mt_spm_pmic_wrap_set_cmd()
144 mmio_write_32(pw.addr[idx].cmd_addr, addr | cmd_wdata); in mt_spm_pmic_wrap_set_cmd()
[all …]
/rk3399_ARM-atf/plat/brcm/board/stingray/src/
H A Diommu.c308 uint32_t idx = smmu->cfg[index].cbndx; in arm_smmu_smr_cfg() local
316 ARM_SMMU_GR0_SMR(idx)), reg); in arm_smmu_smr_cfg()
321 uint32_t idx = smmu->cfg[index].cbndx; in arm_smmu_s2cr_cfg() local
329 ARM_SMMU_GR0_S2CR(idx)), reg); in arm_smmu_s2cr_cfg()
404 uint32_t idx; in arm_smmu_create_identity_map() local
441 for (idx = 0; idx < smmu->streams; idx++) { in arm_smmu_create_identity_map()
443 smmu->s2cr[idx].type = S2CR_TYPE_TRANS; in arm_smmu_create_identity_map()
444 smmu->s2cr[idx].privcfg = S2CR_PRIVCFG_DEFAULT; in arm_smmu_create_identity_map()
445 smmu->s2cr[idx].cbndx = context_bank_index; in arm_smmu_create_identity_map()
446 smmu->cfg[idx].cbndx = context_bank_index; in arm_smmu_create_identity_map()
[all …]
/rk3399_ARM-atf/tools/cert_create/src/
H A Dcmd_opt.c43 const char *cmd_opt_get_name(int idx) in cmd_opt_get_name() argument
45 if (idx >= num_reg_opt) { in cmd_opt_get_name()
49 return long_opt[idx].name; in cmd_opt_get_name()
52 const char *cmd_opt_get_help_msg(int idx) in cmd_opt_get_help_msg() argument
54 if (idx >= num_reg_opt) { in cmd_opt_get_help_msg()
58 return help_msg[idx]; in cmd_opt_get_help_msg()
/rk3399_ARM-atf/tools/encrypt_fw/src/
H A Dcmd_opt.c43 const char *cmd_opt_get_name(int idx) in cmd_opt_get_name() argument
45 if (idx >= num_reg_opt) { in cmd_opt_get_name()
49 return long_opt[idx].name; in cmd_opt_get_name()
52 const char *cmd_opt_get_help_msg(int idx) in cmd_opt_get_help_msg() argument
54 if (idx >= num_reg_opt) { in cmd_opt_get_help_msg()
58 return help_msg[idx]; in cmd_opt_get_help_msg()
/rk3399_ARM-atf/plat/mediatek/mt8183/drivers/spm/
H A Dspm_pmic_wrap.c117 uint32_t idx, addr, data; in mt_spm_pmic_wrap_set_phase() local
132 for (idx = 0; idx < pw.set[phase].nr_idx; idx++) { in mt_spm_pmic_wrap_set_phase()
133 addr = pw.set[phase]._[idx].cmd_addr << SPM_DATA_SHIFT; in mt_spm_pmic_wrap_set_phase()
134 data = pw.set[phase]._[idx].cmd_wdata; in mt_spm_pmic_wrap_set_phase()
135 mmio_write_32(pw.addr[idx].cmd_addr, addr | data); in mt_spm_pmic_wrap_set_phase()
139 void mt_spm_pmic_wrap_set_cmd(enum pmic_wrap_phase_id phase, uint32_t idx, in mt_spm_pmic_wrap_set_cmd() argument
147 if (idx >= pw.set[phase].nr_idx) in mt_spm_pmic_wrap_set_cmd()
150 pw.set[phase]._[idx].cmd_wdata = cmd_wdata; in mt_spm_pmic_wrap_set_cmd()
155 addr = pw.set[phase]._[idx].cmd_addr << SPM_DATA_SHIFT; in mt_spm_pmic_wrap_set_cmd()
156 mmio_write_32(pw.addr[idx].cmd_addr, addr | cmd_wdata); in mt_spm_pmic_wrap_set_cmd()
[all …]
/rk3399_ARM-atf/drivers/st/rif/
H A Dstm32mp2_risaf.c164 int idx; in risaf_conf_protreg() local
166 for (idx = 0; idx < RISAF_MAX_INSTANCE; idx++) { in risaf_conf_protreg()
169 if (pdata->base[idx] == 0) { in risaf_conf_protreg()
173 if (clk_enable(pdata->clock[idx]) != 0) { in risaf_conf_protreg()
174 ERROR("%s: RISAF@%lx clock failed\n", __func__, pdata->base[idx]); in risaf_conf_protreg()
186 if (pdata->region[n].instance != idx) { in risaf_conf_protreg()
192 assert(valid_protreg_id(idx, id)); in risaf_conf_protreg()
211 if (risaf_configure_region(idx, id, cfg, cid_cfg, in risaf_conf_protreg()
214 __func__, id, pdata->base[idx]); in risaf_conf_protreg()
219 clk_disable(pdata->clock[idx]); in risaf_conf_protreg()
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