Searched refs:cmd_addr (Results 1 – 7 of 7) sorted by relevance
| /rk3399_ARM-atf/plat/mediatek/drivers/spm/version/pmic_wrap/v1/ |
| H A D | mt_spm_pmic_wrap.c | 20 uint32_t cmd_addr, cmd_data; in mt_spm_pmic_wrap_set_phase() local
32 cmd_addr = current_phase->cmd[idx].cmd_addr; in mt_spm_pmic_wrap_set_phase()
36 (cmd_addr << SPM_DATA_SHIFT) | cmd_data); in mt_spm_pmic_wrap_set_phase()
44 uint32_t cmd_addr; in mt_spm_pmic_wrap_set_cmd() local
58 cmd_addr = current_phase->cmd[idx].cmd_addr; in mt_spm_pmic_wrap_set_cmd()
61 (cmd_addr << SPM_DATA_SHIFT) | cmd_data); in mt_spm_pmic_wrap_set_cmd()
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| /rk3399_ARM-atf/plat/mediatek/mt8186/drivers/spm/ |
| H A D | mt_spm_pmic_wrap.c | 23 unsigned long cmd_addr; member
32 unsigned long cmd_addr; member
40 unsigned long cmd_addr; member
116 if (pw == NULL || pw->addr[0].cmd_addr == 0) { in mt_spm_pmic_wrap_set_phase()
126 addr = pw->set[phase]._[idx].cmd_addr << SPM_DATA_SHIFT; in mt_spm_pmic_wrap_set_phase()
128 mmio_write_32(pw->addr[idx].cmd_addr, addr | data); in mt_spm_pmic_wrap_set_phase()
151 addr = pw->set[phase]._[idx].cmd_addr << SPM_DATA_SHIFT; in mt_spm_pmic_wrap_set_cmd()
152 mmio_write_32(pw->addr[idx].cmd_addr, addr | cmd_wdata); in mt_spm_pmic_wrap_set_cmd()
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| /rk3399_ARM-atf/plat/mediatek/mt8192/drivers/spm/ |
| H A D | mt_spm_pmic_wrap.c | 36 unsigned long cmd_addr; member
45 unsigned long cmd_addr; member
112 if (pw.addr[0].cmd_addr == 0UL) { in mt_spm_pmic_wrap_set_phase()
120 addr = pw.set[phase]._[idx].cmd_addr << SPM_DATA_SHIFT; in mt_spm_pmic_wrap_set_phase()
122 mmio_write_32(pw.addr[idx].cmd_addr, addr | data); in mt_spm_pmic_wrap_set_phase()
143 addr = pw.set[phase]._[idx].cmd_addr << SPM_DATA_SHIFT; in mt_spm_pmic_wrap_set_cmd()
144 mmio_write_32(pw.addr[idx].cmd_addr, addr | cmd_wdata); in mt_spm_pmic_wrap_set_cmd()
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| /rk3399_ARM-atf/plat/mediatek/drivers/spm/mt8188/ |
| H A D | mt_spm_pmic_wrap.c | 41 uint32_t cmd_addr; member
50 uint32_t cmd_addr; member
113 if (pw.addr[0].cmd_addr == 0) { in mt_spm_pmic_wrap_set_phase()
121 mmio_write_32(pw.addr[idx].cmd_addr, in mt_spm_pmic_wrap_set_phase()
122 (pw.set[phase]._[idx].cmd_addr << SPM_DATA_SHIFT) | in mt_spm_pmic_wrap_set_phase()
139 mmio_write_32(pw.addr[idx].cmd_addr, in mt_spm_pmic_wrap_set_cmd()
140 (pw.set[phase]._[idx].cmd_addr << SPM_DATA_SHIFT) | cmd_wdata); in mt_spm_pmic_wrap_set_cmd()
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| /rk3399_ARM-atf/plat/mediatek/mt8195/drivers/spm/ |
| H A D | mt_spm_pmic_wrap.c | 36 unsigned long cmd_addr; member
45 unsigned long cmd_addr; member
112 if (pw.addr[0].cmd_addr == 0UL) { in mt_spm_pmic_wrap_set_phase()
120 addr = pw.set[phase]._[idx].cmd_addr << SPM_DATA_SHIFT; in mt_spm_pmic_wrap_set_phase()
122 mmio_write_32(pw.addr[idx].cmd_addr, addr | data); in mt_spm_pmic_wrap_set_phase()
143 addr = pw.set[phase]._[idx].cmd_addr << SPM_DATA_SHIFT; in mt_spm_pmic_wrap_set_cmd()
144 mmio_write_32(pw.addr[idx].cmd_addr, addr | cmd_wdata); in mt_spm_pmic_wrap_set_cmd()
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| /rk3399_ARM-atf/plat/mediatek/mt8183/drivers/spm/ |
| H A D | spm_pmic_wrap.c | 39 unsigned long cmd_addr; member
48 unsigned long cmd_addr; member
125 if (pw.addr[0].cmd_addr == 0) in mt_spm_pmic_wrap_set_phase()
133 addr = pw.set[phase]._[idx].cmd_addr << SPM_DATA_SHIFT; in mt_spm_pmic_wrap_set_phase()
135 mmio_write_32(pw.addr[idx].cmd_addr, addr | data); in mt_spm_pmic_wrap_set_phase()
155 addr = pw.set[phase]._[idx].cmd_addr << SPM_DATA_SHIFT; in mt_spm_pmic_wrap_set_cmd()
156 mmio_write_32(pw.addr[idx].cmd_addr, addr | cmd_wdata); in mt_spm_pmic_wrap_set_cmd()
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| /rk3399_ARM-atf/plat/mediatek/drivers/spm/version/pmic_wrap/inc/ |
| H A D | mt_spm_pmic_wrap.h | 12 uint32_t cmd_addr; member
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