Searched refs:bw_ratio (Results 1 – 3 of 3) sorted by relevance
| /rk3399_ARM-atf/plat/intel/soc/agilex5/soc/ |
| H A D | agilex5_memory_controller.c | 178 burst_len_sched_clk, act_to_act, rd_to_wr, wr_to_rd, bw_ratio, in configure_ddr_sched_ctrl_regs() local
232 bw_ratio = ((HMC_ADP_DDRIOCTRL_IO_SIZE(data) == 0) ? 0 : 1); in configure_ddr_sched_ctrl_regs()
264 bw_ratio << DDRTIMING_BWRATIO_OFST | in configure_ddr_sched_ctrl_regs()
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| /rk3399_ARM-atf/plat/intel/soc/agilex/soc/ |
| H A D | agilex_memory_controller.c | 177 burst_len_sched_clk, act_to_act, rd_to_wr, wr_to_rd, bw_ratio, in configure_ddr_sched_ctrl_regs() local
231 bw_ratio = ((HMC_ADP_DDRIOCTRL_IO_SIZE(data) == 0) ? 0 : 1); in configure_ddr_sched_ctrl_regs()
263 bw_ratio << DDRTIMING_BWRATIO_OFST | in configure_ddr_sched_ctrl_regs()
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| /rk3399_ARM-atf/plat/intel/soc/stratix10/soc/ |
| H A D | s10_memory_controller.c | 206 burst_len_sched_clk, act_to_act, rd_to_wr, wr_to_rd, bw_ratio, in configure_ddr_sched_ctrl_regs() local
260 bw_ratio = ((HMC_ADP_DDRIOCTRL_IO_SIZE(data) == 0) ? 0 : 1); in configure_ddr_sched_ctrl_regs()
292 bw_ratio << DDRTIMING_BWRATIO_OFST | in configure_ddr_sched_ctrl_regs()
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