1 #ifndef __ODY_CSRS_PCCBR_H__
2 #define __ODY_CSRS_PCCBR_H__
3 /* This file is auto-generated. Do not edit */
4
5 /***********************license start***********************************
6 * Copyright (C) 2021-2026 Marvell.
7 * SPDX-License-Identifier: BSD-3-Clause
8 * https://spdx.org/licenses
9 ***********************license end**************************************/
10
11
12 /**
13 * @file
14 *
15 * Configuration and status register (CSR) address and type definitions for
16 * PCCBR.
17 *
18 * This file is auto generated. Do not edit.
19 *
20 */
21
22 /**
23 * Register (PCCBR) pccbr_xxx_acs_cap_ctl
24 *
25 * PCC PF ACS Capability and Control Register
26 * This register is the header of the eight-byte PCI access control services
27 * capability structure.
28 *
29 * This register is reset on a chip domain reset.
30 */
31 union ody_pccbr_xxx_acs_cap_ctl {
32 uint32_t u;
33 struct ody_pccbr_xxx_acs_cap_ctl_s {
34 uint32_t sv : 1;
35 uint32_t tb : 1;
36 uint32_t rr : 1;
37 uint32_t cr : 1;
38 uint32_t uf : 1;
39 uint32_t ec : 1;
40 uint32_t dt : 1;
41 uint32_t reserved_7 : 1;
42 uint32_t ecvs : 8;
43 uint32_t sve : 1;
44 uint32_t tbe : 1;
45 uint32_t rre : 1;
46 uint32_t cre : 1;
47 uint32_t ufe : 1;
48 uint32_t ece : 1;
49 uint32_t dte : 1;
50 uint32_t reserved_23_31 : 9;
51 } s;
52 /* struct ody_pccbr_xxx_acs_cap_ctl_s cn; */
53 };
54 typedef union ody_pccbr_xxx_acs_cap_ctl ody_pccbr_xxx_acs_cap_ctl_t;
55
56 #define ODY_PCCBR_XXX_ACS_CAP_CTL ODY_PCCBR_XXX_ACS_CAP_CTL_FUNC()
57 static inline uint64_t ODY_PCCBR_XXX_ACS_CAP_CTL_FUNC(void) __attribute__ ((pure, always_inline));
ODY_PCCBR_XXX_ACS_CAP_CTL_FUNC(void)58 static inline uint64_t ODY_PCCBR_XXX_ACS_CAP_CTL_FUNC(void)
59 {
60 return 0x144;
61 }
62
63 #define typedef_ODY_PCCBR_XXX_ACS_CAP_CTL ody_pccbr_xxx_acs_cap_ctl_t
64 #define bustype_ODY_PCCBR_XXX_ACS_CAP_CTL CSR_TYPE_PCCBR
65 #define basename_ODY_PCCBR_XXX_ACS_CAP_CTL "PCCBR_XXX_ACS_CAP_CTL"
66 #define busnum_ODY_PCCBR_XXX_ACS_CAP_CTL 0
67 #define arguments_ODY_PCCBR_XXX_ACS_CAP_CTL -1, -1, -1, -1
68
69 /**
70 * Register (PCCBR) pccbr_xxx_acs_cap_hdr
71 *
72 * PCC PF ACS Capability Header Register
73 * This register is the header of the eight-byte PCI ACS capability structure.
74 */
75 union ody_pccbr_xxx_acs_cap_hdr {
76 uint32_t u;
77 struct ody_pccbr_xxx_acs_cap_hdr_s {
78 uint32_t acsid : 16;
79 uint32_t cv : 4;
80 uint32_t nco : 12;
81 } s;
82 /* struct ody_pccbr_xxx_acs_cap_hdr_s cn; */
83 };
84 typedef union ody_pccbr_xxx_acs_cap_hdr ody_pccbr_xxx_acs_cap_hdr_t;
85
86 #define ODY_PCCBR_XXX_ACS_CAP_HDR ODY_PCCBR_XXX_ACS_CAP_HDR_FUNC()
87 static inline uint64_t ODY_PCCBR_XXX_ACS_CAP_HDR_FUNC(void) __attribute__ ((pure, always_inline));
ODY_PCCBR_XXX_ACS_CAP_HDR_FUNC(void)88 static inline uint64_t ODY_PCCBR_XXX_ACS_CAP_HDR_FUNC(void)
89 {
90 return 0x140;
91 }
92
93 #define typedef_ODY_PCCBR_XXX_ACS_CAP_HDR ody_pccbr_xxx_acs_cap_hdr_t
94 #define bustype_ODY_PCCBR_XXX_ACS_CAP_HDR CSR_TYPE_PCCBR
95 #define basename_ODY_PCCBR_XXX_ACS_CAP_HDR "PCCBR_XXX_ACS_CAP_HDR"
96 #define busnum_ODY_PCCBR_XXX_ACS_CAP_HDR 0
97 #define arguments_ODY_PCCBR_XXX_ACS_CAP_HDR -1, -1, -1, -1
98
99 /**
100 * Register (PCCBR) pccbr_xxx_bus
101 *
102 * PCC Bridge Bus Register
103 * This register is reset on a chip domain reset.
104 */
105 union ody_pccbr_xxx_bus {
106 uint32_t u;
107 struct ody_pccbr_xxx_bus_s {
108 uint32_t pbnum : 8;
109 uint32_t sbnum : 8;
110 uint32_t subbnum : 8;
111 uint32_t slt : 8;
112 } s;
113 /* struct ody_pccbr_xxx_bus_s cn; */
114 };
115 typedef union ody_pccbr_xxx_bus ody_pccbr_xxx_bus_t;
116
117 #define ODY_PCCBR_XXX_BUS ODY_PCCBR_XXX_BUS_FUNC()
118 static inline uint64_t ODY_PCCBR_XXX_BUS_FUNC(void) __attribute__ ((pure, always_inline));
ODY_PCCBR_XXX_BUS_FUNC(void)119 static inline uint64_t ODY_PCCBR_XXX_BUS_FUNC(void)
120 {
121 return 0x18;
122 }
123
124 #define typedef_ODY_PCCBR_XXX_BUS ody_pccbr_xxx_bus_t
125 #define bustype_ODY_PCCBR_XXX_BUS CSR_TYPE_PCCBR
126 #define basename_ODY_PCCBR_XXX_BUS "PCCBR_XXX_BUS"
127 #define busnum_ODY_PCCBR_XXX_BUS 0
128 #define arguments_ODY_PCCBR_XXX_BUS -1, -1, -1, -1
129
130 /**
131 * Register (PCCBR) pccbr_xxx_cap_ptr
132 *
133 * PCC Bridge Capability Pointer Register
134 */
135 union ody_pccbr_xxx_cap_ptr {
136 uint32_t u;
137 struct ody_pccbr_xxx_cap_ptr_s {
138 uint32_t cp : 8;
139 uint32_t reserved_8_31 : 24;
140 } s;
141 /* struct ody_pccbr_xxx_cap_ptr_s cn; */
142 };
143 typedef union ody_pccbr_xxx_cap_ptr ody_pccbr_xxx_cap_ptr_t;
144
145 #define ODY_PCCBR_XXX_CAP_PTR ODY_PCCBR_XXX_CAP_PTR_FUNC()
146 static inline uint64_t ODY_PCCBR_XXX_CAP_PTR_FUNC(void) __attribute__ ((pure, always_inline));
ODY_PCCBR_XXX_CAP_PTR_FUNC(void)147 static inline uint64_t ODY_PCCBR_XXX_CAP_PTR_FUNC(void)
148 {
149 return 0x34;
150 }
151
152 #define typedef_ODY_PCCBR_XXX_CAP_PTR ody_pccbr_xxx_cap_ptr_t
153 #define bustype_ODY_PCCBR_XXX_CAP_PTR CSR_TYPE_PCCBR
154 #define basename_ODY_PCCBR_XXX_CAP_PTR "PCCBR_XXX_CAP_PTR"
155 #define busnum_ODY_PCCBR_XXX_CAP_PTR 0
156 #define arguments_ODY_PCCBR_XXX_CAP_PTR -1, -1, -1, -1
157
158 /**
159 * Register (PCCBR) pccbr_xxx_clsize
160 *
161 * PCC Bridge Cache Line Size Register
162 */
163 union ody_pccbr_xxx_clsize {
164 uint32_t u;
165 struct ody_pccbr_xxx_clsize_s {
166 uint32_t cls : 8;
167 uint32_t lt : 8;
168 uint32_t chf : 7;
169 uint32_t mfd : 1;
170 uint32_t bist : 8;
171 } s;
172 /* struct ody_pccbr_xxx_clsize_s cn; */
173 };
174 typedef union ody_pccbr_xxx_clsize ody_pccbr_xxx_clsize_t;
175
176 #define ODY_PCCBR_XXX_CLSIZE ODY_PCCBR_XXX_CLSIZE_FUNC()
177 static inline uint64_t ODY_PCCBR_XXX_CLSIZE_FUNC(void) __attribute__ ((pure, always_inline));
ODY_PCCBR_XXX_CLSIZE_FUNC(void)178 static inline uint64_t ODY_PCCBR_XXX_CLSIZE_FUNC(void)
179 {
180 return 0xc;
181 }
182
183 #define typedef_ODY_PCCBR_XXX_CLSIZE ody_pccbr_xxx_clsize_t
184 #define bustype_ODY_PCCBR_XXX_CLSIZE CSR_TYPE_PCCBR
185 #define basename_ODY_PCCBR_XXX_CLSIZE "PCCBR_XXX_CLSIZE"
186 #define busnum_ODY_PCCBR_XXX_CLSIZE 0
187 #define arguments_ODY_PCCBR_XXX_CLSIZE -1, -1, -1, -1
188
189 /**
190 * Register (PCCBR) pccbr_xxx_cmd
191 *
192 * PCC Bridge Command/Status Register
193 */
194 union ody_pccbr_xxx_cmd {
195 uint32_t u;
196 struct ody_pccbr_xxx_cmd_s {
197 uint32_t reserved_0 : 1;
198 uint32_t msae : 1;
199 uint32_t me : 1;
200 uint32_t reserved_3_19 : 17;
201 uint32_t cl : 1;
202 uint32_t reserved_21_31 : 11;
203 } s;
204 /* struct ody_pccbr_xxx_cmd_s cn; */
205 };
206 typedef union ody_pccbr_xxx_cmd ody_pccbr_xxx_cmd_t;
207
208 #define ODY_PCCBR_XXX_CMD ODY_PCCBR_XXX_CMD_FUNC()
209 static inline uint64_t ODY_PCCBR_XXX_CMD_FUNC(void) __attribute__ ((pure, always_inline));
ODY_PCCBR_XXX_CMD_FUNC(void)210 static inline uint64_t ODY_PCCBR_XXX_CMD_FUNC(void)
211 {
212 return 4;
213 }
214
215 #define typedef_ODY_PCCBR_XXX_CMD ody_pccbr_xxx_cmd_t
216 #define bustype_ODY_PCCBR_XXX_CMD CSR_TYPE_PCCBR
217 #define basename_ODY_PCCBR_XXX_CMD "PCCBR_XXX_CMD"
218 #define busnum_ODY_PCCBR_XXX_CMD 0
219 #define arguments_ODY_PCCBR_XXX_CMD -1, -1, -1, -1
220
221 /**
222 * Register (PCCBR) pccbr_xxx_e_cap2
223 *
224 * PCC Bridge PCI Express Capabilities 2 Register
225 */
226 union ody_pccbr_xxx_e_cap2 {
227 uint32_t u;
228 struct ody_pccbr_xxx_e_cap2_s {
229 uint32_t reserved_0_4 : 5;
230 uint32_t arifwd : 1;
231 uint32_t atomfwd : 1;
232 uint32_t reserved_7_31 : 25;
233 } s;
234 /* struct ody_pccbr_xxx_e_cap2_s cn; */
235 };
236 typedef union ody_pccbr_xxx_e_cap2 ody_pccbr_xxx_e_cap2_t;
237
238 #define ODY_PCCBR_XXX_E_CAP2 ODY_PCCBR_XXX_E_CAP2_FUNC()
239 static inline uint64_t ODY_PCCBR_XXX_E_CAP2_FUNC(void) __attribute__ ((pure, always_inline));
ODY_PCCBR_XXX_E_CAP2_FUNC(void)240 static inline uint64_t ODY_PCCBR_XXX_E_CAP2_FUNC(void)
241 {
242 return 0x94;
243 }
244
245 #define typedef_ODY_PCCBR_XXX_E_CAP2 ody_pccbr_xxx_e_cap2_t
246 #define bustype_ODY_PCCBR_XXX_E_CAP2 CSR_TYPE_PCCBR
247 #define basename_ODY_PCCBR_XXX_E_CAP2 "PCCBR_XXX_E_CAP2"
248 #define busnum_ODY_PCCBR_XXX_E_CAP2 0
249 #define arguments_ODY_PCCBR_XXX_E_CAP2 -1, -1, -1, -1
250
251 /**
252 * Register (PCCBR) pccbr_xxx_e_cap_hdr
253 *
254 * PCC Bridge PCI Express Capabilities Register
255 * This register is the header of the 64-byte PCIe capability header.
256 */
257 union ody_pccbr_xxx_e_cap_hdr {
258 uint32_t u;
259 struct ody_pccbr_xxx_e_cap_hdr_s {
260 uint32_t pcieid : 8;
261 uint32_t ncp : 8;
262 uint32_t pciecv : 4;
263 uint32_t porttype : 4;
264 uint32_t reserved_24_31 : 8;
265 } s;
266 /* struct ody_pccbr_xxx_e_cap_hdr_s cn; */
267 };
268 typedef union ody_pccbr_xxx_e_cap_hdr ody_pccbr_xxx_e_cap_hdr_t;
269
270 #define ODY_PCCBR_XXX_E_CAP_HDR ODY_PCCBR_XXX_E_CAP_HDR_FUNC()
271 static inline uint64_t ODY_PCCBR_XXX_E_CAP_HDR_FUNC(void) __attribute__ ((pure, always_inline));
ODY_PCCBR_XXX_E_CAP_HDR_FUNC(void)272 static inline uint64_t ODY_PCCBR_XXX_E_CAP_HDR_FUNC(void)
273 {
274 return 0x70;
275 }
276
277 #define typedef_ODY_PCCBR_XXX_E_CAP_HDR ody_pccbr_xxx_e_cap_hdr_t
278 #define bustype_ODY_PCCBR_XXX_E_CAP_HDR CSR_TYPE_PCCBR
279 #define basename_ODY_PCCBR_XXX_E_CAP_HDR "PCCBR_XXX_E_CAP_HDR"
280 #define busnum_ODY_PCCBR_XXX_E_CAP_HDR 0
281 #define arguments_ODY_PCCBR_XXX_E_CAP_HDR -1, -1, -1, -1
282
283 /**
284 * Register (PCCBR) pccbr_xxx_e_dev_cap
285 *
286 * PCC Bridge PCI Express Device Capabilities Register
287 */
288 union ody_pccbr_xxx_e_dev_cap {
289 uint32_t u;
290 struct ody_pccbr_xxx_e_dev_cap_s {
291 uint32_t reserved_0_14 : 15;
292 uint32_t rber : 1;
293 uint32_t reserved_16_31 : 16;
294 } s;
295 /* struct ody_pccbr_xxx_e_dev_cap_s cn; */
296 };
297 typedef union ody_pccbr_xxx_e_dev_cap ody_pccbr_xxx_e_dev_cap_t;
298
299 #define ODY_PCCBR_XXX_E_DEV_CAP ODY_PCCBR_XXX_E_DEV_CAP_FUNC()
300 static inline uint64_t ODY_PCCBR_XXX_E_DEV_CAP_FUNC(void) __attribute__ ((pure, always_inline));
ODY_PCCBR_XXX_E_DEV_CAP_FUNC(void)301 static inline uint64_t ODY_PCCBR_XXX_E_DEV_CAP_FUNC(void)
302 {
303 return 0x74;
304 }
305
306 #define typedef_ODY_PCCBR_XXX_E_DEV_CAP ody_pccbr_xxx_e_dev_cap_t
307 #define bustype_ODY_PCCBR_XXX_E_DEV_CAP CSR_TYPE_PCCBR
308 #define basename_ODY_PCCBR_XXX_E_DEV_CAP "PCCBR_XXX_E_DEV_CAP"
309 #define busnum_ODY_PCCBR_XXX_E_DEV_CAP 0
310 #define arguments_ODY_PCCBR_XXX_E_DEV_CAP -1, -1, -1, -1
311
312 /**
313 * Register (PCCBR) pccbr_xxx_ea_br
314 *
315 * PCC Bridge PCI Enhanced Allocation Bridge Register
316 */
317 union ody_pccbr_xxx_ea_br {
318 uint32_t u;
319 struct ody_pccbr_xxx_ea_br_s {
320 uint32_t fixed_sbnum : 8;
321 uint32_t fixed_subbnum : 8;
322 uint32_t reserved_16_31 : 16;
323 } s;
324 /* struct ody_pccbr_xxx_ea_br_s cn; */
325 };
326 typedef union ody_pccbr_xxx_ea_br ody_pccbr_xxx_ea_br_t;
327
328 #define ODY_PCCBR_XXX_EA_BR ODY_PCCBR_XXX_EA_BR_FUNC()
329 static inline uint64_t ODY_PCCBR_XXX_EA_BR_FUNC(void) __attribute__ ((pure, always_inline));
ODY_PCCBR_XXX_EA_BR_FUNC(void)330 static inline uint64_t ODY_PCCBR_XXX_EA_BR_FUNC(void)
331 {
332 return 0xb4;
333 }
334
335 #define typedef_ODY_PCCBR_XXX_EA_BR ody_pccbr_xxx_ea_br_t
336 #define bustype_ODY_PCCBR_XXX_EA_BR CSR_TYPE_PCCBR
337 #define basename_ODY_PCCBR_XXX_EA_BR "PCCBR_XXX_EA_BR"
338 #define busnum_ODY_PCCBR_XXX_EA_BR 0
339 #define arguments_ODY_PCCBR_XXX_EA_BR -1, -1, -1, -1
340
341 /**
342 * Register (PCCBR) pccbr_xxx_ea_cap_hdr
343 *
344 * PCC Bridge PCI Enhanced Allocation Capabilities Register
345 * This register is the header of the 8-byte PCI enhanced allocation capability
346 * structure for type 1 bridges.
347 */
348 union ody_pccbr_xxx_ea_cap_hdr {
349 uint32_t u;
350 struct ody_pccbr_xxx_ea_cap_hdr_s {
351 uint32_t pcieid : 8;
352 uint32_t ncp : 8;
353 uint32_t num_entries : 6;
354 uint32_t reserved_22_31 : 10;
355 } s;
356 /* struct ody_pccbr_xxx_ea_cap_hdr_s cn; */
357 };
358 typedef union ody_pccbr_xxx_ea_cap_hdr ody_pccbr_xxx_ea_cap_hdr_t;
359
360 #define ODY_PCCBR_XXX_EA_CAP_HDR ODY_PCCBR_XXX_EA_CAP_HDR_FUNC()
361 static inline uint64_t ODY_PCCBR_XXX_EA_CAP_HDR_FUNC(void) __attribute__ ((pure, always_inline));
ODY_PCCBR_XXX_EA_CAP_HDR_FUNC(void)362 static inline uint64_t ODY_PCCBR_XXX_EA_CAP_HDR_FUNC(void)
363 {
364 return 0xb0;
365 }
366
367 #define typedef_ODY_PCCBR_XXX_EA_CAP_HDR ody_pccbr_xxx_ea_cap_hdr_t
368 #define bustype_ODY_PCCBR_XXX_EA_CAP_HDR CSR_TYPE_PCCBR
369 #define basename_ODY_PCCBR_XXX_EA_CAP_HDR "PCCBR_XXX_EA_CAP_HDR"
370 #define busnum_ODY_PCCBR_XXX_EA_CAP_HDR 0
371 #define arguments_ODY_PCCBR_XXX_EA_CAP_HDR -1, -1, -1, -1
372
373 /**
374 * Register (PCCBR) pccbr_xxx_id
375 *
376 * PCC Bridge Vendor and Device ID Register
377 * This register is the header of the 64-byte PCI type 1 configuration structure.
378 */
379 union ody_pccbr_xxx_id {
380 uint32_t u;
381 struct ody_pccbr_xxx_id_s {
382 uint32_t vendid : 16;
383 uint32_t devid : 16;
384 } s;
385 /* struct ody_pccbr_xxx_id_s cn; */
386 };
387 typedef union ody_pccbr_xxx_id ody_pccbr_xxx_id_t;
388
389 #define ODY_PCCBR_XXX_ID ODY_PCCBR_XXX_ID_FUNC()
390 static inline uint64_t ODY_PCCBR_XXX_ID_FUNC(void) __attribute__ ((pure, always_inline));
ODY_PCCBR_XXX_ID_FUNC(void)391 static inline uint64_t ODY_PCCBR_XXX_ID_FUNC(void)
392 {
393 return 0;
394 }
395
396 #define typedef_ODY_PCCBR_XXX_ID ody_pccbr_xxx_id_t
397 #define bustype_ODY_PCCBR_XXX_ID CSR_TYPE_PCCBR
398 #define basename_ODY_PCCBR_XXX_ID "PCCBR_XXX_ID"
399 #define busnum_ODY_PCCBR_XXX_ID 0
400 #define arguments_ODY_PCCBR_XXX_ID -1, -1, -1, -1
401
402 /**
403 * Register (PCCBR) pccbr_xxx_rev
404 *
405 * PCC Bridge Class Code/Revision ID Register
406 */
407 union ody_pccbr_xxx_rev {
408 uint32_t u;
409 struct ody_pccbr_xxx_rev_s {
410 uint32_t rid : 8;
411 uint32_t pi : 8;
412 uint32_t sc : 8;
413 uint32_t bcc : 8;
414 } s;
415 /* struct ody_pccbr_xxx_rev_s cn; */
416 };
417 typedef union ody_pccbr_xxx_rev ody_pccbr_xxx_rev_t;
418
419 #define ODY_PCCBR_XXX_REV ODY_PCCBR_XXX_REV_FUNC()
420 static inline uint64_t ODY_PCCBR_XXX_REV_FUNC(void) __attribute__ ((pure, always_inline));
ODY_PCCBR_XXX_REV_FUNC(void)421 static inline uint64_t ODY_PCCBR_XXX_REV_FUNC(void)
422 {
423 return 8;
424 }
425
426 #define typedef_ODY_PCCBR_XXX_REV ody_pccbr_xxx_rev_t
427 #define bustype_ODY_PCCBR_XXX_REV CSR_TYPE_PCCBR
428 #define basename_ODY_PCCBR_XXX_REV "PCCBR_XXX_REV"
429 #define busnum_ODY_PCCBR_XXX_REV 0
430 #define arguments_ODY_PCCBR_XXX_REV -1, -1, -1, -1
431
432 /**
433 * Register (PCCBR) pccbr_xxx_vsec_cap_hdr
434 *
435 * PCC Bridge Vendor-Specific Capability Header Register
436 * This register is the header of the 16-byte {ProductLine} family bridge capability
437 * structure.
438 */
439 union ody_pccbr_xxx_vsec_cap_hdr {
440 uint32_t u;
441 struct ody_pccbr_xxx_vsec_cap_hdr_s {
442 uint32_t rbareid : 16;
443 uint32_t cv : 4;
444 uint32_t nco : 12;
445 } s;
446 /* struct ody_pccbr_xxx_vsec_cap_hdr_s cn; */
447 };
448 typedef union ody_pccbr_xxx_vsec_cap_hdr ody_pccbr_xxx_vsec_cap_hdr_t;
449
450 #define ODY_PCCBR_XXX_VSEC_CAP_HDR ODY_PCCBR_XXX_VSEC_CAP_HDR_FUNC()
451 static inline uint64_t ODY_PCCBR_XXX_VSEC_CAP_HDR_FUNC(void) __attribute__ ((pure, always_inline));
ODY_PCCBR_XXX_VSEC_CAP_HDR_FUNC(void)452 static inline uint64_t ODY_PCCBR_XXX_VSEC_CAP_HDR_FUNC(void)
453 {
454 return 0x100;
455 }
456
457 #define typedef_ODY_PCCBR_XXX_VSEC_CAP_HDR ody_pccbr_xxx_vsec_cap_hdr_t
458 #define bustype_ODY_PCCBR_XXX_VSEC_CAP_HDR CSR_TYPE_PCCBR
459 #define basename_ODY_PCCBR_XXX_VSEC_CAP_HDR "PCCBR_XXX_VSEC_CAP_HDR"
460 #define busnum_ODY_PCCBR_XXX_VSEC_CAP_HDR 0
461 #define arguments_ODY_PCCBR_XXX_VSEC_CAP_HDR -1, -1, -1, -1
462
463 /**
464 * Register (PCCBR) pccbr_xxx_vsec_ctl
465 *
466 * PCC Bridge Vendor-Specific Control Register
467 */
468 union ody_pccbr_xxx_vsec_ctl {
469 uint32_t u;
470 struct ody_pccbr_xxx_vsec_ctl_s {
471 uint32_t inst_num : 8;
472 uint32_t static_subbnum : 8;
473 uint32_t reserved_16_31 : 16;
474 } s;
475 /* struct ody_pccbr_xxx_vsec_ctl_s cn; */
476 };
477 typedef union ody_pccbr_xxx_vsec_ctl ody_pccbr_xxx_vsec_ctl_t;
478
479 #define ODY_PCCBR_XXX_VSEC_CTL ODY_PCCBR_XXX_VSEC_CTL_FUNC()
480 static inline uint64_t ODY_PCCBR_XXX_VSEC_CTL_FUNC(void) __attribute__ ((pure, always_inline));
ODY_PCCBR_XXX_VSEC_CTL_FUNC(void)481 static inline uint64_t ODY_PCCBR_XXX_VSEC_CTL_FUNC(void)
482 {
483 return 0x108;
484 }
485
486 #define typedef_ODY_PCCBR_XXX_VSEC_CTL ody_pccbr_xxx_vsec_ctl_t
487 #define bustype_ODY_PCCBR_XXX_VSEC_CTL CSR_TYPE_PCCBR
488 #define basename_ODY_PCCBR_XXX_VSEC_CTL "PCCBR_XXX_VSEC_CTL"
489 #define busnum_ODY_PCCBR_XXX_VSEC_CTL 0
490 #define arguments_ODY_PCCBR_XXX_VSEC_CTL -1, -1, -1, -1
491
492 /**
493 * Register (PCCBR) pccbr_xxx_vsec_id
494 *
495 * PCC Bridge Vendor-Specific Identification Register
496 */
497 union ody_pccbr_xxx_vsec_id {
498 uint32_t u;
499 struct ody_pccbr_xxx_vsec_id_s {
500 uint32_t id : 16;
501 uint32_t rev : 4;
502 uint32_t len : 12;
503 } s;
504 /* struct ody_pccbr_xxx_vsec_id_s cn; */
505 };
506 typedef union ody_pccbr_xxx_vsec_id ody_pccbr_xxx_vsec_id_t;
507
508 #define ODY_PCCBR_XXX_VSEC_ID ODY_PCCBR_XXX_VSEC_ID_FUNC()
509 static inline uint64_t ODY_PCCBR_XXX_VSEC_ID_FUNC(void) __attribute__ ((pure, always_inline));
ODY_PCCBR_XXX_VSEC_ID_FUNC(void)510 static inline uint64_t ODY_PCCBR_XXX_VSEC_ID_FUNC(void)
511 {
512 return 0x104;
513 }
514
515 #define typedef_ODY_PCCBR_XXX_VSEC_ID ody_pccbr_xxx_vsec_id_t
516 #define bustype_ODY_PCCBR_XXX_VSEC_ID CSR_TYPE_PCCBR
517 #define basename_ODY_PCCBR_XXX_VSEC_ID "PCCBR_XXX_VSEC_ID"
518 #define busnum_ODY_PCCBR_XXX_VSEC_ID 0
519 #define arguments_ODY_PCCBR_XXX_VSEC_ID -1, -1, -1, -1
520
521 /**
522 * Register (PCCBR) pccbr_xxx_vsec_sctl
523 *
524 * PCC Bridge Vendor-Specific Secure Control Register
525 * This register is reset on a chip domain reset.
526 */
527 union ody_pccbr_xxx_vsec_sctl {
528 uint32_t u;
529 struct ody_pccbr_xxx_vsec_sctl_s {
530 uint32_t reserved_0_15 : 16;
531 uint32_t rid : 8;
532 uint32_t pi : 8;
533 } s;
534 /* struct ody_pccbr_xxx_vsec_sctl_s cn; */
535 };
536 typedef union ody_pccbr_xxx_vsec_sctl ody_pccbr_xxx_vsec_sctl_t;
537
538 #define ODY_PCCBR_XXX_VSEC_SCTL ODY_PCCBR_XXX_VSEC_SCTL_FUNC()
539 static inline uint64_t ODY_PCCBR_XXX_VSEC_SCTL_FUNC(void) __attribute__ ((pure, always_inline));
ODY_PCCBR_XXX_VSEC_SCTL_FUNC(void)540 static inline uint64_t ODY_PCCBR_XXX_VSEC_SCTL_FUNC(void)
541 {
542 return 0x10c;
543 }
544
545 #define typedef_ODY_PCCBR_XXX_VSEC_SCTL ody_pccbr_xxx_vsec_sctl_t
546 #define bustype_ODY_PCCBR_XXX_VSEC_SCTL CSR_TYPE_PCCBR
547 #define basename_ODY_PCCBR_XXX_VSEC_SCTL "PCCBR_XXX_VSEC_SCTL"
548 #define busnum_ODY_PCCBR_XXX_VSEC_SCTL 0
549 #define arguments_ODY_PCCBR_XXX_VSEC_SCTL -1, -1, -1, -1
550
551 #endif /* __ODY_CSRS_PCCBR_H__ */
552