1 #ifndef __ODY_CSRS_MRML_H__
2 #define __ODY_CSRS_MRML_H__
3 /* This file is auto-generated. Do not edit */
4
5 /***********************license start***********************************
6 * Copyright (C) 2021-2026 Marvell.
7 * SPDX-License-Identifier: BSD-3-Clause
8 * https://spdx.org/licenses
9 ***********************license end**************************************/
10
11
12 /**
13 * @file
14 *
15 * Configuration and status register (CSR) address and type definitions for
16 * MRML.
17 *
18 * This file is auto generated. Do not edit.
19 *
20 */
21
22 /**
23 * Enumeration mrml_bar_e
24 *
25 * MRML Base Address Register Enumeration
26 * Enumerates the base address registers.
27 */
28 #define ODY_MRML_BAR_E_MRML_PF_BAR0 (0x87e0fc000000ll)
29 #define ODY_MRML_BAR_E_MRML_PF_BAR0_SIZE 0x40000ull
30 #define ODY_MRML_BAR_E_MRML_PF_BAR4 (0x87e0fcf00000ll)
31 #define ODY_MRML_BAR_E_MRML_PF_BAR4_SIZE 0x100000ull
32
33 /**
34 * Enumeration mrml_int_vec_e
35 *
36 * MRML MSI-X Vector Enumeration
37 * Enumerates the MSI-X interrupt vectors.
38 */
39 #define ODY_MRML_INT_VEC_E_INTS (0)
40
41 /**
42 * Register (RSL) mrml_active_pc
43 *
44 * MRML Conditional Clock Counter Register
45 * This register counts conditional clocks for power management.
46 * This register is reset on chip reset.
47 */
48 union ody_mrml_active_pc {
49 uint64_t u;
50 struct ody_mrml_active_pc_s {
51 uint64_t count : 64;
52 } s;
53 /* struct ody_mrml_active_pc_s cn; */
54 };
55 typedef union ody_mrml_active_pc ody_mrml_active_pc_t;
56
57 #define ODY_MRML_ACTIVE_PC ODY_MRML_ACTIVE_PC_FUNC()
58 static inline uint64_t ODY_MRML_ACTIVE_PC_FUNC(void) __attribute__ ((pure, always_inline));
ODY_MRML_ACTIVE_PC_FUNC(void)59 static inline uint64_t ODY_MRML_ACTIVE_PC_FUNC(void)
60 {
61 return 0x87e0fc000010ll;
62 }
63
64 #define typedef_ODY_MRML_ACTIVE_PC ody_mrml_active_pc_t
65 #define bustype_ODY_MRML_ACTIVE_PC CSR_TYPE_RSL
66 #define basename_ODY_MRML_ACTIVE_PC "MRML_ACTIVE_PC"
67 #define device_bar_ODY_MRML_ACTIVE_PC 0x0 /* PF_BAR0 */
68 #define busnum_ODY_MRML_ACTIVE_PC 0
69 #define arguments_ODY_MRML_ACTIVE_PC -1, -1, -1, -1
70
71 /**
72 * Register (RSL) mrml_cmd_to
73 *
74 * MRML Command Timeout Register
75 */
76 union ody_mrml_cmd_to {
77 uint64_t u;
78 struct ody_mrml_cmd_to_s {
79 uint64_t tovalue : 32;
80 uint64_t reserved_32_62 : 31;
81 uint64_t ack_dis : 1;
82 } s;
83 /* struct ody_mrml_cmd_to_s cn; */
84 };
85 typedef union ody_mrml_cmd_to ody_mrml_cmd_to_t;
86
87 #define ODY_MRML_CMD_TO ODY_MRML_CMD_TO_FUNC()
88 static inline uint64_t ODY_MRML_CMD_TO_FUNC(void) __attribute__ ((pure, always_inline));
ODY_MRML_CMD_TO_FUNC(void)89 static inline uint64_t ODY_MRML_CMD_TO_FUNC(void)
90 {
91 return 0x87e0fc000008ll;
92 }
93
94 #define typedef_ODY_MRML_CMD_TO ody_mrml_cmd_to_t
95 #define bustype_ODY_MRML_CMD_TO CSR_TYPE_RSL
96 #define basename_ODY_MRML_CMD_TO "MRML_CMD_TO"
97 #define device_bar_ODY_MRML_CMD_TO 0x0 /* PF_BAR0 */
98 #define busnum_ODY_MRML_CMD_TO 0
99 #define arguments_ODY_MRML_CMD_TO -1, -1, -1, -1
100
101 /**
102 * Register (RSL) mrml_config
103 *
104 * MRML Configuration Register
105 */
106 union ody_mrml_config {
107 uint64_t u;
108 struct ody_mrml_config_s {
109 uint64_t force_clk_en : 1;
110 uint64_t force_gibm_clk : 1;
111 uint64_t reserved_2_63 : 62;
112 } s;
113 /* struct ody_mrml_config_s cn; */
114 };
115 typedef union ody_mrml_config ody_mrml_config_t;
116
117 #define ODY_MRML_CONFIG ODY_MRML_CONFIG_FUNC()
118 static inline uint64_t ODY_MRML_CONFIG_FUNC(void) __attribute__ ((pure, always_inline));
ODY_MRML_CONFIG_FUNC(void)119 static inline uint64_t ODY_MRML_CONFIG_FUNC(void)
120 {
121 return 0x87e0fc002000ll;
122 }
123
124 #define typedef_ODY_MRML_CONFIG ody_mrml_config_t
125 #define bustype_ODY_MRML_CONFIG CSR_TYPE_RSL
126 #define basename_ODY_MRML_CONFIG "MRML_CONFIG"
127 #define device_bar_ODY_MRML_CONFIG 0x0 /* PF_BAR0 */
128 #define busnum_ODY_MRML_CONFIG 0
129 #define arguments_ODY_MRML_CONFIG -1, -1, -1, -1
130
131 /**
132 * Register (RSL) mrml_int_ena_w1c
133 *
134 * MRML Interrupt Enable Clear Register
135 * This register clears interrupt enable bits.
136 */
137 union ody_mrml_int_ena_w1c {
138 uint64_t u;
139 struct ody_mrml_int_ena_w1c_s {
140 uint64_t ocx_toe : 1;
141 uint64_t local_toe : 1;
142 uint64_t gibm : 1;
143 uint64_t reserved_3_63 : 61;
144 } s;
145 /* struct ody_mrml_int_ena_w1c_s cn; */
146 };
147 typedef union ody_mrml_int_ena_w1c ody_mrml_int_ena_w1c_t;
148
149 #define ODY_MRML_INT_ENA_W1C ODY_MRML_INT_ENA_W1C_FUNC()
150 static inline uint64_t ODY_MRML_INT_ENA_W1C_FUNC(void) __attribute__ ((pure, always_inline));
ODY_MRML_INT_ENA_W1C_FUNC(void)151 static inline uint64_t ODY_MRML_INT_ENA_W1C_FUNC(void)
152 {
153 return 0x87e0fc000880ll;
154 }
155
156 #define typedef_ODY_MRML_INT_ENA_W1C ody_mrml_int_ena_w1c_t
157 #define bustype_ODY_MRML_INT_ENA_W1C CSR_TYPE_RSL
158 #define basename_ODY_MRML_INT_ENA_W1C "MRML_INT_ENA_W1C"
159 #define device_bar_ODY_MRML_INT_ENA_W1C 0x0 /* PF_BAR0 */
160 #define busnum_ODY_MRML_INT_ENA_W1C 0
161 #define arguments_ODY_MRML_INT_ENA_W1C -1, -1, -1, -1
162
163 /**
164 * Register (RSL) mrml_int_ena_w1s
165 *
166 * MRML Interrupt Enable Set Register
167 * This register sets interrupt enable bits.
168 */
169 union ody_mrml_int_ena_w1s {
170 uint64_t u;
171 struct ody_mrml_int_ena_w1s_s {
172 uint64_t ocx_toe : 1;
173 uint64_t local_toe : 1;
174 uint64_t gibm : 1;
175 uint64_t reserved_3_63 : 61;
176 } s;
177 /* struct ody_mrml_int_ena_w1s_s cn; */
178 };
179 typedef union ody_mrml_int_ena_w1s ody_mrml_int_ena_w1s_t;
180
181 #define ODY_MRML_INT_ENA_W1S ODY_MRML_INT_ENA_W1S_FUNC()
182 static inline uint64_t ODY_MRML_INT_ENA_W1S_FUNC(void) __attribute__ ((pure, always_inline));
ODY_MRML_INT_ENA_W1S_FUNC(void)183 static inline uint64_t ODY_MRML_INT_ENA_W1S_FUNC(void)
184 {
185 return 0x87e0fc001000ll;
186 }
187
188 #define typedef_ODY_MRML_INT_ENA_W1S ody_mrml_int_ena_w1s_t
189 #define bustype_ODY_MRML_INT_ENA_W1S CSR_TYPE_RSL
190 #define basename_ODY_MRML_INT_ENA_W1S "MRML_INT_ENA_W1S"
191 #define device_bar_ODY_MRML_INT_ENA_W1S 0x0 /* PF_BAR0 */
192 #define busnum_ODY_MRML_INT_ENA_W1S 0
193 #define arguments_ODY_MRML_INT_ENA_W1S -1, -1, -1, -1
194
195 /**
196 * Register (RSL) mrml_int_local_to
197 *
198 * MRML Local Node Timeout Register
199 * Configures local node timeouts.
200 */
201 union ody_mrml_int_local_to {
202 uint64_t u;
203 struct ody_mrml_int_local_to_s {
204 uint64_t tovalue : 32;
205 uint64_t reserved_32_63 : 32;
206 } s;
207 /* struct ody_mrml_int_local_to_s cn; */
208 };
209 typedef union ody_mrml_int_local_to ody_mrml_int_local_to_t;
210
211 #define ODY_MRML_INT_LOCAL_TO ODY_MRML_INT_LOCAL_TO_FUNC()
212 static inline uint64_t ODY_MRML_INT_LOCAL_TO_FUNC(void) __attribute__ ((pure, always_inline));
ODY_MRML_INT_LOCAL_TO_FUNC(void)213 static inline uint64_t ODY_MRML_INT_LOCAL_TO_FUNC(void)
214 {
215 return 0x87e0fc000800ll;
216 }
217
218 #define typedef_ODY_MRML_INT_LOCAL_TO ody_mrml_int_local_to_t
219 #define bustype_ODY_MRML_INT_LOCAL_TO CSR_TYPE_RSL
220 #define basename_ODY_MRML_INT_LOCAL_TO "MRML_INT_LOCAL_TO"
221 #define device_bar_ODY_MRML_INT_LOCAL_TO 0x0 /* PF_BAR0 */
222 #define busnum_ODY_MRML_INT_LOCAL_TO 0
223 #define arguments_ODY_MRML_INT_LOCAL_TO -1, -1, -1, -1
224
225 /**
226 * Register (RSL) mrml_int_sum
227 *
228 * MRML Interrupt Summary Register
229 * This register contains the different interrupt summary bits of the MRML.
230 */
231 union ody_mrml_int_sum {
232 uint64_t u;
233 struct ody_mrml_int_sum_s {
234 uint64_t ocx_toe : 1;
235 uint64_t local_toe : 1;
236 uint64_t gibm : 1;
237 uint64_t reserved_3_63 : 61;
238 } s;
239 /* struct ody_mrml_int_sum_s cn; */
240 };
241 typedef union ody_mrml_int_sum ody_mrml_int_sum_t;
242
243 #define ODY_MRML_INT_SUM ODY_MRML_INT_SUM_FUNC()
244 static inline uint64_t ODY_MRML_INT_SUM_FUNC(void) __attribute__ ((pure, always_inline));
ODY_MRML_INT_SUM_FUNC(void)245 static inline uint64_t ODY_MRML_INT_SUM_FUNC(void)
246 {
247 return 0x87e0fc000810ll;
248 }
249
250 #define typedef_ODY_MRML_INT_SUM ody_mrml_int_sum_t
251 #define bustype_ODY_MRML_INT_SUM CSR_TYPE_RSL
252 #define basename_ODY_MRML_INT_SUM "MRML_INT_SUM"
253 #define device_bar_ODY_MRML_INT_SUM 0x0 /* PF_BAR0 */
254 #define busnum_ODY_MRML_INT_SUM 0
255 #define arguments_ODY_MRML_INT_SUM -1, -1, -1, -1
256
257 /**
258 * Register (RSL) mrml_int_sum_w1s
259 *
260 * MRML Interrupt Set Register
261 * This register sets interrupt bits.
262 */
263 union ody_mrml_int_sum_w1s {
264 uint64_t u;
265 struct ody_mrml_int_sum_w1s_s {
266 uint64_t ocx_toe : 1;
267 uint64_t local_toe : 1;
268 uint64_t gibm : 1;
269 uint64_t reserved_3_63 : 61;
270 } s;
271 /* struct ody_mrml_int_sum_w1s_s cn; */
272 };
273 typedef union ody_mrml_int_sum_w1s ody_mrml_int_sum_w1s_t;
274
275 #define ODY_MRML_INT_SUM_W1S ODY_MRML_INT_SUM_W1S_FUNC()
276 static inline uint64_t ODY_MRML_INT_SUM_W1S_FUNC(void) __attribute__ ((pure, always_inline));
ODY_MRML_INT_SUM_W1S_FUNC(void)277 static inline uint64_t ODY_MRML_INT_SUM_W1S_FUNC(void)
278 {
279 return 0x87e0fc000818ll;
280 }
281
282 #define typedef_ODY_MRML_INT_SUM_W1S ody_mrml_int_sum_w1s_t
283 #define bustype_ODY_MRML_INT_SUM_W1S CSR_TYPE_RSL
284 #define basename_ODY_MRML_INT_SUM_W1S "MRML_INT_SUM_W1S"
285 #define device_bar_ODY_MRML_INT_SUM_W1S 0x0 /* PF_BAR0 */
286 #define busnum_ODY_MRML_INT_SUM_W1S 0
287 #define arguments_ODY_MRML_INT_SUM_W1S -1, -1, -1, -1
288
289 /**
290 * Register (RSL) mrml_msix_pba#
291 *
292 * MRML MSI-X Pending Bit Array Registers
293 * This register is the MSI-X PBA table; the bit number is indexed by the MRML_INT_VEC_E enumeration.
294 */
295 union ody_mrml_msix_pbax {
296 uint64_t u;
297 struct ody_mrml_msix_pbax_s {
298 uint64_t pend : 64;
299 } s;
300 /* struct ody_mrml_msix_pbax_s cn; */
301 };
302 typedef union ody_mrml_msix_pbax ody_mrml_msix_pbax_t;
303
304 static inline uint64_t ODY_MRML_MSIX_PBAX(uint64_t a) __attribute__ ((pure, always_inline));
ODY_MRML_MSIX_PBAX(uint64_t a)305 static inline uint64_t ODY_MRML_MSIX_PBAX(uint64_t a)
306 {
307 if (a == 0)
308 return 0x87e0fcff0000ll;
309 __ody_csr_fatal("MRML_MSIX_PBAX", 1, a, 0, 0, 0, 0, 0);
310 }
311
312 #define typedef_ODY_MRML_MSIX_PBAX(a) ody_mrml_msix_pbax_t
313 #define bustype_ODY_MRML_MSIX_PBAX(a) CSR_TYPE_RSL
314 #define basename_ODY_MRML_MSIX_PBAX(a) "MRML_MSIX_PBAX"
315 #define device_bar_ODY_MRML_MSIX_PBAX(a) 0x4 /* PF_BAR4 */
316 #define busnum_ODY_MRML_MSIX_PBAX(a) (a)
317 #define arguments_ODY_MRML_MSIX_PBAX(a) (a), -1, -1, -1
318
319 /**
320 * Register (RSL) mrml_msix_vec#_addr
321 *
322 * MRML MSI-X Vector-Table Address Register
323 * This register is the MSI-X vector table, indexed by the MRML_INT_VEC_E enumeration.
324 */
325 union ody_mrml_msix_vecx_addr {
326 uint64_t u;
327 struct ody_mrml_msix_vecx_addr_s {
328 uint64_t secvec : 1;
329 uint64_t reserved_1 : 1;
330 uint64_t addr : 51;
331 uint64_t reserved_53_63 : 11;
332 } s;
333 /* struct ody_mrml_msix_vecx_addr_s cn; */
334 };
335 typedef union ody_mrml_msix_vecx_addr ody_mrml_msix_vecx_addr_t;
336
337 static inline uint64_t ODY_MRML_MSIX_VECX_ADDR(uint64_t a) __attribute__ ((pure, always_inline));
ODY_MRML_MSIX_VECX_ADDR(uint64_t a)338 static inline uint64_t ODY_MRML_MSIX_VECX_ADDR(uint64_t a)
339 {
340 if (a == 0)
341 return 0x87e0fcf00000ll;
342 __ody_csr_fatal("MRML_MSIX_VECX_ADDR", 1, a, 0, 0, 0, 0, 0);
343 }
344
345 #define typedef_ODY_MRML_MSIX_VECX_ADDR(a) ody_mrml_msix_vecx_addr_t
346 #define bustype_ODY_MRML_MSIX_VECX_ADDR(a) CSR_TYPE_RSL
347 #define basename_ODY_MRML_MSIX_VECX_ADDR(a) "MRML_MSIX_VECX_ADDR"
348 #define device_bar_ODY_MRML_MSIX_VECX_ADDR(a) 0x4 /* PF_BAR4 */
349 #define busnum_ODY_MRML_MSIX_VECX_ADDR(a) (a)
350 #define arguments_ODY_MRML_MSIX_VECX_ADDR(a) (a), -1, -1, -1
351
352 /**
353 * Register (RSL) mrml_msix_vec#_ctl
354 *
355 * MRML MSI-X Vector-Table Control and Data Register
356 * This register is the MSI-X vector table, indexed by the MRML_INT_VEC_E enumeration.
357 */
358 union ody_mrml_msix_vecx_ctl {
359 uint64_t u;
360 struct ody_mrml_msix_vecx_ctl_s {
361 uint64_t data : 32;
362 uint64_t mask : 1;
363 uint64_t reserved_33_63 : 31;
364 } s;
365 /* struct ody_mrml_msix_vecx_ctl_s cn; */
366 };
367 typedef union ody_mrml_msix_vecx_ctl ody_mrml_msix_vecx_ctl_t;
368
369 static inline uint64_t ODY_MRML_MSIX_VECX_CTL(uint64_t a) __attribute__ ((pure, always_inline));
ODY_MRML_MSIX_VECX_CTL(uint64_t a)370 static inline uint64_t ODY_MRML_MSIX_VECX_CTL(uint64_t a)
371 {
372 if (a == 0)
373 return 0x87e0fcf00008ll;
374 __ody_csr_fatal("MRML_MSIX_VECX_CTL", 1, a, 0, 0, 0, 0, 0);
375 }
376
377 #define typedef_ODY_MRML_MSIX_VECX_CTL(a) ody_mrml_msix_vecx_ctl_t
378 #define bustype_ODY_MRML_MSIX_VECX_CTL(a) CSR_TYPE_RSL
379 #define basename_ODY_MRML_MSIX_VECX_CTL(a) "MRML_MSIX_VECX_CTL"
380 #define device_bar_ODY_MRML_MSIX_VECX_CTL(a) 0x4 /* PF_BAR4 */
381 #define busnum_ODY_MRML_MSIX_VECX_CTL(a) (a)
382 #define arguments_ODY_MRML_MSIX_VECX_CTL(a) (a), -1, -1, -1
383
384 /**
385 * Register (RSL) mrml_ncb#_permit
386 *
387 * MRML NCB Bus Permit Registers
388 * This register sets the permissions for access to NCBDIDs address bits \<43:36\>.
389 * Also see and program identically IOBN_NCB()_PERMIT.
390 */
391 union ody_mrml_ncbx_permit {
392 uint64_t u;
393 struct ody_mrml_ncbx_permit_s {
394 uint64_t sec_dis : 1;
395 uint64_t nsec_dis : 1;
396 uint64_t xcp0_dis : 1;
397 uint64_t xcp1_dis : 1;
398 uint64_t xcp2_dis : 1;
399 uint64_t reserved_5_6 : 2;
400 uint64_t kill : 1;
401 uint64_t lock : 1;
402 uint64_t reserved_9_63 : 55;
403 } s;
404 /* struct ody_mrml_ncbx_permit_s cn; */
405 };
406 typedef union ody_mrml_ncbx_permit ody_mrml_ncbx_permit_t;
407
408 static inline uint64_t ODY_MRML_NCBX_PERMIT(uint64_t a) __attribute__ ((pure, always_inline));
ODY_MRML_NCBX_PERMIT(uint64_t a)409 static inline uint64_t ODY_MRML_NCBX_PERMIT(uint64_t a)
410 {
411 if (a <= 255)
412 return 0x87e0fc020000ll + 8ll * ((a) & 0xff);
413 __ody_csr_fatal("MRML_NCBX_PERMIT", 1, a, 0, 0, 0, 0, 0);
414 }
415
416 #define typedef_ODY_MRML_NCBX_PERMIT(a) ody_mrml_ncbx_permit_t
417 #define bustype_ODY_MRML_NCBX_PERMIT(a) CSR_TYPE_RSL
418 #define basename_ODY_MRML_NCBX_PERMIT(a) "MRML_NCBX_PERMIT"
419 #define device_bar_ODY_MRML_NCBX_PERMIT(a) 0x0 /* PF_BAR0 */
420 #define busnum_ODY_MRML_NCBX_PERMIT(a) (a)
421 #define arguments_ODY_MRML_NCBX_PERMIT(a) (a), -1, -1, -1
422
423 /**
424 * Register (RSL) mrml_rsl#_permit
425 *
426 * MRML RSL Bus Permit Registers
427 * This register sets the permissions for access to the device's physical address bits \<33:24\>.
428 */
429 union ody_mrml_rslx_permit {
430 uint64_t u;
431 struct ody_mrml_rslx_permit_s {
432 uint64_t sec_dis : 1;
433 uint64_t nsec_dis : 1;
434 uint64_t xcp0_dis : 1;
435 uint64_t xcp1_dis : 1;
436 uint64_t xcp2_dis : 1;
437 uint64_t reserved_5_6 : 2;
438 uint64_t kill : 1;
439 uint64_t lock : 1;
440 uint64_t reserved_9_63 : 55;
441 } s;
442 /* struct ody_mrml_rslx_permit_s cn; */
443 };
444 typedef union ody_mrml_rslx_permit ody_mrml_rslx_permit_t;
445
446 static inline uint64_t ODY_MRML_RSLX_PERMIT(uint64_t a) __attribute__ ((pure, always_inline));
ODY_MRML_RSLX_PERMIT(uint64_t a)447 static inline uint64_t ODY_MRML_RSLX_PERMIT(uint64_t a)
448 {
449 if (a <= 1023)
450 return 0x87e0fc010000ll + 8ll * ((a) & 0x3ff);
451 __ody_csr_fatal("MRML_RSLX_PERMIT", 1, a, 0, 0, 0, 0, 0);
452 }
453
454 #define typedef_ODY_MRML_RSLX_PERMIT(a) ody_mrml_rslx_permit_t
455 #define bustype_ODY_MRML_RSLX_PERMIT(a) CSR_TYPE_RSL
456 #define basename_ODY_MRML_RSLX_PERMIT(a) "MRML_RSLX_PERMIT"
457 #define device_bar_ODY_MRML_RSLX_PERMIT(a) 0x0 /* PF_BAR0 */
458 #define busnum_ODY_MRML_RSLX_PERMIT(a) (a)
459 #define arguments_ODY_MRML_RSLX_PERMIT(a) (a), -1, -1, -1
460
461 /**
462 * Register (RSL) mrml_scfg
463 *
464 * MRML RSL Secure Configuration Register
465 */
466 union ody_mrml_scfg {
467 uint64_t u;
468 struct ody_mrml_scfg_s {
469 uint64_t reserved_0_63 : 64;
470 } s;
471 /* struct ody_mrml_scfg_s cn; */
472 };
473 typedef union ody_mrml_scfg ody_mrml_scfg_t;
474
475 #define ODY_MRML_SCFG ODY_MRML_SCFG_FUNC()
476 static inline uint64_t ODY_MRML_SCFG_FUNC(void) __attribute__ ((pure, always_inline));
ODY_MRML_SCFG_FUNC(void)477 static inline uint64_t ODY_MRML_SCFG_FUNC(void)
478 {
479 return 0x87e0fc000000ll;
480 }
481
482 #define typedef_ODY_MRML_SCFG ody_mrml_scfg_t
483 #define bustype_ODY_MRML_SCFG CSR_TYPE_RSL
484 #define basename_ODY_MRML_SCFG "MRML_SCFG"
485 #define device_bar_ODY_MRML_SCFG 0x0 /* PF_BAR0 */
486 #define busnum_ODY_MRML_SCFG 0
487 #define arguments_ODY_MRML_SCFG -1, -1, -1, -1
488
489 #endif /* __ODY_CSRS_MRML_H__ */
490