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Searched refs:WRITE_MASK_SET (Results 1 – 2 of 2) sorted by relevance

/rk3399_ARM-atf/plat/rockchip/rk3568/drivers/pmu/
H A Dpmu.c62 mmio_write_32(PMUGRF_BASE + PMU_GRF_SOC_CON(0), WRITE_MASK_SET(BIT(7))); in pmu_pmic_sleep_mode_config()
69 mmio_write_32(PMU_BASE + PMU_WAKEUP_INT_CON, WRITE_MASK_SET(BIT(WAKEUP_GPIO0_INT_EN))); in pmu_wakeup_source_config()
88 mmio_write_32(PMU_BASE + PMU_PLLPD_CON, WRITE_MASK_SET(pll_id)); in pmu_pll_powerdown_config()
172 mmio_write_32(PMU_BASE + PMU_BUS_IDLE_CON0, WRITE_MASK_SET(pmu_bus_idle_con0)); in pmu_pd_powerdown_config()
173 mmio_write_32(PMU_BASE + PMU_BUS_IDLE_CON1, WRITE_MASK_SET(pmu_bus_idle_con1)); in pmu_pd_powerdown_config()
181 mmio_write_32(PMU_BASE + PMU_VOL_GATE_SFTCON, WRITE_MASK_SET(BIT(VD_NPU_ENA))); in pmu_pd_powerdown_config()
207 mmio_write_32(PMU_BASE + PMU_DDR_PWR_CON, WRITE_MASK_SET(pmu_ddr_pwr_con)); in pmu_ddr_suspend_config()
209 mmio_write_32(PMU_BASE + PMU_PLLPD_CON, WRITE_MASK_SET(BIT(DPLL_PD_ENA))); in pmu_ddr_suspend_config()
247 mmio_write_32(PMU_BASE + PMU_DSU_PWR_CON, WRITE_MASK_SET(pmu_dsu_pwr_con)); in pmu_dsu_suspend_config()
314 mmio_write_32(PMU_BASE + PMU_CRU_PWR_CON, WRITE_MASK_SET(pmu_cru_pwr_con)); in pvtm_32k_config()
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H A Dpmu.h104 #define WRITE_MASK_SET(value) ((value << 16) | value) macro