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Searched refs:WRITE_MASK_CLR (Results 1 – 2 of 2) sorted by relevance

/rk3399_ARM-atf/plat/rockchip/rk3568/drivers/pmu/
H A Dpmu.c183 mmio_write_32(PMU_BASE + PMU_PWR_CON, WRITE_MASK_CLR(BIT(PWRDN_BYPASS))); in pmu_pd_powerdown_config()
184 mmio_write_32(PMU_BASE + PMU_PWR_CON, WRITE_MASK_CLR(BIT(BUS_BYPASS))); in pmu_pd_powerdown_config()
210 mmio_write_32(PMU_BASE + PMU_PWR_CON, WRITE_MASK_CLR(BIT(DDR_BYPASS))); in pmu_ddr_suspend_config()
248 mmio_write_32(PMU_BASE + PMU_PWR_CON, WRITE_MASK_CLR(BIT(DSU_BYPASS))); in pmu_dsu_suspend_config()
H A Dpmu.h105 #define WRITE_MASK_CLR(value) ((value << 16)) macro