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Searched refs:UFS_SYS_PSW_POWER_CTRL_REG (Results 1 – 3 of 3) sorted by relevance

/rk3399_ARM-atf/plat/hisilicon/hikey960/
H A Dhikey960_bl1_setup.c130 mmio_setbits_32(UFS_SYS_PSW_POWER_CTRL_REG, BIT_UFS_PSW_MTCMOS_EN); in hikey960_ufs_reset()
152 mmio_clrbits_32(UFS_SYS_PSW_POWER_CTRL_REG, BIT_UFS_PSW_ISO_CTRL); in hikey960_ufs_reset()
H A Dhikey960_bl2_setup.c108 mmio_setbits_32(UFS_SYS_PSW_POWER_CTRL_REG, BIT_UFS_PSW_MTCMOS_EN); in hikey960_ufs_reset()
130 mmio_clrbits_32(UFS_SYS_PSW_POWER_CTRL_REG, BIT_UFS_PSW_ISO_CTRL); in hikey960_ufs_reset()
/rk3399_ARM-atf/plat/hisilicon/hikey960/include/
H A Dhi3660.h318 #define UFS_SYS_PSW_POWER_CTRL_REG (UFS_SYS_REG_BASE + 0x004) macro