1 /* SPDX-License-Identifier: BSD-3-Clause */ 2 /* 3 * Cadence DDR Driver - Minimal Macros 4 * 5 * Copyright (C) 2012-2026 Cadence Design Systems, Inc. 6 * Copyright (C) 2018-2026 Texas Instruments Incorporated - https://www.ti.com/ 7 * 8 * This file contains only the macros actually used by the AM62L DDR driver. 9 * Reduced from 6,796 macros to 80 macros (1.2% of original). 10 */ 11 12 #ifndef LPDDR4_MACROS_H 13 #define LPDDR4_MACROS_H 14 15 /* Controller Register Field Masks */ 16 #define TI_LPDDR4__DENALI_CTL_0__DRAM_CLASS_MASK 0x00000F00U 17 #define TI_LPDDR4__DENALI_CTL_0__START_MASK 0x00000001U 18 #define TI_LPDDR4__DENALI_CTL_337__INT_STATUS_LOWPOWER_MASK 0xFFFF0000U 19 #define TI_LPDDR4__DENALI_CTL_341__INT_STATUS_BIST_MASK 0x00FF0000U 20 #define TI_LPDDR4__DENALI_CTL_341__INT_STATUS_MISC_MASK 0x0000FFFFU 21 #define TI_LPDDR4__DENALI_CTL_342__INT_STATUS_DFI_MASK 0x000000FFU 22 #define TI_LPDDR4__DENALI_CTL_342__INT_STATUS_FREQ_MASK 0x00FF0000U 23 #define TI_LPDDR4__DENALI_CTL_342__INT_STATUS_INIT_MASK 0xFF000000U 24 #define TI_LPDDR4__DENALI_CTL_343__INT_STATUS_PARITY_MASK 0x0000FF00U 25 #define TI_LPDDR4__DENALI_CTL_345__INT_ACK_LOWPOWER_MASK 0xFFFF0000U 26 #define TI_LPDDR4__DENALI_CTL_349__INT_ACK_BIST_MASK 0x00FF0000U 27 #define TI_LPDDR4__DENALI_CTL_350__INT_ACK_FREQ_MASK 0x00FF0000U 28 #define TI_LPDDR4__DENALI_CTL_350__INT_ACK_INIT_MASK 0xFF000000U 29 #define TI_LPDDR4__DENALI_CTL_351__INT_ACK_PARITY_MASK 0x0000FF00U 30 31 /* PI Register Field Masks */ 32 #define TI_LPDDR4__DENALI_PI_0__PI_START_MASK 0x00000001U 33 #define TI_LPDDR4__DENALI_PI_3__PI_NORMAL_LVL_SEQ_MASK 0x01000000U 34 #define TI_LPDDR4__DENALI_PI_4__PI_INIT_LVL_EN_MASK 0x00000001U 35 36 /* Driver-level field masks (for CPS_FLD_MASK token concatenation) */ 37 #define TI_LPDDR4__DRAM_CLASS__FLD_MASK 0x00000F00U 38 #define TI_LPDDR4__START__FLD_MASK 0x00000001U 39 #define TI_LPDDR4__INT_STATUS_LOWPOWER__FLD_MASK 0xFFFF0000U 40 #define TI_LPDDR4__INT_STATUS_BIST__FLD_MASK 0x00FF0000U 41 #define TI_LPDDR4__INT_STATUS_MISC__FLD_MASK 0x0000FFFFU 42 #define TI_LPDDR4__INT_STATUS_DFI__FLD_MASK 0x000000FFU 43 #define TI_LPDDR4__INT_STATUS_FREQ__FLD_MASK 0x00FF0000U 44 #define TI_LPDDR4__INT_STATUS_INIT__FLD_MASK 0xFF000000U 45 #define TI_LPDDR4__INT_STATUS_PARITY__FLD_MASK 0x0000FF00U 46 #define TI_LPDDR4__INT_ACK_LOWPOWER__FLD_MASK 0xFFFF0000U 47 #define TI_LPDDR4__INT_ACK_BIST__FLD_MASK 0x00FF0000U 48 #define TI_LPDDR4__INT_ACK_FREQ__FLD_MASK 0x00FF0000U 49 #define TI_LPDDR4__INT_ACK_INIT__FLD_MASK 0xFF000000U 50 #define TI_LPDDR4__INT_ACK_PARITY__FLD_MASK 0x0000FF00U 51 #define TI_LPDDR4__PI_START__FLD_MASK 0x00000001U 52 #define TI_LPDDR4__PI_NORMAL_LVL_SEQ__FLD_MASK 0x01000000U 53 #define TI_LPDDR4__PI_INIT_LVL_EN__FLD_MASK 0x00000001U 54 55 /* Driver-level macros - Basic Configuration */ 56 #define TI_LPDDR4__START__REG DENALI_CTL[0] 57 58 /* Driver-level macros - Interrupt Status */ 59 #define TI_LPDDR4__INT_STATUS_MASTER__REG DENALI_CTL[334] 60 #define TI_LPDDR4__INT_STATUS_TIMEOUT__REG DENALI_CTL[336] 61 #define TI_LPDDR4__INT_STATUS_LOWPOWER__REG DENALI_CTL[337] 62 #define TI_LPDDR4__INT_STATUS_TRAINING__REG DENALI_CTL[339] 63 #define TI_LPDDR4__INT_STATUS_USERIF__REG DENALI_CTL[340] 64 #define TI_LPDDR4__INT_STATUS_BIST__REG DENALI_CTL[341] 65 #define TI_LPDDR4__INT_STATUS_MISC__REG DENALI_CTL[341] 66 #define TI_LPDDR4__INT_STATUS_DFI__REG DENALI_CTL[342] 67 #define TI_LPDDR4__INT_STATUS_FREQ__REG DENALI_CTL[342] 68 #define TI_LPDDR4__INT_STATUS_INIT__REG DENALI_CTL[342] 69 #define TI_LPDDR4__INT_STATUS_MODE__REG DENALI_CTL[343] 70 #define TI_LPDDR4__INT_STATUS_PARITY__REG DENALI_CTL[343] 71 72 /* Driver-level macros - Interrupt Acknowledge */ 73 #define TI_LPDDR4__INT_ACK_TIMEOUT__REG DENALI_CTL[344] 74 #define TI_LPDDR4__INT_ACK_LOWPOWER__REG DENALI_CTL[345] 75 #define TI_LPDDR4__INT_ACK_TRAINING__REG DENALI_CTL[347] 76 #define TI_LPDDR4__INT_ACK_USERIF__REG DENALI_CTL[348] 77 #define TI_LPDDR4__INT_ACK_BIST__REG DENALI_CTL[349] 78 #define TI_LPDDR4__INT_ACK_MISC__REG DENALI_CTL[349] 79 #define TI_LPDDR4__INT_ACK_DFI__REG DENALI_CTL[350] 80 #define TI_LPDDR4__INT_ACK_FREQ__REG DENALI_CTL[350] 81 #define TI_LPDDR4__INT_ACK_INIT__REG DENALI_CTL[350] 82 #define TI_LPDDR4__INT_ACK_MODE__REG DENALI_CTL[351] 83 #define TI_LPDDR4__INT_ACK_PARITY__REG DENALI_CTL[351] 84 85 /* Driver-level macros - PI (PHY Independent) */ 86 #define TI_LPDDR4__PI_START__REG DENALI_PI[0] 87 #define TI_LPDDR4__PI_NORMAL_LVL_SEQ__REG DENALI_PI[3] 88 #define TI_LPDDR4__PI_INIT_LVL_EN__REG DENALI_PI[4] 89 #define TI_LPDDR4__PI_INT_STATUS__REG DENALI_PI[83] 90 #define TI_LPDDR4__PI_INT_ACK__REG DENALI_PI[84] 91 92 #endif /* LPDDR4_MACROS_H */ 93