Searched refs:TI_LPDDR4_BIT_MASK (Results 1 – 3 of 3) sorted by relevance
197 TI_LPDDR4_BIT_MASK) > 0U) && in ti_lpddr4_checkctlinterrupt()199 TI_LPDDR4_BIT_MASK) > 0U) && in ti_lpddr4_checkctlinterrupt()203 TI_LPDDR4_BIT_MASK) > 0U) && in ti_lpddr4_checkctlinterrupt()240 TI_LPDDR4_BIT_MASK << ctlintmap[intr].int_shift; in ti_lpddr4_ackctlinterrupt()246 (TI_LPDDR4_BIT_MASK << ctlintmap[intr].int_shift)); in ti_lpddr4_ackctlinterrupt()255 TI_LPDDR4_BIT_MASK << ctlintmap[intr].int_shift; in ti_lpddr4_ackctlinterrupt()263 TI_LPDDR4_BIT_MASK << ctlintmap[intr].int_shift; in ti_lpddr4_ackctlinterrupt()271 TI_LPDDR4_BIT_MASK << ctlintmap[intr].int_shift; in ti_lpddr4_ackctlinterrupt()276 TI_LPDDR4_BIT_MASK << ctlintmap[intr].int_shift); in ti_lpddr4_ackctlinterrupt()286 TI_LPDDR4_BIT_MASK << ctlintmap[intr].int_shift; in ti_lpddr4_ackctlinterrupt()[all …]
19 #define TI_LPDDR4_BIT_MASK (0x1U) macro
306 *irqstatus = (((phyindepirqstatus >> (uint32_t)intr) & TI_LPDDR4_BIT_MASK) > 0U); in ti_lpddr4_checkphyindepinterrupt()321 regval = (TI_LPDDR4_BIT_MASK << (uint32_t)intr); in ti_lpddr4_ackphyindepinterrupt()