Searched refs:TEGRA_MISC_BASE (Results 1 – 7 of 7) sorted by relevance
57 mmio_write_32(TEGRA_MISC_BASE + MISCREG_AA64_RST_LOW, addr_low); in plat_secondary_setup()58 assert(mmio_read_32(TEGRA_MISC_BASE + MISCREG_AA64_RST_LOW) == addr_low); in plat_secondary_setup()59 mmio_write_32(TEGRA_MISC_BASE + MISCREG_AA64_RST_HIGH, addr_high); in plat_secondary_setup()60 assert(mmio_read_32(TEGRA_MISC_BASE + MISCREG_AA64_RST_HIGH) == addr_high); in plat_secondary_setup()
18 return mmio_read_32((uintptr_t)TEGRA_MISC_BASE + off); in tegra_misc_read_32()
89 MAP_REGION_FLAT(TEGRA_MISC_BASE, 0x4000U, /* 16KB */
138 val = mmio_read_32(TEGRA_MISC_BASE + MISCREG_PFCFG); in tegra_soc_pwr_domain_suspend()
23 seed = mmio_read_32(TEGRA_MISC_BASE + HARDWARE_REVISION_OFFSET); in plat_get_stack_protector_canary()
58 return mmio_read_32(TEGRA_MISC_BASE + HARDWARE_REVISION_OFFSET); in tegra_get_chipid()
65 #define TEGRA_MISC_BASE U(0x00100000) macro