1 /* 2 * Copyright (c) 2026, Qualcomm Technologies, Inc. and/or its subsidiaries. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef VMIDMT_TARGET_HWIO_H 8 #define VMIDMT_TARGET_HWIO_H 9 10 #include <kodiak_def.h> 11 12 #define TCSR_TCSR_REGS_REG_BASE (QTI_CORE_TOP_CSR_BASE + 0x000c0000) 13 #define TCSR_TCSR_REGS_REG_BASE_SIZE 0x30000 14 #define TCSR_TCSR_REGS_REG_BASE_USED 0x2f010 15 16 #define HWIO_TCSR_VMIDMT_CLIENT_NON_SEC_IRQ_STATUS_REG_0_ADDR \ 17 (TCSR_TCSR_REGS_REG_BASE + 0x2010) 18 #define HWIO_TCSR_VMIDMT_CLIENT_NON_SEC_IRQ_STATUS_REG_0_RMSK 0x3ffff 19 20 #define HWIO_TCSR_VMIDMT_CLIENT_NON_SEC_IRQ_ENABLE_0_REG_0_ADDR \ 21 (TCSR_TCSR_REGS_REG_BASE + 0x2050) 22 #define HWIO_TCSR_VMIDMT_CLIENT_NON_SEC_IRQ_ENABLE_0_REG_0_RMSK 0x3ffff 23 24 #define HWIO_TCSR_VMIDMT_CFG_NON_SEC_IRQ_STATUS_REG_0_ADDR \ 25 (TCSR_TCSR_REGS_REG_BASE + 0x3000) 26 #define HWIO_TCSR_VMIDMT_CFG_NON_SEC_IRQ_STATUS_REG_0_RMSK 0x3ffff 27 28 #define HWIO_TCSR_VMIDMT_CFG_NON_SEC_IRQ_ENABLE_0_REG_0_ADDR \ 29 (TCSR_TCSR_REGS_REG_BASE + 0x3040) 30 #define HWIO_TCSR_VMIDMT_CFG_NON_SEC_IRQ_ENABLE_0_REG_0_RMSK 0x3ffff 31 32 #define HWIO_TCSR_VMIDMT_CLIENT_SEC_IRQ_STATUS_REG_0_ADDR \ 33 (TCSR_TCSR_REGS_REG_BASE + 0x4010) 34 #define HWIO_TCSR_VMIDMT_CLIENT_SEC_IRQ_STATUS_REG_0_RMSK 0x3ffff 35 36 #define HWIO_TCSR_VMIDMT_CLIENT_SEC_IRQ_ENABLE_0_REG_0_ADDR \ 37 (TCSR_TCSR_REGS_REG_BASE + 0x4050) 38 #define HWIO_TCSR_VMIDMT_CLIENT_SEC_IRQ_ENABLE_0_REG_0_RMSK 0x3ffff 39 40 #define HWIO_TCSR_VMIDMT_CFG_SEC_IRQ_STATUS_REG_0_ADDR \ 41 (TCSR_TCSR_REGS_REG_BASE + 0x5000) 42 #define HWIO_TCSR_VMIDMT_CFG_SEC_IRQ_STATUS_REG_0_RMSK 0x3ffff 43 44 #define HWIO_TCSR_VMIDMT_CFG_SEC_IRQ_ENABLE_0_REG_0_ADDR \ 45 (TCSR_TCSR_REGS_REG_BASE + 0x5040) 46 #define HWIO_TCSR_VMIDMT_CFG_SEC_IRQ_ENABLE_0_REG_0_RMSK 0x3ffff 47 48 #ifndef HWIO_TCSR_SS_VMIDMT_CLIENT_SEC_INTR_ADDR 49 #define HWIO_TCSR_SS_VMIDMT_CLIENT_SEC_INTR_ADDR \ 50 HWIO_TCSR_VMIDMT_CLIENT_SEC_IRQ_STATUS_REG_0_ADDR 51 #define HWIO_TCSR_SS_VMIDMT_CLIENT_SEC_INTR_RMSK \ 52 HWIO_TCSR_VMIDMT_CLIENT_SEC_IRQ_STATUS_REG_0_RMSK 53 #endif 54 55 #ifndef HWIO_TCSR_SS_VMIDMT_CLIENT_NON_SEC_INTR_ADDR 56 #define HWIO_TCSR_SS_VMIDMT_CLIENT_NON_SEC_INTR_ADDR \ 57 HWIO_TCSR_VMIDMT_CLIENT_NON_SEC_IRQ_STATUS_REG_0_ADDR 58 #define HWIO_TCSR_SS_VMIDMT_CLIENT_NON_SEC_INTR_RMSK \ 59 HWIO_TCSR_VMIDMT_CLIENT_NON_SEC_IRQ_STATUS_REG_0_RMSK 60 #endif 61 62 #ifndef HWIO_TCSR_SS_VMIDMT_CFG_SEC_INTR_ADDR 63 #define HWIO_TCSR_SS_VMIDMT_CFG_SEC_INTR_ADDR \ 64 HWIO_TCSR_VMIDMT_CFG_SEC_IRQ_STATUS_REG_0_ADDR 65 #define HWIO_TCSR_SS_VMIDMT_CFG_SEC_INTR_RMSK \ 66 HWIO_TCSR_VMIDMT_CFG_SEC_IRQ_STATUS_REG_0_RMSK 67 #endif 68 69 #ifndef HWIO_TCSR_SS_VMIDMT_CFG_NON_SEC_INTR_ADDR 70 #define HWIO_TCSR_SS_VMIDMT_CFG_NON_SEC_INTR_ADDR \ 71 HWIO_TCSR_VMIDMT_CFG_NON_SEC_IRQ_STATUS_REG_0_ADDR 72 #define HWIO_TCSR_SS_VMIDMT_CFG_NON_SEC_INTR_RMSK \ 73 HWIO_TCSR_VMIDMT_CFG_NON_SEC_IRQ_STATUS_REG_0_RMSK 74 #endif 75 76 #define HWIO_TCSR_SS_VMIDMT_CLIENT_SEC_INTR_ENABLE_ADDR \ 77 HWIO_TCSR_VMIDMT_CLIENT_SEC_IRQ_ENABLE_0_REG_0_ADDR 78 79 #define HWIO_TCSR_SS_VMIDMT_CLIENT_NON_SEC_INTR_ENABLE_ADDR \ 80 HWIO_TCSR_VMIDMT_CLIENT_NON_SEC_IRQ_ENABLE_0_REG_0_ADDR 81 82 #define HWIO_TCSR_SS_VMIDMT_CFG_SEC_INTR_ENABLE_ADDR \ 83 HWIO_TCSR_VMIDMT_CFG_SEC_IRQ_ENABLE_0_REG_0_ADDR 84 85 #define HWIO_TCSR_SS_VMIDMT_CFG_NON_SEC_INTR_ENABLE_ADDR \ 86 HWIO_TCSR_VMIDMT_CFG_NON_SEC_IRQ_ENABLE_0_REG_0_ADDR 87 88 #endif /* VMIDMT_TARGET_HWIO_H */ 89