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Searched refs:SYS_SGRF_FW_BASE (Results 1 – 3 of 3) sorted by relevance

/rk3399_ARM-atf/plat/rockchip/rk3576/drivers/secure/
H A Dfirewall.c534 mmio_write_32(SYS_SGRF_FW_BASE + FW_SGRF_MST_DOMAIN_CON(i), in fw_config_buf_flush()
542 mmio_write_32(SYS_SGRF_FW_BASE + FW_SGRF_BUS_SLV_CON(i), in fw_config_buf_flush()
546 mmio_write_32(SYS_SGRF_FW_BASE + FW_SGRF_TOP_SLV_CON(i), in fw_config_buf_flush()
550 mmio_write_32(SYS_SGRF_FW_BASE + FW_SGRF_CENTER_SLV_CON(i), in fw_config_buf_flush()
554 mmio_write_32(SYS_SGRF_FW_BASE + FW_SGRF_CCI_SLV_CON(i), in fw_config_buf_flush()
558 mmio_write_32(SYS_SGRF_FW_BASE + FW_SGRF_PHP_SLV_CON(i), in fw_config_buf_flush()
561 mmio_write_32(SYS_SGRF_FW_BASE + FW_SGRF_GPU_SLV_CON, in fw_config_buf_flush()
565 mmio_write_32(SYS_SGRF_FW_BASE + FW_SGRF_NPU_SLV_CON(i), in fw_config_buf_flush()
574 mmio_write_32(SYS_SGRF_FW_BASE + FW_SGRF_DDR_RGN(i), in fw_config_buf_flush()
577 mmio_write_32(SYS_SGRF_FW_BASE + FW_SGRF_DDR_SIZE, fw_config_buf.ddr_size); in fw_config_buf_flush()
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/rk3399_ARM-atf/plat/rockchip/rk3576/
H A Drk3576_def.h33 #define SYS_SGRF_FW_BASE 0x26005000 macro
/rk3399_ARM-atf/plat/rockchip/rk3576/drivers/pmu/
H A Dpmu.c686 mmio_write_32(SYS_SGRF_FW_BASE + FW_SGRF_KEYUPD_CON0, 0x03ff0000); in pmu_sleep_config()
697 mmio_write_32(SYS_SGRF_FW_BASE + FW_SGRF_KEYUPD_CON1, in pmu_sleep_config()
699 mmio_write_32(SYS_SGRF_FW_BASE + FW_SGRF_KEYUPD_CON1, in pmu_sleep_config()