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Searched refs:SIDEBANDMGR_FLAGOUTSET0_REG (Results 1 – 1 of 1) sorted by relevance

/rk3399_ARM-atf/plat/intel/soc/agilex5/soc/
H A Dagilex5_ddr.c39 #define SIDEBANDMGR_FLAGOUTSET0_REG (SOCFPGA_F2SDRAM_MGR_ADDRESS \ macro
340 mmio_setbits_32(SIDEBANDMGR_FLAGOUTSET0_REG, BIT(4)); in agilex5_ddr_init()
350 mmio_setbits_32(SIDEBANDMGR_FLAGOUTSET0_REG, BIT(5)); in agilex5_ddr_init()